/*
 * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
 * 
 * SPDX-License-Identifier: Apache-2.0
 * 
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 * 
 * http://www.apache.org/licenses/LICENSE-2.0
 * 
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * @file     R2401.h
 * @brief    CMSIS HeaderFile
 * @version  1
 * @date     11. April 2025
 * @note     Generated by SVDConv V3.3.42 on Friday, 11.04.2025 15:40:27
 *           from File 'Test/R2401.svd',
 *           last modified on Friday, 11.04.2025 07:40:26
 */



/** @addtogroup 
  * @{
  */


/** @addtogroup R2401
  * @{
  */


#ifndef R2401_H
#define R2401_H

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum {
/* =======================================  ARM Cortex-M4 Specific Interrupt Numbers  ======================================== */
  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
  MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
                                                     and No Match                                                              */
  BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
                                                     related Fault                                                             */
  UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
  DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
/* ===========================================  R2401 Specific Interrupt Numbers  ============================================ */
  eDIAG_LEVEL0_IRQn         =   0,              /*!< 0  eDIAG_LEVEL0                                                           */
  eDIAG_LEVEL1_IRQn         =   1,              /*!< 1  eDIAG_LEVEL1                                                           */
  RCC_IRQn                  =   2,              /*!< 2  RCC                                                                    */
  eDIAG_OC_IRQn             =   3,              /*!< 3  eDIAG_OC                                                               */
  FMC0_IRQn                 =   4,              /*!< 4  FMC0                                                                   */
  FMC1_IRQn                 =   5,              /*!< 5  FMC1                                                                   */
  TIM0_IRQn                 =   6,              /*!< 6  TIM0                                                                   */
  TIM1_IRQn                 =   7,              /*!< 7  TIM1                                                                   */
  TIM2_IRQn                 =   8,              /*!< 8  TIM2                                                                   */
  WWDG_IRQn                 =  10,              /*!< 10 WWDG                                                                   */
  LIN_IRQn                  =  11,              /*!< 11 LIN                                                                    */
  ADC0_IRQn                 =  12,              /*!< 12 ADC0                                                                   */
  ADC1_IRQn                 =  13,              /*!< 13 ADC1                                                                   */
  SPI0_IRQn                 =  14,              /*!< 14 SPI0                                                                   */
  SPI1_IRQn                 =  15,              /*!< 15 SPI1                                                                   */
  eCAP_IRQn                 =  16,              /*!< 16 eCAP                                                                   */
  ePWM_BRK_UP_TRG_COM_IRQn  =  17,              /*!< 17 ePWM_BRK_UP_TRG_COM                                                    */
  ePWM_CC_IRQn              =  18,              /*!< 18 ePWM_CC                                                                */
  eDIAG_CMP_IRQn            =  19,              /*!< 19 eDIAG_CMP                                                              */
  CAN_IRQ0_IRQn             =  20,              /*!< 20 CAN_IRQ0                                                               */
  IWDG_IRQn                 =  21,              /*!< 21 IWDG                                                                   */
  GPIOA_IRQn                =  22,              /*!< 22 GPIOA                                                                  */
  GPIOB_IRQn                =  23,              /*!< 23 GPIOB                                                                  */
  GPIOC_IRQn                =  24,              /*!< 24 GPIOC                                                                  */
  DMA_CH0_IRQn              =  25,              /*!< 25 DMA_CH0                                                                */
  DMA_CH1_2_IRQn            =  26,              /*!< 26 DMA_CH1_2                                                              */
  DMA_CH3_6_IRQn            =  27,              /*!< 27 DMA_CH3_6                                                              */
  CAN_IRQ1_IRQn             =  29               /*!< 29 CAN_IRQ1                                                               */
} IRQn_Type;



/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ===========================  Configuration of the ARM Cortex-M4 Processor and Core Peripherals  =========================== */
#define __CM4_REV                 0x0001U       /*!< CM4 Core Revision                                                         */
#define __NVIC_PRIO_BITS               4        /*!< Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
#define __MPU_PRESENT                  1        /*!< MPU present                                                               */
#define __FPU_PRESENT                  1        /*!< FPU present                                                               */


/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm4.h"                           /*!< ARM Cortex-M4 processor and core peripherals                              */
#include "system_R2401.h"                       /*!< R2401 System                                                              */

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif


/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                           FMC0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Flash Memory Controller of Eflash 0. (FMC0)
  */

typedef struct {                                /*!< (@ 0x50006000) FMC0 Structure                                             */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) Controller Register of Eflash                              */
    
    struct {
      __IOM uint32_t PRESCALER_CFG : 3;         /*!< [2..0] Clock Prescaler, set the clock of Flash to a proper level:         */
            uint32_t            : 21;
      __IOM uint32_t DPSTB_EN   : 1;            /*!< [24..24] 0 to enable FMC to go to deepsleep following CPU goes
                                                     to deepsleep1 to disable the function.                                    */
      __IOM uint32_t PreadyEn   : 1;            /*!< [25..25] PreadyEn                                                         */
            uint32_t            : 1;
      __IOM uint32_t FILTER_FF  : 1;            /*!< [27..27] When a FF is asked to be programed : 0, program the
                                                     FF1. pass by not-programing the FF                                        */
            uint32_t            : 4;
    } bit;
  } CR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) State Register 0 of Eflash                                 */
    
    struct {
      __IM  uint32_t STAR_ERR   : 1;            /*!< [0..0] startup reading config error                                       */
            uint32_t            : 3;
      __IM  uint32_t ECC_ERR    : 2;            /*!< [5..4] Ecc Error Type                                                     */
            uint32_t            : 2;
      __IM  uint32_t ECC_SYND   : 8;            /*!< [15..8] Position of ECC error occurs                                      */
            uint32_t            : 16;
    } bit;
  } SR0;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000008) State Register 1 of Eflash                                 */
    
    struct {
      __IM  uint32_t ECC_ERR_ADDR : 32;         /*!< [31..0] Address that Ecc Error happens                                    */
    } bit;
  } SR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) Operation Command Register                                 */
    
    struct {
      __IOM uint32_t CMD        : 3;            /*!< [2..0] Operation Command                                                  */
            uint32_t            : 29;
    } bit;
  } CMD;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000010) Operation Excution Register                                */
    
    struct {
            uint32_t            : 31;
      __IOM uint32_t EXE        : 1;            /*!< [31..31] Excute the cmd in CMD                                            */
    } bit;
  } CMD_EXE;
  __IM  uint32_t  RESERVED[2];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) Programing Byte Control Register                           */
    
    struct {
      __IOM uint32_t PROG_BYTES : 8;            /*!< [7..0] Byte program control register. Each bit controls one
                                                     byte in the 8 byte programing operation. Bit 7 for the
                                                     byte of the highst address. Bit 0 for the byte of the lowest
                                                     address.                                                                  */
            uint32_t            : 24;
    } bit;
  } BYTES;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000020) Operation Address Register                                 */
    
    struct {
      __IOM uint32_t ADDR       : 32;           /*!< [31..0] The address to operate.                                           */
    } bit;
  } ADDR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000024) Data 0 Register                                            */
    
    struct {
      __IOM uint32_t DATA0      : 32;           /*!< [31..0] Data to be programed or read from Flash, low part.                */
    } bit;
  } DATA0;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000028) Data 1 Register                                            */
    
    struct {
      __IOM uint32_t DATA1      : 32;           /*!< [31..0] Data to be programed or read from Flash, high part.               */
    } bit;
  } DATA1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000002C) Data 2 Register                                            */
    
    struct {
      __IOM uint32_t DATA2      : 8;            /*!< [7..0] Data read from Flash, part of ECC code.                            */
            uint32_t            : 24;
    } bit;
  } DATA2;
  __IM  uint32_t  RESERVED1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000034) Interrupt State Register                                   */
    
    struct {
      __IM  uint32_t ECC_ERR_STATE : 1;         /*!< [0..0] State of ECC Error interrupt                                       */
      __IM  uint32_t PROG_STATE : 1;            /*!< [1..1] State of program finish interrupt                                  */
      __IM  uint32_t ERASE_STATE : 1;           /*!< [2..2] State of erase finish interrupt                                    */
      __IM  uint32_t AHB_PROG_ERR_STATE : 1;    /*!< [3..3] State of the AHB programing error interrupt                        */
      __IM  uint32_t PROTECTED_ERR_STATE : 1;   /*!< [4..4] State of the protection error interrupt                            */
            uint32_t            : 27;
    } bit;
  } INIT;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000038) Interrupt Enable Register                                  */
    
    struct {
      __IOM uint32_t ECC_ERR_EN : 1;            /*!< [0..0] Setting 1 to enable ECC Error interrupt else disable               */
      __IOM uint32_t PROG_EN    : 1;            /*!< [1..1] Setting 1 to enable program finish interrupt else disable          */
      __IOM uint32_t ERASE_EN   : 1;            /*!< [2..2] Setting 1 to enable erase finish interrupt else disable            */
      __IOM uint32_t AHB_PROG_ERR_EN : 1;       /*!< [3..3] Setting 1 to enable the AHB programing error interrupt
                                                     else disable                                                              */
      __IOM uint32_t PROTECTED_ERR_EN : 1;      /*!< [4..4] Setting 1 to enable the protection error interrupt else
                                                     disable                                                                   */
            uint32_t            : 27;
    } bit;
  } IER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000003C) Interrupt Clear Register                                   */
    
    struct {
      __OM  uint32_t ECC_ERR_CLR : 1;           /*!< [0..0] Writing 1 to clear the ECC Error interrupt state                   */
      __OM  uint32_t PROG_CLR   : 1;            /*!< [1..1] Writing 1 to clear the program finish interrupt state              */
      __OM  uint32_t ERASE_CLR  : 1;            /*!< [2..2] Writing 1 to clear the erase finish interrupt state                */
      __OM  uint32_t AHB_PROG_ERR_CLR : 1;      /*!< [3..3] Writing 1 to clear the AHB programing error interrupt
                                                     state                                                                     */
      __OM  uint32_t PROTECTED_ERR_CLR : 1;     /*!< [4..4] Writing 1 to clear the protection error interrupt state            */
            uint32_t            : 27;
    } bit;
  } CLR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000040) Operation Timing 0 Register                                */
    
    struct {
      __IOM uint32_t TWUP       : 4;            /*!< [3..0] Twup time                                                          */
      __IOM uint32_t ERASE_TNVS : 4;            /*!< [7..4] erase_Tnvs time                                                    */
      __IOM uint32_t ERASE_TERASE_S : 4;        /*!< [11..8] erase_Terase_s time                                               */
      __IOM uint32_t ERASE_TERASE_C : 4;        /*!< [15..12] erase_Terase_c time                                              */
      __IOM uint32_t ERASE_TRCV_S : 4;          /*!< [19..16] erase_Trcv_s time                                                */
      __IOM uint32_t ERASE_TRCV_C : 4;          /*!< [23..20] erase_Trcv_c time                                                */
            uint32_t            : 8;
    } bit;
  } PARAM0;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000044) Operation Timing 1 Register                                */
    
    struct {
      __IOM uint32_t prog_Tnvs  : 4;            /*!< [3..0] prog_Tnvs time                                                     */
      __IOM uint32_t prog_Tpgs  : 6;            /*!< [9..4] prog_Tpgs time                                                     */
      __IOM uint32_t prog_Tprog : 6;            /*!< [15..10] prog_Tprog time                                                  */
      __IOM uint32_t prog_Trcv  : 4;            /*!< [19..16] prog_Trcv time                                                   */
            uint32_t            : 12;
    } bit;
  } PARAM1;
  __IM  uint32_t  RESERVED2[6];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000060) Trim0 Register                                             */
    
    struct {
      __IOM uint32_t TRIM0      : 32;           /*!< [31..0] data of trim0                                                     */
    } bit;
  } TRIM0;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000064) Trim1 Register                                             */
    
    struct {
      __IOM uint32_t TRIM1      : 32;           /*!< [31..0] data of trim1                                                     */
    } bit;
  } TRIM1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000068) Trim2 Register                                             */
    
    struct {
      __IOM uint32_t TRIM2      : 16;           /*!< [15..0] data of trim2                                                     */
            uint32_t            : 16;
    } bit;
  } TRIM2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000006C) KEY for TRIM KEY and ECC Regs                              */
    
    struct {
      __IOM uint32_t READM0     : 1;            /*!< [0..0] read margin0                                                       */
      __IOM uint32_t READM1     : 1;            /*!< [1..1] read margin1                                                       */
            uint32_t            : 14;
      __OM  uint32_t TST_KEY    : 16;           /*!< [31..16] test key                                                         */
    } bit;
  } FTST;
  __IOM uint32_t  TRIM_KEY;                     /*!< (@ 0x00000070) Trim Key Register                                          */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000074) Parameter Key Register                                     */
    
    struct {
      __OM  uint32_t PARAM_KEY  : 32;           /*!< [31..0] parameter district key                                            */
    } bit;
  } PARAM_KEY;
  __IM  uint32_t  RESERVED3[2];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000080) Ecc Injection L Register                                   */
    
    struct {
      __IOM uint32_t ECC_INL    : 32;           /*!< [31..0] ECC Err inject bits [31:0]                                        */
    } bit;
  } ECC_INL;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000084) Ecc Injection M Register                                   */
    
    struct {
      __IOM uint32_t ECC_INM    : 32;           /*!< [31..0] ECC Err inject bits [63:32]                                       */
    } bit;
  } ECC_INM;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000088) Ecc Injection H Register                                   */
    
    struct {
      __IOM uint32_t ECC_INH    : 8;            /*!< [7..0] ECC Err inject bits [71:64]                                        */
            uint32_t            : 24;
    } bit;
  } ECC_INH;
} FMC_Type;                                     /*!< Size = 140 (0x8c)                                                         */



/* =========================================================================================================================== */
/* ================                                           GPIOA                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief GPIOA (GPIOA)
  */

typedef struct {                                /*!< (@ 0x400F0000) GPIOA Structure                                            */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) GPIO Mode Register                                         */
    
    struct {
      __IOM uint32_t MODE0      : 2;            /*!< [1..0] Mode configuration of of GPIO 0                                    */
      __IOM uint32_t MODE1      : 2;            /*!< [3..2] Mode configuration of of GPIO 1                                    */
      __IOM uint32_t MODE2      : 2;            /*!< [5..4] Mode configuration of of GPIO 2                                    */
      __IOM uint32_t MODE3      : 2;            /*!< [7..6] Mode configuration of of GPIO 3                                    */
      __IOM uint32_t MODE4      : 2;            /*!< [9..8] Mode configuration of of GPIO 4                                    */
      __IOM uint32_t MODE5      : 2;            /*!< [11..10] Mode configuration of of GPIO 5                                  */
      __IOM uint32_t MODE6      : 2;            /*!< [13..12] Mode configuration of of GPIO 6                                  */
      __IOM uint32_t MODE7      : 2;            /*!< [15..14] Mode configuration of of GPIO 7                                  */
      __IOM uint32_t MODE8      : 2;            /*!< [17..16] Mode configuration of of GPIO 8                                  */
      __IOM uint32_t MODE9      : 2;            /*!< [19..18] Mode configuration of of GPIO 9                                  */
      __IOM uint32_t MODE10     : 2;            /*!< [21..20] Mode configuration of of GPIO 10                                 */
      __IOM uint32_t MODE11     : 2;            /*!< [23..22] Mode configuration of of GPIO 11                                 */
      __IOM uint32_t MODE12     : 2;            /*!< [25..24] Mode configuration of of GPIO 12                                 */
      __IOM uint32_t MODE13     : 2;            /*!< [27..26] Mode configuration of of GPIO 13                                 */
      __IOM uint32_t MODE14     : 2;            /*!< [29..28] Mode configuration of of GPIO 14                                 */
      __IOM uint32_t MODE15     : 2;            /*!< [31..30] Mode configuration of of GPIO 15                                 */
    } bit;
  } MODER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) GPIO Output Type Register                                  */
    
    struct {
      __IOM uint32_t OT0        : 1;            /*!< [0..0] Output type configuration of GPIO 0                                */
      __IOM uint32_t OT1        : 1;            /*!< [1..1] Output type configuration of GPIO 1                                */
      __IOM uint32_t OT2        : 1;            /*!< [2..2] Output type configuration of GPIO 2                                */
      __IOM uint32_t OT3        : 1;            /*!< [3..3] Output type configuration of GPIO 3                                */
      __IOM uint32_t OT4        : 1;            /*!< [4..4] Output type configuration of GPIO 4                                */
      __IOM uint32_t OT5        : 1;            /*!< [5..5] Output type configuration of GPIO 5                                */
      __IOM uint32_t OT6        : 1;            /*!< [6..6] Output type configuration of GPIO 6                                */
      __IOM uint32_t OT7        : 1;            /*!< [7..7] Output type configuration of GPIO 7                                */
      __IOM uint32_t OT8        : 1;            /*!< [8..8] Output type configuration of GPIO 8                                */
      __IOM uint32_t OT9        : 1;            /*!< [9..9] Output type configuration of GPIO 9                                */
      __IOM uint32_t OT10       : 1;            /*!< [10..10] Output type configuration of GPIO 10                             */
      __IOM uint32_t OT11       : 1;            /*!< [11..11] Output type configuration of GPIO 11                             */
      __IOM uint32_t OT12       : 1;            /*!< [12..12] Output type configuration of GPIO 12                             */
      __IOM uint32_t OT13       : 1;            /*!< [13..13] Output type configuration of GPIO 13                             */
      __IOM uint32_t OT14       : 1;            /*!< [14..14] Output type configuration of GPIO 14                             */
      __IOM uint32_t OT15       : 1;            /*!< [15..15] Output type configuration of GPIO 15                             */
            uint32_t            : 16;
    } bit;
  } OTYPER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000008) GPIO Strength Register                                     */
    
    struct {
      __IOM uint32_t STR0       : 1;            /*!< [0..0] GPIO strength configuration of of GPIO 0                           */
      __IOM uint32_t STR1       : 1;            /*!< [1..1] GPIO strength configuration of of GPIO 1                           */
      __IOM uint32_t STR2       : 1;            /*!< [2..2] GPIO strength configuration of of GPIO 2                           */
      __IOM uint32_t STR3       : 1;            /*!< [3..3] GPIO strength configuration of of GPIO 3                           */
      __IOM uint32_t STR4       : 1;            /*!< [4..4] GPIO strength configuration of of GPIO 4                           */
      __IOM uint32_t STR5       : 1;            /*!< [5..5] GPIO strength configuration of of GPIO 5                           */
      __IOM uint32_t STR6       : 1;            /*!< [6..6] GPIO strength configuration of of GPIO 6                           */
      __IOM uint32_t STR7       : 1;            /*!< [7..7] GPIO strength configuration of of GPIO 7                           */
      __IOM uint32_t STR8       : 1;            /*!< [8..8] GPIO strength configuration of of GPIO 8                           */
      __IOM uint32_t STR9       : 1;            /*!< [9..9] GPIO strength configuration of of GPIO 9                           */
      __IOM uint32_t STR10      : 1;            /*!< [10..10] GPIO strength configuration of of GPIO 10                        */
      __IOM uint32_t STR11      : 1;            /*!< [11..11] GPIO strength configuration of of GPIO 11                        */
      __IOM uint32_t STR12      : 1;            /*!< [12..12] GPIO strength configuration of of GPIO 12                        */
      __IOM uint32_t STR13      : 1;            /*!< [13..13] GPIO strength configuration of of GPIO 13                        */
      __IOM uint32_t STR14      : 1;            /*!< [14..14] GPIO strength configuration of of GPIO 14                        */
      __IOM uint32_t STR15      : 1;            /*!< [15..15] GPIO strength configuration of of GPIO 15                        */
            uint32_t            : 16;
    } bit;
  } STR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) GPIO Slew Rate Register                                    */
    
    struct {
      __IOM uint32_t RATE0      : 1;            /*!< [0..0] GPIO slew rate configuration of of GPIO 0                          */
      __IOM uint32_t RATE1      : 1;            /*!< [1..1] GPIO slew rate configuration of of GPIO 1                          */
      __IOM uint32_t RATE2      : 1;            /*!< [2..2] GPIO slew rate configuration of of GPIO 2                          */
      __IOM uint32_t RATE3      : 1;            /*!< [3..3] GPIO slew rate configuration of of GPIO 3                          */
      __IOM uint32_t RATE4      : 1;            /*!< [4..4] GPIO slew rate configuration of of GPIO 4                          */
      __IOM uint32_t RATE5      : 1;            /*!< [5..5] GPIO slew rate configuration of of GPIO 5                          */
      __IOM uint32_t RATE6      : 1;            /*!< [6..6] GPIO slew rate configuration of of GPIO 6                          */
      __IOM uint32_t RATE7      : 1;            /*!< [7..7] GPIO slew rate configuration of of GPIO 7                          */
      __IOM uint32_t RATE8      : 1;            /*!< [8..8] GPIO slew rate configuration of of GPIO 8                          */
      __IOM uint32_t RATE9      : 1;            /*!< [9..9] GPIO slew rate configuration of of GPIO 9                          */
      __IOM uint32_t RATE10     : 1;            /*!< [10..10] GPIO slew rate configuration of of GPIO 10                       */
      __IOM uint32_t RATE11     : 1;            /*!< [11..11] GPIO slew rate configuration of of GPIO 11                       */
      __IOM uint32_t RATE12     : 1;            /*!< [12..12] GPIO slew rate configuration of of GPIO 12                       */
      __IOM uint32_t RATE13     : 1;            /*!< [13..13] GPIO slew rate configuration of of GPIO 13                       */
      __IOM uint32_t RATE14     : 1;            /*!< [14..14] GPIO slew rate configuration of of GPIO 14                       */
      __IOM uint32_t RATE15     : 1;            /*!< [15..15] GPIO slew rate configuration of of GPIO 15                       */
            uint32_t            : 16;
    } bit;
  } SLEWR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000010) GPIO Pull-up Pull-down Register                            */
    
    struct {
      __IOM uint32_t PUPD0      : 2;            /*!< [1..0] GPIO pull up/down configuration of of GPIO 0                       */
      __IOM uint32_t PUPD1      : 2;            /*!< [3..2] GPIO pull up/down configuration of of GPIO 1                       */
      __IOM uint32_t PUPD2      : 2;            /*!< [5..4] GPIO pull up/down configuration of of GPIO 2                       */
      __IOM uint32_t PUPD3      : 2;            /*!< [7..6] GPIO pull up/down configuration of of GPIO 3                       */
      __IOM uint32_t PUPD4      : 2;            /*!< [9..8] GPIO pull up/down configuration of of GPIO 4                       */
      __IOM uint32_t PUPD5      : 2;            /*!< [11..10] GPIO pull up/down configuration of of GPIO 5                     */
      __IOM uint32_t PUPD6      : 2;            /*!< [13..12] GPIO pull up/down configuration of of GPIO 6                     */
      __IOM uint32_t PUPD7      : 2;            /*!< [15..14] GPIO pull up/down configuration of of GPIO 7                     */
      __IOM uint32_t PUPD8      : 2;            /*!< [17..16] GPIO pull up/down configuration of of GPIO 8                     */
      __IOM uint32_t PUPD9      : 2;            /*!< [19..18] GPIO pull up/down configuration of of GPIO 9                     */
      __IOM uint32_t PUPD10     : 2;            /*!< [21..20] GPIO pull up/down configuration of of GPIO 10                    */
      __IOM uint32_t PUPD11     : 2;            /*!< [23..22] GPIO pull up/down configuration of of GPIO 11                    */
      __IOM uint32_t PUPD12     : 2;            /*!< [25..24] GPIO pull up/down configuration of of GPIO 12                    */
      __IOM uint32_t PUPD13     : 2;            /*!< [27..26] GPIO pull up/down configuration of of GPIO 13                    */
      __IOM uint32_t PUPD14     : 2;            /*!< [29..28] GPIO pull up/down configuration of of GPIO 14                    */
      __IOM uint32_t PUPD15     : 2;            /*!< [31..30] GPIO pull up/down configuration of of GPIO 15                    */
    } bit;
  } PUPDR;
  __IM  uint32_t  RESERVED[2];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) GPIO Input Data Register                                   */
    
    struct {
      __IM  uint32_t ID0        : 1;            /*!< [0..0] If GPIO 0 is INPUT, this bit reflects the voltage level
                                                     on the GPIO.                                                              */
      __IM  uint32_t ID1        : 1;            /*!< [1..1] If GPIO 1 is INPUT, this bit reflects the voltage level
                                                     on the GPIO.                                                              */
      __IM  uint32_t ID2        : 1;            /*!< [2..2] If GPIO 2 is INPUT, this bit reflects the voltage level
                                                     on the GPIO.                                                              */
      __IM  uint32_t ID3        : 1;            /*!< [3..3] If GPIO 3 is INPUT, this bit reflects the voltage level
                                                     on the GPIO.                                                              */
      __IM  uint32_t ID4        : 1;            /*!< [4..4] If GPIO 4 is INPUT, this bit reflects the voltage level
                                                     on the GPIO.                                                              */
      __IM  uint32_t ID5        : 1;            /*!< [5..5] If GPIO 5 is INPUT, this bit reflects the voltage level
                                                     on the GPIO.                                                              */
      __IM  uint32_t ID6        : 1;            /*!< [6..6] If GPIO 6 is INPUT, this bit reflects the voltage level
                                                     on the GPIO.                                                              */
      __IM  uint32_t ID7        : 1;            /*!< [7..7] If GPIO 7 is INPUT, this bit reflects the voltage level
                                                     on the GPIO.                                                              */
      __IM  uint32_t ID8        : 1;            /*!< [8..8] If GPIO 8 is INPUT, this bit reflects the voltage level
                                                     on the GPIO.                                                              */
      __IM  uint32_t ID9        : 1;            /*!< [9..9] If GPIO 9 is INPUT, this bit reflects the voltage level
                                                     on the GPIO.                                                              */
      __IM  uint32_t ID10       : 1;            /*!< [10..10] If GPIO 10 is INPUT, this bit reflects the voltage
                                                     level on the GPIO.                                                        */
      __IM  uint32_t ID11       : 1;            /*!< [11..11] If GPIO 11 is INPUT, this bit reflects the voltage
                                                     level on the GPIO.                                                        */
      __IM  uint32_t ID12       : 1;            /*!< [12..12] If GPIO 12 is INPUT, this bit reflects the voltage
                                                     level on the GPIO.                                                        */
      __IM  uint32_t ID13       : 1;            /*!< [13..13] If GPIO 13 is INPUT, this bit reflects the voltage
                                                     level on the GPIO.                                                        */
      __IM  uint32_t ID14       : 1;            /*!< [14..14] If GPIO 14 is INPUT, this bit reflects the voltage
                                                     level on the GPIO.                                                        */
      __IM  uint32_t ID15       : 1;            /*!< [15..15] If GPIO 15 is INPUT, this bit reflects the voltage
                                                     level on the GPIO.                                                        */
            uint32_t            : 16;
    } bit;
  } IDR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000020) GPIO Output Data Register                                  */
    
    struct {
      __IOM uint32_t OD0        : 1;            /*!< [0..0] If GPIO 0 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD1        : 1;            /*!< [1..1] If GPIO 1 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD2        : 1;            /*!< [2..2] If GPIO 2 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD3        : 1;            /*!< [3..3] If GPIO 3 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD4        : 1;            /*!< [4..4] If GPIO 4 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD5        : 1;            /*!< [5..5] If GPIO 5 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD6        : 1;            /*!< [6..6] If GPIO 6 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD7        : 1;            /*!< [7..7] If GPIO 7 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD8        : 1;            /*!< [8..8] If GPIO 8 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD9        : 1;            /*!< [9..9] If GPIO 9 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD10       : 1;            /*!< [10..10] If GPIO 10 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD11       : 1;            /*!< [11..11] If GPIO 11 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD12       : 1;            /*!< [12..12] If GPIO 12 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD13       : 1;            /*!< [13..13] If GPIO 13 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD14       : 1;            /*!< [14..14] If GPIO 14 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
      __IOM uint32_t OD15       : 1;            /*!< [15..15] If GPIO 15 is OUTPUT, this bit sets the output voltage
                                                     level on the GPIO.                                                        */
            uint32_t            : 16;
    } bit;
  } ODR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000024) GPIO Altenate Function Low Register                        */
    
    struct {
      __IOM uint32_t AFSEL0     : 4;            /*!< [3..0] Alternate selection for GPIO 0.                                    */
      __IOM uint32_t AFSEL1     : 4;            /*!< [7..4] Alternate selection for GPIO 1.                                    */
      __IOM uint32_t AFSEL2     : 4;            /*!< [11..8] Alternate selection for GPIO 2.                                   */
      __IOM uint32_t AFSEL3     : 4;            /*!< [15..12] Alternate selection for GPIO 3.                                  */
      __IOM uint32_t AFSEL4     : 4;            /*!< [19..16] Alternate selection for GPIO 4.                                  */
      __IOM uint32_t AFSEL5     : 4;            /*!< [23..20] Alternate selection for GPIO 5.                                  */
      __IOM uint32_t AFSEL6     : 4;            /*!< [27..24] Alternate selection for GPIO 6.                                  */
      __IOM uint32_t AFSEL7     : 4;            /*!< [31..28] Alternate selection for GPIO 7.                                  */
    } bit;
  } AFLR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000028) GPIO Altenate Function High Register                       */
    
    struct {
      __IOM uint32_t AFSEL8     : 4;            /*!< [3..0] Alternate selection for GPIO 8.                                    */
      __IOM uint32_t AFSEL9     : 4;            /*!< [7..4] Alternate selection for GPIO 9.                                    */
      __IOM uint32_t AFSEL10    : 4;            /*!< [11..8] Alternate selection for GPIO 10.                                  */
      __IOM uint32_t AFSEL11    : 4;            /*!< [15..12] Alternate selection for GPIO 11.                                 */
      __IOM uint32_t AFSEL12    : 4;            /*!< [19..16] Alternate selection for GPIO 12.                                 */
      __IOM uint32_t AFSEL13    : 4;            /*!< [23..20] Alternate selection for GPIO 13.                                 */
      __IOM uint32_t AFSEL14    : 4;            /*!< [27..24] Alternate selection for GPIO 14.                                 */
      __IOM uint32_t AFSEL15    : 4;            /*!< [31..28] Alternate selection for GPIO 15.                                 */
    } bit;
  } AFHR;
  __IM  uint32_t  RESERVED1[5];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000040) GPIO Edge Interrupt Enable Register                        */
    
    struct {
      __IOM uint32_t EDGIE0     : 2;            /*!< [1..0] GPIO 0 edge interrupt enable                                       */
      __IOM uint32_t EDGIE1     : 2;            /*!< [3..2] GPIO 1 edge interrupt enable                                       */
      __IOM uint32_t EDGIE2     : 2;            /*!< [5..4] GPIO 2 edge interrupt enable                                       */
      __IOM uint32_t EDGIE3     : 2;            /*!< [7..6] GPIO 3 edge interrupt enable                                       */
      __IOM uint32_t EDGIE4     : 2;            /*!< [9..8] GPIO 4 edge interrupt enable                                       */
      __IOM uint32_t EDGIE5     : 2;            /*!< [11..10] GPIO 5 edge interrupt enable                                     */
      __IOM uint32_t EDGIE6     : 2;            /*!< [13..12] GPIO 6 edge interrupt enable                                     */
      __IOM uint32_t EDGIE7     : 2;            /*!< [15..14] GPIO 7 edge interrupt enable                                     */
      __IOM uint32_t EDGIE8     : 2;            /*!< [17..16] GPIO 8 edge interrupt enable                                     */
      __IOM uint32_t EDGIE9     : 2;            /*!< [19..18] GPIO 9 edge interrupt enable                                     */
      __IOM uint32_t EDGIE10    : 2;            /*!< [21..20] GPIO 10 edge interrupt enable                                    */
      __IOM uint32_t EDGIE11    : 2;            /*!< [23..22] GPIO 11 edge interrupt enable                                    */
      __IOM uint32_t EDGIE12    : 2;            /*!< [25..24] GPIO 12 edge interrupt enable                                    */
      __IOM uint32_t EDGIE13    : 2;            /*!< [27..26] GPIO 13 edge interrupt enable                                    */
      __IOM uint32_t EDGIE14    : 2;            /*!< [29..28] GPIO 14 edge interrupt enable                                    */
      __IOM uint32_t EDGIE15    : 2;            /*!< [31..30] GPIO 15 edge interrupt enable                                    */
    } bit;
  } EDGIER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000044) GPIO Edge Interrupt Status Register                        */
    
    struct {
      __IM  uint32_t EDGISR0    : 2;            /*!< [1..0] GPIO 0 edge interrupt status                                       */
      __IM  uint32_t EDGISR1    : 2;            /*!< [3..2] GPIO 1 edge interrupt status                                       */
      __IM  uint32_t EDGISR2    : 2;            /*!< [5..4] GPIO 2 edge interrupt status                                       */
      __IM  uint32_t EDGISR3    : 2;            /*!< [7..6] GPIO 3 edge interrupt status                                       */
      __IM  uint32_t EDGISR4    : 2;            /*!< [9..8] GPIO 4 edge interrupt status                                       */
      __IM  uint32_t EDGISR5    : 2;            /*!< [11..10] GPIO 5 edge interrupt status                                     */
      __IM  uint32_t EDGISR6    : 2;            /*!< [13..12] GPIO 6 edge interrupt status                                     */
      __IM  uint32_t EDGISR7    : 2;            /*!< [15..14] GPIO 7 edge interrupt status                                     */
      __IM  uint32_t EDGISR8    : 2;            /*!< [17..16] GPIO 8 edge interrupt status                                     */
      __IM  uint32_t EDGISR9    : 2;            /*!< [19..18] GPIO 9 edge interrupt status                                     */
      __IM  uint32_t EDGISR10   : 2;            /*!< [21..20] GPIO 10 edge interrupt status                                    */
      __IM  uint32_t EDGISR11   : 2;            /*!< [23..22] GPIO 11 edge interrupt status                                    */
      __IM  uint32_t EDGISR12   : 2;            /*!< [25..24] GPIO 12 edge interrupt status                                    */
      __IM  uint32_t EDGISR13   : 2;            /*!< [27..26] GPIO 13 edge interrupt status                                    */
      __IM  uint32_t EDGISR14   : 2;            /*!< [29..28] GPIO 14 edge interrupt status                                    */
      __IM  uint32_t EDGISR15   : 2;            /*!< [31..30] GPIO 15 edge interrupt status                                    */
    } bit;
  } EDGISR;
  __IM  uint32_t  RESERVED2[6];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000060) GPIO Edge Interrupt Status Clear Register                  */
    
    struct {
      __OM  uint32_t EDGICLR0   : 2;            /*!< [1..0] GPIO 0 edge interrupt status clear.Writing 1 into this
                                                     bits can clear the corresponding EDGISR.                                  */
      __OM  uint32_t EDGICLR1   : 2;            /*!< [3..2] GPIO 1 edge interrupt status clear.Writing 1 into this
                                                     bits can clear the corresponding EDGISR.                                  */
      __OM  uint32_t EDGICLR2   : 2;            /*!< [5..4] GPIO 2 edge interrupt status clear.Writing 1 into this
                                                     bits can clear the corresponding EDGISR.                                  */
      __OM  uint32_t EDGICLR3   : 2;            /*!< [7..6] GPIO 3 edge interrupt status clear.Writing 1 into this
                                                     bits can clear the corresponding EDGISR.                                  */
      __OM  uint32_t EDGICLR4   : 2;            /*!< [9..8] GPIO 4 edge interrupt status clear.Writing 1 into this
                                                     bits can clear the corresponding EDGISR.                                  */
      __OM  uint32_t EDGICLR5   : 2;            /*!< [11..10] GPIO 5 edge interrupt status clear.Writing 1 into this
                                                     bits can clear the corresponding EDGISR.                                  */
      __OM  uint32_t EDGICLR6   : 2;            /*!< [13..12] GPIO 6 edge interrupt status clear.Writing 1 into this
                                                     bits can clear the corresponding EDGISR.                                  */
      __OM  uint32_t EDGICLR7   : 2;            /*!< [15..14] GPIO 7 edge interrupt status clear.Writing 1 into this
                                                     bits can clear the corresponding EDGISR.                                  */
      __OM  uint32_t EDGICLR8   : 2;            /*!< [17..16] GPIO 8 edge interrupt status clear.Writing 1 into this
                                                     bits can clear the corresponding EDGISR.                                  */
      __OM  uint32_t EDGICLR9   : 2;            /*!< [19..18] GPIO 9 edge interrupt status clear.Writing 1 into this
                                                     bits can clear the corresponding EDGISR.                                  */
      __OM  uint32_t EDGICLR10  : 2;            /*!< [21..20] GPIO 10 edge interrupt status clear.Writing 1 into
                                                     this bits can clear the corresponding EDGISR.                             */
      __OM  uint32_t EDGICLR11  : 2;            /*!< [23..22] GPIO 11 edge interrupt status clear.Writing 1 into
                                                     this bits can clear the corresponding EDGISR.                             */
      __OM  uint32_t EDGICLR12  : 2;            /*!< [25..24] GPIO 12 edge interrupt status clear.Writing 1 into
                                                     this bits can clear the corresponding EDGISR.                             */
      __OM  uint32_t EDGICLR13  : 2;            /*!< [27..26] GPIO 13 edge interrupt status clear.Writing 1 into
                                                     this bits can clear the corresponding EDGISR.                             */
      __OM  uint32_t EDGICLR14  : 2;            /*!< [29..28] GPIO 14 edge interrupt status clear.Writing 1 into
                                                     this bits can clear the corresponding EDGISR.                             */
      __OM  uint32_t EDGICLR15  : 2;            /*!< [31..30] GPIO 15 edge interrupt status clear.Writing 1 into
                                                     this bits can clear the corresponding EDGISR.                             */
    } bit;
  } EDGICLR;
  __IM  uint32_t  RESERVED3[3];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000070) GPIO Level Interrupt Enable Register                       */
    
    struct {
      __IOM uint32_t LEVIE0     : 2;            /*!< [1..0] GPIO 0 level interrupt enable.                                     */
      __IOM uint32_t LEVIE1     : 2;            /*!< [3..2] GPIO 1 level interrupt enable.                                     */
      __IOM uint32_t LEVIE2     : 2;            /*!< [5..4] GPIO 2 level interrupt enable.                                     */
      __IOM uint32_t LEVIE3     : 2;            /*!< [7..6] GPIO 3 level interrupt enable.                                     */
      __IOM uint32_t LEVIE4     : 2;            /*!< [9..8] GPIO 4 level interrupt enable.                                     */
      __IOM uint32_t LEVIE5     : 2;            /*!< [11..10] GPIO 5 level interrupt enable.                                   */
      __IOM uint32_t LEVIE6     : 2;            /*!< [13..12] GPIO 6 level interrupt enable.                                   */
      __IOM uint32_t LEVIE7     : 2;            /*!< [15..14] GPIO 7 level interrupt enable.                                   */
      __IOM uint32_t LEVIE8     : 2;            /*!< [17..16] GPIO 8 level interrupt enable.                                   */
      __IOM uint32_t LEVIE9     : 2;            /*!< [19..18] GPIO 9 level interrupt enable.                                   */
      __IOM uint32_t LEVIE10    : 2;            /*!< [21..20] GPIO 10 level interrupt enable.                                  */
      __IOM uint32_t LEVIE11    : 2;            /*!< [23..22] GPIO 11 level interrupt enable.                                  */
      __IOM uint32_t LEVIE12    : 2;            /*!< [25..24] GPIO 12 level interrupt enable.                                  */
      __IOM uint32_t LEVIE13    : 2;            /*!< [27..26] GPIO 13 level interrupt enable.                                  */
      __IOM uint32_t LEVIE14    : 2;            /*!< [29..28] GPIO 14 level interrupt enable.                                  */
      __IOM uint32_t LEVIE15    : 2;            /*!< [31..30] GPIO 15 level interrupt enable.                                  */
    } bit;
  } LEVIER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000074) GPIO Level Interrupt Status Register                       */
    
    struct {
      __IM  uint32_t LEVISR0    : 2;            /*!< [1..0] GPIO 0 level interrupt status                                      */
      __IM  uint32_t LEVISR1    : 2;            /*!< [3..2] GPIO 1 level interrupt status                                      */
      __IM  uint32_t LEVISR2    : 2;            /*!< [5..4] GPIO 2 level interrupt status                                      */
      __IM  uint32_t LEVISR3    : 2;            /*!< [7..6] GPIO 3 level interrupt status                                      */
      __IM  uint32_t LEVISR4    : 2;            /*!< [9..8] GPIO 4 level interrupt status                                      */
      __IM  uint32_t LEVISR5    : 2;            /*!< [11..10] GPIO 5 level interrupt status                                    */
      __IM  uint32_t LEVISR6    : 2;            /*!< [13..12] GPIO 6 level interrupt status                                    */
      __IM  uint32_t LEVISR7    : 2;            /*!< [15..14] GPIO 7 level interrupt status                                    */
      __IM  uint32_t LEVISR8    : 2;            /*!< [17..16] GPIO 8 level interrupt status                                    */
      __IM  uint32_t LEVISR9    : 2;            /*!< [19..18] GPIO 9 level interrupt status                                    */
      __IM  uint32_t LEVISR10   : 2;            /*!< [21..20] GPIO 10 level interrupt status                                   */
      __IM  uint32_t LEVISR11   : 2;            /*!< [23..22] GPIO 11 level interrupt status                                   */
      __IM  uint32_t LEVISR12   : 2;            /*!< [25..24] GPIO 12 level interrupt status                                   */
      __IM  uint32_t LEVISR13   : 2;            /*!< [27..26] GPIO 13 level interrupt status                                   */
      __IM  uint32_t LEVISR14   : 2;            /*!< [29..28] GPIO 14 level interrupt status                                   */
      __IM  uint32_t LEVISR15   : 2;            /*!< [31..30] GPIO 15 level interrupt status                                   */
    } bit;
  } LEVISR;
  __IM  uint32_t  RESERVED4[2];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000080) GPIO Level Interrupt Status Clear Register                 */
    
    struct {
      __OM  uint32_t LEVICLR0   : 2;            /*!< [1..0] GPIO 0 level status clear.Writing 1 into this bits can
                                                     clear the corresponding LEVISR.                                           */
      __OM  uint32_t LEVICLR1   : 2;            /*!< [3..2] GPIO 1 level status clear.Writing 1 into this bits can
                                                     clear the corresponding LEVISR.                                           */
      __OM  uint32_t LEVICLR2   : 2;            /*!< [5..4] GPIO 2 level status clear.Writing 1 into this bits can
                                                     clear the corresponding LEVISR.                                           */
      __OM  uint32_t LEVICLR3   : 2;            /*!< [7..6] GPIO 3 level status clear.Writing 1 into this bits can
                                                     clear the corresponding LEVISR.                                           */
      __OM  uint32_t LEVICLR4   : 2;            /*!< [9..8] GPIO 4 level status clear.Writing 1 into this bits can
                                                     clear the corresponding LEVISR.                                           */
      __OM  uint32_t LEVICLR5   : 2;            /*!< [11..10] GPIO 5 level status clear.Writing 1 into this bits
                                                     can clear the corresponding LEVISR.                                       */
      __OM  uint32_t LEVICLR6   : 2;            /*!< [13..12] GPIO 6 level status clear.Writing 1 into this bits
                                                     can clear the corresponding LEVISR.                                       */
      __OM  uint32_t LEVICLR7   : 2;            /*!< [15..14] GPIO 7 level status clear.Writing 1 into this bits
                                                     can clear the corresponding LEVISR.                                       */
      __OM  uint32_t LEVICLR8   : 2;            /*!< [17..16] GPIO 8 level status clear.Writing 1 into this bits
                                                     can clear the corresponding LEVISR.                                       */
      __OM  uint32_t LEVICLR9   : 2;            /*!< [19..18] GPIO 9 level status clear.Writing 1 into this bits
                                                     can clear the corresponding LEVISR.                                       */
      __OM  uint32_t LEVICLR10  : 2;            /*!< [21..20] GPIO 10 level status clear.Writing 1 into this bits
                                                     can clear the corresponding LEVISR.                                       */
      __OM  uint32_t LEVICLR11  : 2;            /*!< [23..22] GPIO 11 level status clear.Writing 1 into this bits
                                                     can clear the corresponding LEVISR.                                       */
      __OM  uint32_t LEVICLR12  : 2;            /*!< [25..24] GPIO 12 level status clear.Writing 1 into this bits
                                                     can clear the corresponding LEVISR.                                       */
      __OM  uint32_t LEVICLR13  : 2;            /*!< [27..26] GPIO 13 level status clear.Writing 1 into this bits
                                                     can clear the corresponding LEVISR.                                       */
      __OM  uint32_t LEVICLR14  : 2;            /*!< [29..28] GPIO 14 level status clear.Writing 1 into this bits
                                                     can clear the corresponding LEVISR.                                       */
      __OM  uint32_t LEVICLR15  : 2;            /*!< [31..30] GPIO 15 level status clear.Writing 1 into this bits
                                                     can clear the corresponding LEVISR.                                       */
    } bit;
  } LEVICLR;
} GPIO_Type;                                    /*!< Size = 132 (0x84)                                                         */



/* =========================================================================================================================== */
/* ================                                           SPI0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief SPI Master 0 (SPI0)
  */

typedef struct {                                /*!< (@ 0x40011000) SPI0 Structure                                             */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) This register controls the serial data transfer.
                                                                    It is impossible to write to this register.                */
    
    struct {
      __IOM uint32_t DFS        : 4;            /*!< [3..0] Data Frame Size.                                                   */
      __IOM uint32_t FRF        : 2;            /*!< [5..4] Frame Format.Selects which serial protocol transfers
                                                     the data.                                                                 */
      __IOM uint32_t SCPH       : 1;            /*!< [6..6] Serial Clock Phase. Valid when the frame format (FRF)
                                                     is set to Motorola SPI. The serial clock phase selects
                                                     the relationship of the serial clock with the slave select
                                                     signal. When SCPH = 0, data are captured on the first edge
                                                     of the serial clock. When SCPH = 1, the serial clock starts
                                                     toggling one cycle after the slave select line is activated,
                                                     and data are captured on the second edge of the serial
                                                     clock.  Values: 0x0 (SCPH_MIDDLE): Serial clock toggles
                                                     in middle of first d                                                      */
      __IOM uint32_t SCPOL      : 1;            /*!< [7..7] Serial Clock Polarity. Valid when the frame format (FRF)
                                                     is set to Motorola SPI. Used to select the polarity of
                                                     the inactive serial clock, which is held inactive when
                                                     the SSI master is not actively transferring data on the
                                                     serial bus. Values: 0x0 (SCLK_LOW): Inactive state of serial
                                                     clock is low  0x1 (SCLK_HIGH): Inactive state of serial
                                                     clock is high                                                             */
      __IOM uint32_t TMOD       : 2;            /*!< [9..8] Transfer Mode.                                                     */
            uint32_t            : 1;
      __IOM uint32_t SRL        : 1;            /*!< [11..11] Shift Register Loop. 0x1 (TESTING_MODE): Test mode:
                                                     Tx & Rx shift reg connected,0x0 (NORMAL_MODE): Normal mode
                                                     operation                                                                 */
      __IOM uint32_t CFS        : 4;            /*!< [15..12] Control Frame Size. Selects the length of the control
                                                     word for the Microwire frame format.                                      */
      __IOM uint32_t DFS_32     : 5;            /*!< [20..16] Data Frame Size in 32-bit transfer size mode.                    */
      __IM  uint32_t SPI_FRF    : 2;            /*!< [22..21] SPI Frame Format : Standard SPI Frame Format                     */
            uint32_t            : 1;
      __IOM uint32_t SSTE       : 1;            /*!< [24..24] Slave Select Toggle Enable. If this register field
                                                     is set to 1 the ss_*_n line will toggle between consecutive
                                                     data frames, with the serial clock (sclk) being held to
                                                     its default value while ss_*_n is high; if this register
                                                     field is set to 0 the ss_*_n will stay low and sclk will
                                                     run continuously for the duration of the transfer.                        */
            uint32_t            : 7;
    } bit;
  } CTRLR0;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) Control register 1 controls the end of serial
                                                                    transfers when in receive-only mode. It
                                                                    is impossible to write to this register
                                                                    when the DW_apb_ssi is enabled. The DW_apb_ssi
                                                                    is enabled and disabled by writing to the
                                                                    SSIENR register.                                           */
    
    struct {
      __IOM uint32_t NDF        : 16;           /*!< [15..0] Number of Data Frames.                                            */
            uint32_t            : 16;
    } bit;
  } CTRLR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000008) This register enables and disables the DW_apb_ssi.         */
    
    struct {
      __IOM uint32_t SSI_EN     : 1;            /*!< [0..0] SSI Enable. Enables and disables all SSI operations.               */
            uint32_t            : 31;
    } bit;
  } SSIENR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) This register controls the direction of the data
                                                                    word for the half-duplex Microwire serial
                                                                    protocol. It is impossible to write to this
                                                                    register when the DW_apb_ssi is enabled.                   */
    
    struct {
      __IOM uint32_t MWMOD      : 1;            /*!< [0..0] Microwire Transfer Mode. alues: 0x0 (NON_SEQUENTIAL):
                                                     Non-Sequential Microwire Transfer  0x1 (SEQUENTIAL): Sequential
                                                     Microwire Transfer                                                        */
      __IOM uint32_t MDD        : 1;            /*!< [1..1] Microwire Control. Values: 0x0 (RECEIVE): SSI receives
                                                     data  0x1 (TRANSMIT): SSI transmits data                                  */
      __IOM uint32_t MHS        : 1;            /*!< [2..2] Microwire Handshaking. Values: 0x0 (DISABLE): Handshaking
                                                     interface is disabled  0x1 (ENABLED): Handshaking interface
                                                     is enabled                                                                */
            uint32_t            : 29;
    } bit;
  } MWCR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000010) The register enables the individual slave select
                                                                    output lines from the DW_apb_ssi master.                   */
    
    struct {
      __IOM uint32_t SER        : 1;            /*!< [0..0] Slave Select Enable Flag.                                          */
            uint32_t            : 31;
    } bit;
  } SER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000014) The register derives the frequency of the serial
                                                                    clock that regulates the data transfer.
                                                                    The 16-bit field in this register defines
                                                                    the ssi_clk divider value. It is impossible
                                                                    to write to this register when the DW_apb_ssi
                                                                    is enabled.                                                */
    
    struct {
      __IOM uint32_t SCKDV      : 16;           /*!< [15..0] SSI Clock Divider. The LSB for this field is always
                                                     set to 0 and is unaffected by a write operation, which
                                                     ensures an even value is held in this register. If the
                                                     value is 0, the serial output clock (sclk_out) is disabled.
                                                     The frequency of the sclk_out is derived from the following
                                                     equation: Fsclk_out = Fssi_clk/SCKDV where SCKDV is any
                                                     even value between 2 and 65534. For example: for Fssi_clk
                                                     = 3.6864MHz and SCKDV =2 Fsclk_out = 3.6864/2 = 1.8432MHz                 */
            uint32_t            : 16;
    } bit;
  } BAUDR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000018) This register controls the threshold value for
                                                                    the transmit FIFO memory.                                  */
    
    struct {
      __IOM uint32_t TFT        : 3;            /*!< [2..0] Transmit FIFO Threshold. Controls the level of entries
                                                     (or below) at which the transmit FIFO controller triggers
                                                     an interrupt. When the number of transmit FIFO entries
                                                     is less than or equal to this value, the transmit FIFO
                                                     empty interrupt is triggered.                                             */
            uint32_t            : 29;
    } bit;
  } TXFTLR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) This register controls the threshold value for
                                                                    the receive FIFO memory.                                   */
    
    struct {
      __IOM uint32_t RFT        : 3;            /*!< [2..0] Receive FIFO Threshold. Controls the level of entries
                                                     (or above) at which the receive FIFO controller triggers
                                                     an interrupt. When the number of receive FIFO entries is
                                                     greater than or equal to this value + 1, the receive FIFO
                                                     full interrupt is triggered.                                              */
            uint32_t            : 29;
    } bit;
  } RXFTLR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000020) This register contains the number of valid data
                                                                    entries in the transmit FIFO memory.                       */
    
    struct {
      __IOM uint32_t TXTFL      : 4;            /*!< [3..0] Transmit FIFO Level. Contains the number of valid data
                                                     entries in the transmit FIFO.                                             */
            uint32_t            : 28;
    } bit;
  } TXFLR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000024) This register contains the number of valid data
                                                                    entries in the receive FIFO memory.                        */
    
    struct {
      __IOM uint32_t RXTFL      : 4;            /*!< [3..0] Receive FIFO Level. Contains the number of valid data
                                                     entries in the receive FIFO.                                              */
            uint32_t            : 28;
    } bit;
  } RXFLR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000028) This is a read-only register used to indicate
                                                                    the current transfer status, FIFO status,
                                                                    and any transmission/reception errors that
                                                                    may have occurred.                                         */
    
    struct {
      __IOM uint32_t BUSY       : 1;            /*!< [0..0] SSI Busy Flag. When set, indicates that a serial transfer
                                                     is in progress; when cleared indicates that the SSI is
                                                     idle or disabled.  Values: 0x0 (INACTIVE): SSI is idle
                                                     or disabled  0x1 (ACTIVE): SSI is actively transferring
                                                     data                                                                      */
      __IOM uint32_t TFNF       : 1;            /*!< [1..1] Transmit FIFO Not Full. Set when the transmit FIFO contains
                                                     one or more empty locations, and is cleared when the FIFO
                                                     is full.  Values: 0x0 (FULL): Transmit FIFO is full  0x1
                                                     (NOT_FULL): Transmit FIFO is not Full                                     */
      __IOM uint32_t TFE        : 1;            /*!< [2..2] Transmit FIFO Empty. When the transmit FIFO is completely
                                                     empty, this bit is set. When the transmit FIFO contains
                                                     one or more valid entries, this bit is cleared. This bit
                                                     field does not request an interrupt.  Values: 0x0 (NOT_EMPTY):
                                                     Transmit FIFO is not empty  0x1 (EMPTY): Transmit FIFO
                                                     is empty                                                                  */
      __IOM uint32_t RFNE       : 1;            /*!< [3..3] Receive FIFO Not Empty. Set when the receive FIFO contains
                                                     one or more entries and is cleared when the receive FIFO
                                                     is empty. This bit can be polled by software to completely
                                                     empty the receive FIFO.  Values: 0x0 (EMPTY): Receive FIFO
                                                     is empty  0x1 (NOT_EMPTY): Receive FIFO is not empty                      */
      __IOM uint32_t RFF        : 1;            /*!< [4..4] Receive FIFO Full. When the receive FIFO is completely
                                                     full, this bit is set. When the receive FIFO contains one
                                                     or more empty location, this bit is cleared.  Values: 0x0
                                                     (NOT_FULL): Receive FIFO is not full  0x1 (FULL): Receive
                                                     FIFO is full                                                              */
            uint32_t            : 1;
      __IOM uint32_t DCOL       : 1;            /*!< [6..6] Data Collision Error. This bit will be set if ss_in_n
                                                     input is asserted by other master, when the SSI master
                                                     is in the middle of the transfer. This informs the processor
                                                     that the last data transfer was halted before completion.
                                                     This bit is cleared when read.  Values: 0x0 (NO_ERROR_CONDITION):
                                                     No Error  0x1 (TX_COLLISION_ERROR): Transmit Data Collision
                                                     Error                                                                     */
            uint32_t            : 25;
    } bit;
  } SR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000002C) This read/write reigster masks or enables all
                                                                    interrupts generated by the DW_apb_ssi.                    */
    
    struct {
      __IOM uint32_t TXEIM      : 1;            /*!< [0..0] Transmit FIFO Empty Interrupt Mask 
                                                     Values: 0x0 (MASKED): ssi_txe_intr interrupt is masked
                                                     0x1 (UNMASKED): ssi_txe_intr interrupt is not masked                      */
      __IOM uint32_t TXOIM      : 1;            /*!< [1..1] Transmit FIFO Overflow Interrupt Mask 
                                                     Values: 0x0 (MASKED): ssi_txo_intr interrupt is masked
                                                     0x1 (UNMASKED): ssi_txo_intr interrupt is not masked                      */
      __IOM uint32_t RXUIM      : 1;            /*!< [2..2] Receive FIFO Underflow Interrupt Mask 
                                                     Values: 0x0 (MASKED): ssi_rxu_intr interrupt is masked
                                                     0x1 (UNMASKED): ssi_rxu_intr interrupt is not masked                      */
      __IOM uint32_t RXOIM      : 1;            /*!< [3..3] Receive FIFO Overflow Interrupt Mask 
                                                     Values: 0x0 (MASKED): ssi_rxo_intr interrupt is masked
                                                     0x1 (UNMASKED): ssi_rxo_intr interrupt is not masked                      */
      __IOM uint32_t RXFIM      : 1;            /*!< [4..4] Receive FIFO Full Interrupt Mask 
                                                     Values: 0x0 (MASKED): ssi_rxf_intr interrupt is masked
                                                     0x1 (UNMASKED): ssi_rxf_intr interrupt is not masked                      */
      __IOM uint32_t MSTIM      : 1;            /*!< [5..5] Multi-Master Contention Interrupt Mask. This bit field
                                                     is not present if the SSI is configured as a serial-slave
                                                     device.  Values: 0x0 (MASKED): ssi_mst_intr interrupt is
                                                     masked  0x1 (UNMASKED): ssi_mst_intr interrupt is not masked              */
            uint32_t            : 26;
    } bit;
  } IMR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000030) This register reports the status of the DW_apb_ssi
                                                                    interrupts after they have been masked.                    */
    
    struct {
      __IM  uint32_t TXEIS      : 1;            /*!< [0..0] Transmit FIFO Empty Interrupt Status  Values: 0x0 (INACTIVE):
                                                     ssi_txe_intr interrupt is not active after masking  0x1
                                                     (ACTIVE): ssi_txe_intr interrupt is active after masking                  */
      __IM  uint32_t TXOIS      : 1;            /*!< [1..1] Transmit FIFO Overflow Interrupt Status  Values: 0x0
                                                     (INACTIVE): ssi_txo_intr interrupt is not active after
                                                     masking  0x1 (ACTIVE): ssi_txo_intr interrupt is active
                                                     after masking                                                             */
      __IM  uint32_t RXUIS      : 1;            /*!< [2..2] Receive FIFO Underflow Interrupt Status  Values: 0x0
                                                     (INACTIVE): ssi_rxu_intr interrupt is not active after
                                                     masking  0x1 (ACTIVE): ssi_rxu_intr interrupt is active
                                                     after masking                                                             */
      __IM  uint32_t RXOIS      : 1;            /*!< [3..3] Receive FIFO Overflow Interrupt Status  Values: 0x0 (INACTIVE):
                                                     ssi_rxo_intr interrupt is not active after masking  0x1
                                                     (ACTIVE): ssi_rxo_intr interrupt is active after masking                  */
      __IM  uint32_t RXFIS      : 1;            /*!< [4..4] Receive FIFO Full Interrupt Status  Values: 0x0 (INACTIVE):
                                                     ssi_rxf_intr interrupt is not active after masking  0x1
                                                     (ACTIVE): ssi_rxf_intr interrupt is full after masking                    */
      __IM  uint32_t MSTIS      : 1;            /*!< [5..5] Multi-Master Contention Interrupt Status. This bit field
                                                     is not present if the SSI is configured as a serial-slave
                                                     device.  Values: 0x0 (INACTIVE): ssi_mst_intr interrupt
                                                     not active after masking  0x1 (ACTIVE): ssi_mst_intr interrupt
                                                     is active after masking                                                   */
            uint32_t            : 26;
    } bit;
  } ISR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000034) This read-only register reports the status of
                                                                    the DW_apb_ssi interrupts prior to masking.                */
    
    struct {
      __IM  uint32_t TXEIR      : 1;            /*!< [0..0] Transmit FIFO Empty Raw Interrupt Status  Values: 0x0
                                                     (INACTIVE): ssi_txe_intr interrupt is not active prior
                                                     to masking  0x1 (ACTIVE): ssi_txe_intr interrupt is active
                                                     prior masking                                                             */
      __IM  uint32_t TXOIR      : 1;            /*!< [1..1] Transmit FIFO Overflow Raw Interrupt Status  Values:
                                                     0x0 (INACTIVE): ssi_txo_intr interrupt is not active prior
                                                     to masking  0x1 (ACTIVE): ssi_txo_intr interrupt is active
                                                     prior masking                                                             */
      __IM  uint32_t RXUIR      : 1;            /*!< [2..2] Receive FIFO Underflow Raw Interrupt Status  Values:
                                                     0x0 (INACTIVE): ssi_rxu_intr interrupt is not active prior
                                                     to masking  0x1 (ACTIVE): ssi_rxu_intr interrupt is active
                                                     prior to masking                                                          */
      __IM  uint32_t RXOIR      : 1;            /*!< [3..3] Receive FIFO Overflow Raw Interrupt Status  Values: 0x1
                                                     (ACTIVE): ssi_rxo_intr interrupt is not active prior to
                                                     masking  0x0 (INACTIVE): ssi_rxo_intr interrupt is active
                                                     prior masking                                                             */
      __IM  uint32_t RXFIR      : 1;            /*!< [4..4] Receive FIFO Full Raw Interrupt Status  Values: 0x0 (INACTIVE):
                                                     ssi_rxf_intr interrupt is not active prior to masking 
                                                     0x1 (ACTIVE): ssi_rxf_intr interrupt is active prior to
                                                     masking                                                                   */
      __IM  uint32_t MSTIR      : 1;            /*!< [5..5] Multi-Master Contention Raw Interrupt Status. This bit
                                                     field is not present if the SSI is configured as a serial-slave
                                                     device.  Values: 0x0 (INACTIVE): ssi_mst_intr interrupt
                                                     is not active prior to masking  0x1 (ACTIVE): ssi_mst_intr
                                                     interrupt is active prior masking                                         */
            uint32_t            : 26;
    } bit;
  } RISR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000038) Transmit FIFO Overflow Interrupt Clear Register.           */
    
    struct {
      __IM  uint32_t TXOICR     : 1;            /*!< [0..0] Clear Transmit FIFO Overflow Interrupt. This register
                                                     reflects the status of the interrupt. A read from this
                                                     register clears the ssi_txo_intr interrupt; writing has
                                                     no effect.                                                                */
            uint32_t            : 31;
    } bit;
  } TXOICR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt Clear Register.            */
    
    struct {
      __IM  uint32_t RXOICR     : 1;            /*!< [0..0] Clear Receive FIFO Overflow Interrupt. This register
                                                     reflects the status of the interrupt. A read from this
                                                     register clears the ssi_rxo_intr interrupt; writing has
                                                     no effect.                                                                */
            uint32_t            : 31;
    } bit;
  } RXOICR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000040) Receive FIFO Underflow Interrupt Clear Register.           */
    
    struct {
      __IM  uint32_t RXUICR     : 1;            /*!< [0..0] Clear Receive FIFO Underflow Interrupt. This register
                                                     reflects the status of the interrupt. A read from this
                                                     register clears the ssi_rxu_intr interrupt; writing has
                                                     no effect.                                                                */
            uint32_t            : 31;
    } bit;
  } RXUICR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000044) Multi-Master Interrupt Clear Register.                     */
    
    struct {
      __IM  uint32_t MSTICR     : 1;            /*!< [0..0] Clear Multi-Master Contention Interrupt. This register
                                                     reflects the status of the interrupt. A read from this
                                                     register clears the ssi_mst_intr interrupt; writing has
                                                     no effect.                                                                */
            uint32_t            : 31;
    } bit;
  } MSTICR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000048) Interrupt Clear Register.                                  */
    
    struct {
      __IM  uint32_t ICR        : 1;            /*!< [0..0] Clear Interrupts. This register is set if any of the
                                                     interrupts below are active. A read clears the ssi_txo_intr,
                                                     ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts.
                                                     Writing to this register has no effect.                                   */
            uint32_t            : 31;
    } bit;
  } ICR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000004C) The register is used to enable the DMA Controller
                                                                    interface operation.                                       */
    
    struct {
      __IOM uint32_t RDMAE      : 1;            /*!< [0..0] Receive DMA Enable. This bit enables/disables the receive
                                                     FIFO DMA channel 
                                                     Values: 0x0 (DISABLE): Receive DMA disabled  0x1 (ENABLED):
                                                     Receive DMA enabled                                                       */
      __IOM uint32_t TDMAE      : 1;            /*!< [1..1] Transmit DMA Enable. This bit enables/disables the transmit
                                                     FIFO DMA channel. 
                                                     Values: 0x0 (DISABLE): Transmit DMA disabled  0x1 (ENABLED):
                                                     Transmit DMA enabled                                                      */
            uint32_t            : 30;
    } bit;
  } DMACR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000050) this register controls the level at which a DMA
                                                                    request is made by the transmit logic.                     */
    
    struct {
      __IOM uint32_t DMATDL     : 3;            /*!< [2..0] Transmit Data Level. This bit field controls the level
                                                     at which a DMA request is made by the transmit logic. It
                                                     is equal to the watermark level; that is, the dma_tx_req
                                                     signal is generated when the number of valid data entries
                                                     in the transmit FIFO is equal to or below this field value,
                                                     and TDMAE = 1.                                                            */
            uint32_t            : 29;
    } bit;
  } DMATDLR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000054) this register controls the level at which a DMA
                                                                    request is made by the receive logic.                      */
    
    struct {
      __IOM uint32_t DMARDLR    : 3;            /*!< [2..0] DMA Receive Data Level. This register is only valid when
                                                     SSI is configured with a set of DMA interface signals (SSI_HAS_DMA
                                                     = 1). When SSI is not configured for DMA operation, this
                                                     register will not exist and writing to its address will
                                                     have no effect; reading from its address will return zero.                */
            uint32_t            : 29;
    } bit;
  } DMARDLR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000058) This register contains the peripherals identification
                                                                    code, which is written into the register
                                                                    at configuration time using coreConsultant.                */
    
    struct {
      __IOM uint32_t IDCODE     : 32;           /*!< [31..0] Identification code. The register contains the peripheral's
                                                     identification code, which is written into the register
                                                     at configuration time using CoreConsultant.                               */
    } bit;
  } IDR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000005C) This read-only register stores the specific DW_apb_ssi
                                                                    component version.                                         */
    
    struct {
      __IOM uint32_t SSI_COMP_VERSION : 32;     /*!< [31..0] Contains the hex representation of the Synopsys component
                                                     version. Consists of ASCII value for each number in the
                                                     version, followed by *.                                                   */
    } bit;
  } SSI_VERSION_ID;
  __IOM uint32_t  DR;                           /*!< (@ 0x00000060) Data Register x                                            */
  __IM  uint32_t  RESERVED[35];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000F0) This register control the number of ssi_clk cycles
                                                                    that are delayed (from the default sample
                                                                    time) before the actual sample of the rxd
                                                                    input occurs. It is impossible to write
                                                                    to this register when the DW_apb_ssi is
                                                                    enabled.                                                   */
    
    struct {
      __IOM uint32_t RSD        : 8;            /*!< [7..0] Rxd Sample Delay. This register is used to delay the
                                                     sample of the rxd input port. Each value represents a single
                                                     ssi_clk delay on the sample of rxd. 
                                                     If this register is programmed with a value that exceeds
                                                     the depth of the internal shift registers (SSI_RX_DLY_SR_DEPTH)
                                                     zero delay will be applied to the rxd sample.                             */
            uint32_t            : 24;
    } bit;
  } RX_SAMPLE_DLY;
  __IM  uint32_t  RESERVED1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000F8) This register is used to control the driving
                                                                    edge of TXD register in DDR mode. It is
                                                                    not possible to write to this register when
                                                                    the DW_apb_ssi is enabled (SSI_EN=1).                      */
    
    struct {
      __IOM uint32_t TDE        : 8;            /*!< [7..0] TXD Drive edge - value of which decides the driving edge
                                                     of tramit data. The maximum value of this regster is =
                                                     (BAUDR/2) -1.                                                             */
            uint32_t            : 24;
    } bit;
  } TXD_DRIVE_EDGE;
} SPI_Type;                                     /*!< Size = 252 (0xfc)                                                         */



/* =========================================================================================================================== */
/* ================                                           ePWM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief PWM Generater (ePWM)
  */

typedef struct {                                /*!< (@ 0x50003000) ePWM Structure                                             */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) control register 1                                         */
    
    struct {
      __IOM uint32_t CEN        : 1;            /*!< [0..0] Counter enable                                                     */
      __IOM uint32_t UDIS       : 1;            /*!< [1..1] Update disable                                                     */
      __IOM uint32_t URS        : 1;            /*!< [2..2] Update request source                                              */
      __IOM uint32_t OPM        : 1;            /*!< [3..3] One-pulse mode                                                     */
      __IOM uint32_t DIR        : 1;            /*!< [4..4] Direction                                                          */
      __IOM uint32_t CMS        : 2;            /*!< [6..5] Center-aligned mode selection                                      */
      __IOM uint32_t ARPE       : 1;            /*!< [7..7] Auto-reload preload enable                                         */
      __IOM uint32_t CKD        : 2;            /*!< [9..8] Clock division                                                     */
      __IOM uint32_t CMP0TRGCF  : 2;            /*!< [11..10] CMP0 Trig config                                                 */
      __IOM uint32_t CMP1TRGCF  : 2;            /*!< [13..12] CMP1Trig config                                                  */
      __IOM uint32_t CMP2TRGCF  : 2;            /*!< [15..14] CMP2Trig config                                                  */
      __IOM uint32_t CMP3TRGCF  : 2;            /*!< [17..16] CMP3Trig config                                                  */
      __IOM uint32_t CMP4TRGCF  : 2;            /*!< [19..18] CMP4Trig config                                                  */
      __IOM uint32_t CMP5TRGCF  : 2;            /*!< [21..20] CMP5 Trig config                                                 */
            uint32_t            : 10;
    } bit;
  } CR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) control register 2                                         */
    
    struct {
      __IOM uint32_t CCPC       : 1;            /*!< [0..0] Capture/compare preloaded control                                  */
            uint32_t            : 1;
      __IOM uint32_t CCUS       : 1;            /*!< [2..2] Capture/compare control update selection                           */
      __IOM uint32_t CCDS       : 1;            /*!< [3..3] Capture/compare DMA selection                                      */
      __IOM uint32_t MMS        : 3;            /*!< [6..4] Master mode selection                                              */
      __IOM uint32_t TI1S       : 1;            /*!< [7..7] TI1 selection                                                      */
      __IOM uint32_t OIS1       : 1;            /*!< [8..8] Output Idle state 1                                                */
      __IOM uint32_t OIS1N      : 1;            /*!< [9..9] Output Idle state 1                                                */
      __IOM uint32_t OIS2       : 1;            /*!< [10..10] Output Idle state 2                                              */
      __IOM uint32_t OIS2N      : 1;            /*!< [11..11] Output Idle state 2                                              */
      __IOM uint32_t OIS3       : 1;            /*!< [12..12] Output Idle state 3                                              */
      __IOM uint32_t OIS3N      : 1;            /*!< [13..13] Output Idle state 3                                              */
      __IOM uint32_t OIS4       : 1;            /*!< [14..14] Output Idle state 4                                              */
            uint32_t            : 17;
    } bit;
  } CR2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000008) slave mode control register                                */
    
    struct {
      __IOM uint32_t SMS        : 3;            /*!< [2..0] Slave mode selection                                               */
            uint32_t            : 1;
      __IOM uint32_t TS         : 3;            /*!< [6..4] Trigger selection                                                  */
      __IOM uint32_t MSM        : 1;            /*!< [7..7] Master/Slave mode                                                  */
      __IOM uint32_t ETF        : 4;            /*!< [11..8] External trigger filter                                           */
      __IOM uint32_t ETPS       : 2;            /*!< [13..12] External trigger prescaler                                       */
      __IOM uint32_t ECE        : 1;            /*!< [14..14] External clock enable                                            */
      __IOM uint32_t ETP        : 1;            /*!< [15..15] External trigger polarity                                        */
            uint32_t            : 16;
    } bit;
  } SMCR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) DMA/Interrupt enable register                              */
    
    struct {
      __IOM uint32_t UIE        : 1;            /*!< [0..0] Update interrupt enable                                            */
      __IOM uint32_t CC1IE      : 1;            /*!< [1..1] Capture/Compare 1 interrupt enable                                 */
      __IOM uint32_t CC2IE      : 1;            /*!< [2..2] Capture/Compare 2 interrupt enable                                 */
      __IOM uint32_t CC3IE      : 1;            /*!< [3..3] Capture/Compare 3 interrupt enable                                 */
      __IOM uint32_t CC4IE      : 1;            /*!< [4..4] Capture/Compare 4 interrupt enable                                 */
      __IOM uint32_t COMIE      : 1;            /*!< [5..5] COM interrupt enable                                               */
      __IOM uint32_t TIE        : 1;            /*!< [6..6] Trigger interrupt enable                                           */
      __IOM uint32_t BIE        : 1;            /*!< [7..7] Break interrupt enable                                             */
      __IOM uint32_t UDE        : 1;            /*!< [8..8] Update DMA request enable                                          */
      __IOM uint32_t CC1DE      : 1;            /*!< [9..9] Capture/Compare 1 DMA request enable                               */
      __IOM uint32_t CC2DE      : 1;            /*!< [10..10] Capture/Compare 2 DMA request enable                             */
      __IOM uint32_t CC3DE      : 1;            /*!< [11..11] Capture/Compare 3 DMA request enable                             */
      __IOM uint32_t CC4DE      : 1;            /*!< [12..12] Capture/Compare 4 DMA request enable                             */
      __IOM uint32_t COMDE      : 1;            /*!< [13..13] COM DMA request enable                                           */
      __IOM uint32_t TDE        : 1;            /*!< [14..14] Trigger DMA request enable                                       */
            uint32_t            : 17;
    } bit;
  } DIER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000010) status register                                            */
    
    struct {
      __IOM uint32_t UIF        : 1;            /*!< [0..0] Update interrupt flag                                              */
      __IOM uint32_t CC1IF      : 1;            /*!< [1..1] Capture/compare 1 interrupt flag                                   */
      __IOM uint32_t CC2IF      : 1;            /*!< [2..2] Capture/Compare 2 interrupt flag                                   */
      __IOM uint32_t CC3IF      : 1;            /*!< [3..3] Capture/Compare 3 interrupt flag                                   */
      __IOM uint32_t CC4IF      : 1;            /*!< [4..4] Capture/Compare 4 interrupt flag                                   */
      __IOM uint32_t COMIF      : 1;            /*!< [5..5] COM interrupt flag                                                 */
      __IOM uint32_t TIF        : 1;            /*!< [6..6] Trigger interrupt flag                                             */
      __IOM uint32_t BIF        : 1;            /*!< [7..7] Break interrupt flag                                               */
            uint32_t            : 1;
      __IOM uint32_t CC1OF      : 1;            /*!< [9..9] Capture/Compare 1 overcapture flag                                 */
      __IOM uint32_t CC2OF      : 1;            /*!< [10..10] Capture/compare 2 overcapture flag                               */
      __IOM uint32_t CC3OF      : 1;            /*!< [11..11] Capture/Compare 3 overcapture flag                               */
      __IOM uint32_t CC4OF      : 1;            /*!< [12..12] Capture/Compare 4 overcapture flag                               */
            uint32_t            : 19;
    } bit;
  } SR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000014) event generation register                                  */
    
    struct {
      __IOM uint32_t UG         : 1;            /*!< [0..0] Update generation                                                  */
      __IOM uint32_t CC1G       : 1;            /*!< [1..1] Capture/compare 1 generation                                       */
      __IOM uint32_t CC2G       : 1;            /*!< [2..2] Capture/compare 2 generation                                       */
      __IOM uint32_t CC3G       : 1;            /*!< [3..3] Capture/compare 3 generation                                       */
      __IOM uint32_t CC4G       : 1;            /*!< [4..4] Capture/compare 4 generation                                       */
      __IOM uint32_t COMG       : 1;            /*!< [5..5] Capture/Compare control update generation                          */
      __IOM uint32_t TG         : 1;            /*!< [6..6] Trigger generation                                                 */
      __IOM uint32_t BG         : 1;            /*!< [7..7] Break generation                                                   */
            uint32_t            : 24;
    } bit;
  } EGR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000018) capture/compare mode register (output mode)                */
    
    struct {
      __IOM uint32_t CC1S       : 2;            /*!< [1..0] Capture/Compare 1 selection                                        */
      __IOM uint32_t OC1FE      : 1;            /*!< [2..2] Output Compare 1 fast enable                                       */
      __IOM uint32_t OC1PE      : 1;            /*!< [3..3] Output Compare 1 preload enable                                    */
      __IOM uint32_t OC1M       : 3;            /*!< [6..4] Output Compare 1 mode                                              */
      __IOM uint32_t OC1CE      : 1;            /*!< [7..7] Output Compare 1 clear enable                                      */
      __IOM uint32_t CC2S       : 2;            /*!< [9..8] Capture/Compare 2 selection                                        */
      __IOM uint32_t OC2FE      : 1;            /*!< [10..10] Output Compare 2 fast enable                                     */
      __IOM uint32_t OC2PE      : 1;            /*!< [11..11] Output Compare 2 preload enable                                  */
      __IOM uint32_t OC2M       : 3;            /*!< [14..12] Output Compare 2 mode                                            */
      __IOM uint32_t OC2CE      : 1;            /*!< [15..15] Output Compare 2 clear enable                                    */
            uint32_t            : 16;
    } bit;
  } CCMR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) capture/compare mode register (output mode)                */
    
    struct {
      __IOM uint32_t CC3S       : 2;            /*!< [1..0] Capture/Compare 3 selection                                        */
      __IOM uint32_t OC3FE      : 1;            /*!< [2..2] Output compare 3 fast enable                                       */
      __IOM uint32_t OC3PE      : 1;            /*!< [3..3] Output compare 3 preload enable                                    */
      __IOM uint32_t OC3M       : 3;            /*!< [6..4] Output compare 3 mode                                              */
      __IOM uint32_t OC3CE      : 1;            /*!< [7..7] Output compare 3 clear enable                                      */
      __IOM uint32_t CC4S       : 2;            /*!< [9..8] Capture/Compare 4 selection                                        */
      __IOM uint32_t OC4FE      : 1;            /*!< [10..10] Output compare 4 fast enable                                     */
      __IOM uint32_t OC4PE      : 1;            /*!< [11..11] Output compare 4 preload enable                                  */
      __IOM uint32_t OC4M       : 3;            /*!< [14..12] Output compare 4 mode                                            */
      __IOM uint32_t OC4CE      : 1;            /*!< [15..15] Output compare 4 clear enable                                    */
            uint32_t            : 16;
    } bit;
  } CCMR2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000020) capture/compare enable register                            */
    
    struct {
      __IOM uint32_t CC1E       : 1;            /*!< [0..0] Capture/Compare 1 output enable                                    */
      __IOM uint32_t CC1P       : 1;            /*!< [1..1] Capture/Compare 1 output Polarity                                  */
      __IOM uint32_t CC1NE      : 1;            /*!< [2..2] Capture/Compare 1 complementary output enable                      */
      __IOM uint32_t CC1NP      : 1;            /*!< [3..3] Capture/Compare 1 output Polarity                                  */
      __IOM uint32_t CC2E       : 1;            /*!< [4..4] Capture/Compare 2 output enable                                    */
      __IOM uint32_t CC2P       : 1;            /*!< [5..5] Capture/Compare 2 output Polarity                                  */
      __IOM uint32_t CC2NE      : 1;            /*!< [6..6] Capture/Compare 2 complementary output enable                      */
      __IOM uint32_t CC2NP      : 1;            /*!< [7..7] Capture/Compare 2 output Polarity                                  */
      __IOM uint32_t CC3E       : 1;            /*!< [8..8] Capture/Compare 3 output enable                                    */
      __IOM uint32_t CC3P       : 1;            /*!< [9..9] Capture/Compare 3 output Polarity                                  */
      __IOM uint32_t CC3NE      : 1;            /*!< [10..10] Capture/Compare 3 complementary output enable                    */
      __IOM uint32_t CC3NP      : 1;            /*!< [11..11] Capture/Compare 3 output Polarity                                */
      __IOM uint32_t CC4E       : 1;            /*!< [12..12] Capture/Compare 4 output enable                                  */
      __IOM uint32_t CC4P       : 1;            /*!< [13..13] Capture/Compare 3 output Polarity                                */
            uint32_t            : 18;
    } bit;
  } CCER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000024) counter                                                    */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] counter value                                                     */
            uint32_t            : 16;
    } bit;
  } CNT;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000028) prescaler                                                  */
    
    struct {
      __IOM uint32_t PSC        : 16;           /*!< [15..0] Prescaler value                                                   */
            uint32_t            : 16;
    } bit;
  } PSC;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000002C) auto-reload register                                       */
    
    struct {
      __IOM uint32_t ARR        : 16;           /*!< [15..0] Auto-reload value                                                 */
            uint32_t            : 16;
    } bit;
  } ARR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000030) repetition counter register                                */
    
    struct {
      __IOM uint32_t REP        : 8;            /*!< [7..0] Repetition counter value                                           */
      __IOM uint32_t REP_CMP03  : 8;            /*!< [15..8] Repetition counter value for cmp0-3                               */
      __IOM uint32_t REP_CMP4   : 8;            /*!< [23..16] Repetition counter value for cmp4                                */
      __IOM uint32_t REP_CMP5   : 8;            /*!< [31..24] Repetition counter value for cmp5                                */
    } bit;
  } RCR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000034) capture/compare register 1                                 */
    
    struct {
      __IOM uint32_t CCR1       : 16;           /*!< [15..0] Capture/Compare 1 value                                           */
            uint32_t            : 16;
    } bit;
  } CCR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000038) capture/compare register 2                                 */
    
    struct {
      __IOM uint32_t CCR2       : 16;           /*!< [15..0] Capture/Compare 2 value                                           */
            uint32_t            : 16;
    } bit;
  } CCR2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000003C) capture/compare register 3                                 */
    
    struct {
      __IOM uint32_t CCR3       : 16;           /*!< [15..0] Capture/Compare value                                             */
            uint32_t            : 16;
    } bit;
  } CCR3;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000040) capture/compare register 4                                 */
    
    struct {
      __IOM uint32_t CCR4       : 16;           /*!< [15..0] Capture/Compare value                                             */
            uint32_t            : 16;
    } bit;
  } CCR4;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000044) break and dead-time register                               */
    
    struct {
      __IOM uint32_t DTG        : 8;            /*!< [7..0] Dead-time generator setup                                          */
      __IOM uint32_t LOCK       : 2;            /*!< [9..8] Lock configuration                                                 */
      __IOM uint32_t OSSI       : 1;            /*!< [10..10] Off-state selection for Idle mode                                */
      __IOM uint32_t OSSR       : 1;            /*!< [11..11] Off-state selection for Run mode                                 */
      __IOM uint32_t BKE        : 1;            /*!< [12..12] Break enable                                                     */
      __IOM uint32_t BKP        : 1;            /*!< [13..13] Break polarity                                                   */
      __IOM uint32_t AOE        : 1;            /*!< [14..14] Automatic output enable                                          */
      __IOM uint32_t MOE        : 1;            /*!< [15..15] Main output enable                                               */
            uint32_t            : 16;
    } bit;
  } BDTR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000048) DMA control register                                       */
    
    struct {
      __IOM uint32_t DBA        : 5;            /*!< [4..0] DMA base address                                                   */
            uint32_t            : 3;
      __IOM uint32_t DBL        : 5;            /*!< [12..8] DMA burst length                                                  */
            uint32_t            : 19;
    } bit;
  } DCR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000004C) DMA address for full transfer                              */
    
    struct {
      __IOM uint32_t DMAB       : 16;           /*!< [15..0] DMA register for burst accesses                                   */
            uint32_t            : 16;
    } bit;
  } DMAR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000050) Compare 01 registers                                       */
    
    struct {
      __IOM uint32_t CMP0       : 16;           /*!< [15..0] CMP0 Value                                                        */
      __IOM uint32_t CMP1       : 16;           /*!< [31..16] CMP1 Value                                                       */
    } bit;
  } CMP01;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000054) Compare 23 registers                                       */
    
    struct {
      __IOM uint32_t CMP2       : 16;           /*!< [15..0] CMP2 Value                                                        */
      __IOM uint32_t CMP3       : 16;           /*!< [31..16] CMP3 Value                                                       */
    } bit;
  } CMP23;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000058) Compare 45 registers                                       */
    
    struct {
      __IOM uint32_t CMP4       : 16;           /*!< [15..0] CMP4 Value                                                        */
      __IOM uint32_t CMP5       : 16;           /*!< [31..16] CMP5 Value                                                       */
    } bit;
  } CMP45;
} ePWM_Type;                                    /*!< Size = 92 (0x5c)                                                          */



/* =========================================================================================================================== */
/* ================                                          SYSCFG                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief System configuration (SYSCFG)
  */

typedef struct {                                /*!< (@ 0x50005000) SYSCFG Structure                                           */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) Chip Id Register                                           */
    
    struct {
      __IOM uint32_t CHIPID     : 32;           /*!< [31..0] Chip Identification.                                              */
    } bit;
  } CHIPID;
  __IM  uint32_t  RESERVED[7];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000020) FLASH Read Protect Register                                */
    
    struct {
      __IOM uint32_t RDP        : 1;            /*!< [0..0] Read protect enable.                                               */
            uint32_t            : 31;
    } bit;
  } RDP;
  __IM  uint32_t  RESERVED1[55];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000100) RAM0 ECC Interrupt Register                                */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] RAM ECC Interrupt Enable.                                          */
            uint32_t            : 31;
    } bit;
  } RAM0IER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000104) RAM0 ECC Interrupt Status Register                         */
    
    struct {
      __IM  uint32_t ERR        : 2;            /*!< [1..0] When read RAM, ECC detects 1 bit err in one word, and
                                                     correct this err bit.0: NOERR. No ecc err. 1: ERR1b. When
                                                     read RAM, ECC detects 1 bit err, and correct this err bit.
                                                     2: ERR2B. When read RAM, ECC detects 2 bit err.                           */
            uint32_t            : 30;
    } bit;
  } RAM0ISR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000108) RAM0 ECC Interrupt Status Clear Register                   */
    
    struct {
      __OM  uint32_t ERRCLR     : 1;            /*!< [0..0] Write 1 clear RAMECCSR.                                            */
            uint32_t            : 31;
    } bit;
  } RAM0ICLR;
  __IM  uint32_t  RESERVED2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000110) RAM0 ECC Syndrome Register                                 */
    
    struct {
      __IM  uint32_t SYND       : 7;            /*!< [6..0] ECC Syndrome, There are RAM ECC err if this val is not
                                                     0. Use syndrome can find witch bit err if RAMCCSR is 1;                   */
            uint32_t            : 25;
    } bit;
  } RAM0SYND;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000114) RAM0 ECC Inject Low Register                               */
    
    struct {
      __IOM uint32_t INJL       : 32;           /*!< [31..0] Note: only when DBGEN = 1, writing this value is effective.
                                                     When this val is not 0, read ram will lead to ecc error.
                                                     For example, if this value is 0x8, read ram will lead to
                                                     4th ram Bit error.                                                        */
    } bit;
  } RAM0INJL;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000118) RAM0 ECC Interrupt Status Clear Register                   */
    
    struct {
      __IOM uint32_t INJH       : 7;            /*!< [6..0] Note: only when DBGEN = 1, writing this value is effective.
                                                     When this val is not 0, read ram will lead to ecc error.
                                                     For example, if this value is 0x8, read ram will lead to
                                                     36th ram Bit error.                                                       */
            uint32_t            : 25;
    } bit;
  } RAM0INJH;
  __IM  uint32_t  RESERVED3[5];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000130) RAM1 ECC Interrupt Register                                */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] RAM1 ECC Interrupt Enable.                                         */
            uint32_t            : 31;
    } bit;
  } RAM1IER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000134) RAM1 ECC Interrupt Status Register                         */
    
    struct {
      __IM  uint32_t ERR        : 2;            /*!< [1..0] When read RAM, ECC detects 1 bit err in one word, and
                                                     correct this err bit.0: NOERR. No ecc err. 1: ERR1b. When
                                                     read RAM, ECC detects 1 bit err, and correct this err bit.
                                                     2: ERR2B. When read RAM, ECC detects 2 bit err.                           */
            uint32_t            : 30;
    } bit;
  } RAM1ISR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000138) RAM1 ECC Interrupt Status Clear Register                   */
    
    struct {
      __OM  uint32_t ERRCLR     : 1;            /*!< [0..0] Write 1 clear RAMECCSR.                                            */
            uint32_t            : 31;
    } bit;
  } RAM1ICLR;
  __IM  uint32_t  RESERVED4;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000140) RAM1 ECC Syndrome Register                                 */
    
    struct {
      __IM  uint32_t SYND       : 7;            /*!< [6..0] ECC Syndrome, There are RAM ECC err if this val is not
                                                     0. Use syndrome can find witch bit err if RAMCCSR is 1;                   */
            uint32_t            : 25;
    } bit;
  } RAM1SYND;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000144) RAM1 ECC Inject Low Register                               */
    
    struct {
      __IOM uint32_t INJL       : 32;           /*!< [31..0] Note: only when DBGEN = 1, writing this value is effective.
                                                     When this val is not 0, read ram will lead to ecc error.
                                                     For example, if this value is 0x8, read ram will lead to
                                                     4th ram Bit error.                                                        */
    } bit;
  } RAM1INJL;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000148) RAM1 ECC Interrupt Status Clear Register                   */
    
    struct {
      __IOM uint32_t INJH       : 7;            /*!< [6..0] Note: only when DBGEN = 1, writing this value is effective.
                                                     When this val is not 0, read ram will lead to ecc error.
                                                     For example, if this value is 0x8, read ram will lead to
                                                     36th ram Bit error.                                                       */
            uint32_t            : 25;
    } bit;
  } RAM1INJH;
  __IM  uint32_t  RESERVED5[45];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000200) ADC0 Trigger Selection Register.Trigger signal
                                                                    selection. Whenever any of the trigger source
                                                                    signals (ORed together) becomes active,
                                                                    the trigger output signal is toggled.                      */
    
    struct {
      __IOM uint32_t ePWM_CMP0  : 1;            /*!< [0..0] ePWM_CMP0 trigger enable                                           */
      __IOM uint32_t ePWM_CMP1  : 1;            /*!< [1..1] ePWM_CMP1 trigger enable                                           */
      __IOM uint32_t ePWM_CMP2  : 1;            /*!< [2..2] ePWM_CMP2 trigger enable                                           */
      __IOM uint32_t ePWM_CMP3  : 1;            /*!< [3..3] ePWM_CMP3 trigger enable                                           */
      __IOM uint32_t ePWM_CMP4  : 1;            /*!< [4..4] ePWM_CMP4 trigger enable                                           */
      __IOM uint32_t ePWM_CMP5  : 1;            /*!< [5..5] ePWM_CMP5 trigger enable                                           */
      __IOM uint32_t ePWM_TRGO  : 1;            /*!< [6..6] ePWM_TRGO trigger enable                                           */
      __IOM uint32_t ePWM_OC0   : 1;            /*!< [7..7] ePWM_OC0 trigger enable                                            */
      __IOM uint32_t ePWM_OC1   : 1;            /*!< [8..8] ePWM_OC1 trigger enable                                            */
      __IOM uint32_t ePWM_OC2   : 1;            /*!< [9..9] ePWM_OC2 trigger enable                                            */
      __IOM uint32_t ePWM_OC3   : 1;            /*!< [10..10] ePWM_OC3 trigger enable                                          */
      __IOM uint32_t TIM0_UP    : 1;            /*!< [11..11] TIM0_UP trigger enable                                           */
      __IOM uint32_t TIM1_UP    : 1;            /*!< [12..12] TIM1_UP trigger enable                                           */
      __IOM uint32_t TIM2_UP    : 1;            /*!< [13..13] TIM2_UP trigger enable                                           */
      __IOM uint32_t eDIAG_CMP  : 1;            /*!< [14..14] eDIAG CMP trigger enable                                         */
            uint32_t            : 17;
    } bit;
  } ADC0TRG;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000204) ADC1 Trigger Selection Register.Trigger signal
                                                                    selection. Whenever any of the trigger source
                                                                    signals (ORed together) becomes active,
                                                                    the trigger output signal is toggled.                      */
    
    struct {
      __IOM uint32_t ePWM_CMP0  : 1;            /*!< [0..0] ePWM_CMP0 trigger enable                                           */
      __IOM uint32_t ePWM_CMP1  : 1;            /*!< [1..1] ePWM_CMP1 trigger enable                                           */
      __IOM uint32_t ePWM_CMP2  : 1;            /*!< [2..2] ePWM_CMP2 trigger enable                                           */
      __IOM uint32_t ePWM_CMP3  : 1;            /*!< [3..3] ePWM_CMP3 trigger enable                                           */
      __IOM uint32_t ePWM_CMP4  : 1;            /*!< [4..4] ePWM_CMP4 trigger enable                                           */
      __IOM uint32_t ePWM_CMP5  : 1;            /*!< [5..5] ePWM_CMP5 trigger enable                                           */
      __IOM uint32_t ePWM_TRGO  : 1;            /*!< [6..6] ePWM_TRGO trigger enable                                           */
      __IOM uint32_t ePWM_OC0   : 1;            /*!< [7..7] ePWM_OC0 trigger enable                                            */
      __IOM uint32_t ePWM_OC1   : 1;            /*!< [8..8] ePWM_OC1 trigger enable                                            */
      __IOM uint32_t ePWM_OC2   : 1;            /*!< [9..9] ePWM_OC2 trigger enable                                            */
      __IOM uint32_t ePWM_OC3   : 1;            /*!< [10..10] ePWM_OC3 trigger enable                                          */
      __IOM uint32_t TIM0_UP    : 1;            /*!< [11..11] TIM0_UP trigger enable                                           */
      __IOM uint32_t TIM1_UP    : 1;            /*!< [12..12] TIM1_UP trigger enable                                           */
      __IOM uint32_t TIM2_UP    : 1;            /*!< [13..13] TIM2_UP trigger enable                                           */
      __IOM uint32_t eDIAG_CMP  : 1;            /*!< [14..14] eDIAG CMP trigger enable                                         */
            uint32_t            : 17;
    } bit;
  } ADC1TRG;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000208) TIM0 Trigger Selection RegisterTrigger signal
                                                                    selection. Whenever any of the trigger source
                                                                    signals (ORed together) becomes active,
                                                                    the trigger output signal is toggled.                      */
    
    struct {
      __IOM uint32_t ePWM_CMP0  : 1;            /*!< [0..0] ePWM_CMP0 trigger enable                                           */
      __IOM uint32_t ePWM_CMP1  : 1;            /*!< [1..1] ePWM_CMP1 trigger enable                                           */
      __IOM uint32_t ePWM_CMP2  : 1;            /*!< [2..2] ePWM_CMP2 trigger enable                                           */
      __IOM uint32_t ePWM_CMP3  : 1;            /*!< [3..3] ePWM_CMP3 trigger enable                                           */
      __IOM uint32_t ePWM_CMP4  : 1;            /*!< [4..4] ePWM_CMP4 trigger enable                                           */
      __IOM uint32_t ePWM_CMP5  : 1;            /*!< [5..5] ePWM_CMP5 trigger enable                                           */
      __IOM uint32_t ePWM_TRGO  : 1;            /*!< [6..6] ePWM_TRGO trigger enable                                           */
      __IOM uint32_t ePWM_OC0   : 1;            /*!< [7..7] ePWM_OC0 trigger enable                                            */
      __IOM uint32_t ePWM_OC1   : 1;            /*!< [8..8] ePWM_OC1 trigger enable                                            */
      __IOM uint32_t ePWM_OC2   : 1;            /*!< [9..9] ePWM_OC2 trigger enable                                            */
      __IOM uint32_t ePWM_OC3   : 1;            /*!< [10..10] ePWM_OC3 trigger enable                                          */
      __IOM uint32_t TIM0_UP    : 1;            /*!< [11..11] TIM0_UP trigger enable                                           */
      __IOM uint32_t TIM1_UP    : 1;            /*!< [12..12] TIM1_UP trigger enable                                           */
      __IOM uint32_t TIM2_UP    : 1;            /*!< [13..13] TIM2_UP trigger enable                                           */
      __IOM uint32_t eDIAG_CMP  : 1;            /*!< [14..14] eDIAG CMP trigger enable                                         */
            uint32_t            : 17;
    } bit;
  } TIM0TRG;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000020C) TIM1 Trigger Selection RegisterTrigger signal
                                                                    selection. Whenever any of the trigger source
                                                                    signals (ORed together) becomes active,
                                                                    the trigger output signal is toggled.                      */
    
    struct {
      __IOM uint32_t ePWM_CMP0  : 1;            /*!< [0..0] ePWM_CMP0 trigger enable                                           */
      __IOM uint32_t ePWM_CMP1  : 1;            /*!< [1..1] ePWM_CMP1 trigger enable                                           */
      __IOM uint32_t ePWM_CMP2  : 1;            /*!< [2..2] ePWM_CMP2 trigger enable                                           */
      __IOM uint32_t ePWM_CMP3  : 1;            /*!< [3..3] ePWM_CMP3 trigger enable                                           */
      __IOM uint32_t ePWM_CMP4  : 1;            /*!< [4..4] ePWM_CMP4 trigger enable                                           */
      __IOM uint32_t ePWM_CMP5  : 1;            /*!< [5..5] ePWM_CMP5 trigger enable                                           */
      __IOM uint32_t ePWM_TRGO  : 1;            /*!< [6..6] ePWM_TRGO trigger enable                                           */
      __IOM uint32_t ePWM_OC0   : 1;            /*!< [7..7] ePWM_OC0 trigger enable                                            */
      __IOM uint32_t ePWM_OC1   : 1;            /*!< [8..8] ePWM_OC1 trigger enable                                            */
      __IOM uint32_t ePWM_OC2   : 1;            /*!< [9..9] ePWM_OC2 trigger enable                                            */
      __IOM uint32_t ePWM_OC3   : 1;            /*!< [10..10] ePWM_OC3 trigger enable                                          */
      __IOM uint32_t TIM0_UP    : 1;            /*!< [11..11] TIM0_UP trigger enable                                           */
      __IOM uint32_t TIM1_UP    : 1;            /*!< [12..12] TIM1_UP trigger enable                                           */
      __IOM uint32_t TIM2_UP    : 1;            /*!< [13..13] TIM2_UP trigger enable                                           */
      __IOM uint32_t eDIAG_CMP  : 1;            /*!< [14..14] eDIAG CMP trigger enable                                         */
            uint32_t            : 17;
    } bit;
  } TIM1TRG;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000210) TIM2 Trigger Selection RegisterTrigger signal
                                                                    selection. Whenever any of the trigger source
                                                                    signals (ORed together) becomes active,
                                                                    the trigger output signal is toggled.                      */
    
    struct {
      __IOM uint32_t ePWM_CMP0  : 1;            /*!< [0..0] ePWM_CMP0 trigger enable                                           */
      __IOM uint32_t ePWM_CMP1  : 1;            /*!< [1..1] ePWM_CMP1 trigger enable                                           */
      __IOM uint32_t ePWM_CMP2  : 1;            /*!< [2..2] ePWM_CMP2 trigger enable                                           */
      __IOM uint32_t ePWM_CMP3  : 1;            /*!< [3..3] ePWM_CMP3 trigger enable                                           */
      __IOM uint32_t ePWM_CMP4  : 1;            /*!< [4..4] ePWM_CMP4 trigger enable                                           */
      __IOM uint32_t ePWM_CMP5  : 1;            /*!< [5..5] ePWM_CMP5 trigger enable                                           */
      __IOM uint32_t ePWM_TRGO  : 1;            /*!< [6..6] ePWM_TRGO trigger enable                                           */
      __IOM uint32_t ePWM_OC0   : 1;            /*!< [7..7] ePWM_OC0 trigger enable                                            */
      __IOM uint32_t ePWM_OC1   : 1;            /*!< [8..8] ePWM_OC1 trigger enable                                            */
      __IOM uint32_t ePWM_OC2   : 1;            /*!< [9..9] ePWM_OC2 trigger enable                                            */
      __IOM uint32_t ePWM_OC3   : 1;            /*!< [10..10] ePWM_OC3 trigger enable                                          */
      __IOM uint32_t TIM0_UP    : 1;            /*!< [11..11] TIM0_UP trigger enable                                           */
      __IOM uint32_t TIM1_UP    : 1;            /*!< [12..12] TIM1_UP trigger enable                                           */
      __IOM uint32_t TIM2_UP    : 1;            /*!< [13..13] TIM2_UP trigger enable                                           */
      __IOM uint32_t eDIAG_CMP  : 1;            /*!< [14..14] eDIAG CMP trigger enable                                         */
            uint32_t            : 17;
    } bit;
  } TIM2TRG;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000214) Trigeger Out0 Selection RegisterTrigger signal
                                                                    selection. Whenever any of the trigger source
                                                                    signals (ORed together) becomes active,
                                                                    the trigger output signal is toggled.                      */
    
    struct {
      __IOM uint32_t ePWM_CMP0  : 1;            /*!< [0..0] ePWM_CMP0 trigger enable                                           */
      __IOM uint32_t ePWM_CMP1  : 1;            /*!< [1..1] ePWM_CMP1 trigger enable                                           */
      __IOM uint32_t ePWM_CMP2  : 1;            /*!< [2..2] ePWM_CMP2 trigger enable                                           */
      __IOM uint32_t ePWM_CMP3  : 1;            /*!< [3..3] ePWM_CMP3 trigger enable                                           */
      __IOM uint32_t ePWM_CMP4  : 1;            /*!< [4..4] ePWM_CMP4 trigger enable                                           */
      __IOM uint32_t ePWM_CMP5  : 1;            /*!< [5..5] ePWM_CMP5 trigger enable                                           */
      __IOM uint32_t ePWM_TRGO  : 1;            /*!< [6..6] ePWM_TRGO trigger enable                                           */
      __IOM uint32_t ePWM_OC0   : 1;            /*!< [7..7] ePWM_OC0 trigger enable                                            */
      __IOM uint32_t ePWM_OC1   : 1;            /*!< [8..8] ePWM_OC1 trigger enable                                            */
      __IOM uint32_t ePWM_OC2   : 1;            /*!< [9..9] ePWM_OC2 trigger enable                                            */
      __IOM uint32_t ePWM_OC3   : 1;            /*!< [10..10] ePWM_OC3 trigger enable                                          */
      __IOM uint32_t TIM0_UP    : 1;            /*!< [11..11] TIM0_UP trigger enable                                           */
      __IOM uint32_t TIM1_UP    : 1;            /*!< [12..12] TIM1_UP trigger enable                                           */
      __IOM uint32_t TIM2_UP    : 1;            /*!< [13..13] TIM2_UP trigger enable                                           */
      __IOM uint32_t eDIAG_CMP  : 1;            /*!< [14..14] eDIAG CMP trigger enable                                         */
            uint32_t            : 17;
    } bit;
  } TRGO0;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000218) Trigeger Out1 Selection RegisterTrigger signal
                                                                    selection. Whenever any of the trigger source
                                                                    signals (ORed together) becomes active,
                                                                    the trigger output signal is toggled.                      */
    
    struct {
      __IOM uint32_t ePWM_CMP0  : 1;            /*!< [0..0] ePWM_CMP0 trigger enable                                           */
      __IOM uint32_t ePWM_CMP1  : 1;            /*!< [1..1] ePWM_CMP1 trigger enable                                           */
      __IOM uint32_t ePWM_CMP2  : 1;            /*!< [2..2] ePWM_CMP2 trigger enable                                           */
      __IOM uint32_t ePWM_CMP3  : 1;            /*!< [3..3] ePWM_CMP3 trigger enable                                           */
      __IOM uint32_t ePWM_CMP4  : 1;            /*!< [4..4] ePWM_CMP4 trigger enable                                           */
      __IOM uint32_t ePWM_CMP5  : 1;            /*!< [5..5] ePWM_CMP5 trigger enable                                           */
      __IOM uint32_t ePWM_TRGO  : 1;            /*!< [6..6] ePWM_TRGO trigger enable                                           */
      __IOM uint32_t ePWM_OC0   : 1;            /*!< [7..7] ePWM_OC0 trigger enable                                            */
      __IOM uint32_t ePWM_OC1   : 1;            /*!< [8..8] ePWM_OC1 trigger enable                                            */
      __IOM uint32_t ePWM_OC2   : 1;            /*!< [9..9] ePWM_OC2 trigger enable                                            */
      __IOM uint32_t ePWM_OC3   : 1;            /*!< [10..10] ePWM_OC3 trigger enable                                          */
      __IOM uint32_t TIM0_UP    : 1;            /*!< [11..11] TIM0_UP trigger enable                                           */
      __IOM uint32_t TIM1_UP    : 1;            /*!< [12..12] TIM1_UP trigger enable                                           */
      __IOM uint32_t TIM2_UP    : 1;            /*!< [13..13] TIM2_UP trigger enable                                           */
      __IOM uint32_t eDIAG_CMP  : 1;            /*!< [14..14] eDIAG CMP trigger enable                                         */
            uint32_t            : 17;
    } bit;
  } TRGO1;
  __IM  uint32_t  RESERVED6[57];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000300) Address Remap Register                                     */
    
    struct {
      __IOM uint32_t FLASH1     : 1;            /*!< [0..0] 0, Do not remap, only 0x11000000 area(idbus access)1,
                                                     Flash1 remap enable, add 0x30000000 area(sysbus access)                   */
      __IOM uint32_t RAM        : 1;            /*!< [1..1] 0, Do not remap RAM0: 0x20000000 area (sysbus access)
                                                     RAM1: 0x20002000 area (sysbus access)1, remap enable  RAM0:
                                                     add 0x02000000 area (id accessea) RAM1: add 0x02002000
                                                     area (id accessea)                                                        */
            uint32_t            : 30;
    } bit;
  } REMAPR;
  __IM  uint32_t  RESERVED7[703];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000E00) Debug Enable Register                                      */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] When KEY is 0xA5, write 0 disable DBG mode, write 1 enable
                                                     DBG mode.                                                                 */
            uint32_t            : 23;
      __IOM uint32_t KEY        : 8;            /*!< [31..24] Only when KEY is 0xA5, and DBGLOCK bit0 is reset, write
                                                     EN(bit0) is effective.                                                    */
    } bit;
  } DBGEN;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000E04) Debug Lock Register                                        */
    
    struct {
      __IOM uint32_t LOCK       : 1;            /*!< [0..0] When KEY is 0x5A, write 0 to unlock DBGEN bit0(EN), write
                                                     1 to lock DBGEN bit0(EN).                                                 */
            uint32_t            : 23;
      __IOM uint32_t KEY        : 8;            /*!< [31..24] Only when KEY is 0x5A, write LOCK(bit0) is effective.            */
    } bit;
  } DBGLOCK;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000E08) Debug MODE register                                        */
    
    struct {
      __IOM uint32_t MODE       : 3;            /*!< [2..0] Select DBG mode, and start DBG test.                               */
            uint32_t            : 29;
    } bit;
  } DBGMODE;
  __IM  uint32_t  RESERVED8[61];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000F00) DFT Enable Register                                        */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] When KEY is 0xA5, write 0 disableDFT mode, write 1 enable
                                                     DFT mode.                                                                 */
            uint32_t            : 23;
      __IOM uint32_t KEY        : 8;            /*!< [31..24] Only when KEY is 0xA5, and DFTLOCK bit0 is reset, write
                                                     EN(bit0) is effective.                                                    */
    } bit;
  } DFTEN;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000F04) DFT Lock Register                                          */
    
    struct {
      __IOM uint32_t LOCK       : 1;            /*!< [0..0] When KEY is 0x5A, write 0 to unlock DFTEN bit0(EN), write
                                                     1 to lock DFTEN bit0(EN).                                                 */
            uint32_t            : 23;
      __IOM uint32_t KEY        : 8;            /*!< [31..24] Only when KEY is 0x5A, write LOCK(bit0) is effective.            */
    } bit;
  } DFTLOCK;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000F08) DFT MODE register                                          */
    
    struct {
      __IOM uint32_t MODE       : 4;            /*!< [3..0] Select DFT mode, and start DFT test.                               */
            uint32_t            : 28;
    } bit;
  } DFTMODE;
  __IM  uint32_t  RESERVED9;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000F10) OSC H Enable Register                                      */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Writting 1 to enable OSCH after OSCHENR Key is written
                                                     0x5A.                                                                     */
            uint32_t            : 23;
      __OM  uint32_t KEY        : 8;            /*!< [31..24] OSCH EN key. To write OSCHEN, this field must be 0x5A.           */
    } bit;
  } OSCHENR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000F14) OSC H Enable Lock Register                                 */
    
    struct {
      __IOM uint32_t LOCK       : 1;            /*!< [0..0] Only when KEY is matched, writing this bit is effective.           */
            uint32_t            : 23;
      __OM  uint32_t KEY        : 8;            /*!< [31..24] OSCH LOCK key. To write OSCHLOCK, this field must be
                                                     0x5A.                                                                     */
    } bit;
  } OSCHENLOCKR;
} SYSCFG_Type;                                  /*!< Size = 3864 (0xf18)                                                       */



/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief System configuration unit (DMA)
  */

typedef struct {                                /*!< (@ 0x400F1000) DMA Structure                                              */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) DMA interrupt status register (DMA_ISR)                    */
    
    struct {
      __IOM uint32_t GIF1       : 1;            /*!< [0..0] Channel 1 Global interrupt flag                                    */
      __IOM uint32_t TCIF1      : 1;            /*!< [1..1] Channel 1 Transfer Complete flag                                   */
      __IOM uint32_t HTIF1      : 1;            /*!< [2..2] Channel 1 Half Transfer Complete flag                              */
      __IOM uint32_t TEIF1      : 1;            /*!< [3..3] Channel 1 Transfer Error flag                                      */
      __IOM uint32_t GIF2       : 1;            /*!< [4..4] Channel 2 Global interrupt flag                                    */
      __IOM uint32_t TCIF2      : 1;            /*!< [5..5] Channel 2 Transfer Complete flag                                   */
      __IOM uint32_t HTIF2      : 1;            /*!< [6..6] Channel 2 Half Transfer Complete flag                              */
      __IOM uint32_t TEIF2      : 1;            /*!< [7..7] Channel 2 Transfer Error flag                                      */
      __IOM uint32_t GIF3       : 1;            /*!< [8..8] Channel 3 Global interrupt flag                                    */
      __IOM uint32_t TCIF3      : 1;            /*!< [9..9] Channel 3 Transfer Complete flag                                   */
      __IOM uint32_t HTIF3      : 1;            /*!< [10..10] Channel 3 Half Transfer Complete flag                            */
      __IOM uint32_t TEIF3      : 1;            /*!< [11..11] Channel 3 Transfer Error flag                                    */
      __IOM uint32_t GIF4       : 1;            /*!< [12..12] Channel 4 Global interrupt flag                                  */
      __IOM uint32_t TCIF4      : 1;            /*!< [13..13] Channel 4 Transfer Complete flag                                 */
      __IOM uint32_t HTIF4      : 1;            /*!< [14..14] Channel 4 Half Transfer Complete flag                            */
      __IOM uint32_t TEIF4      : 1;            /*!< [15..15] Channel 4 Transfer Error flag                                    */
      __IOM uint32_t GIF5       : 1;            /*!< [16..16] Channel 5 Global interrupt flag                                  */
      __IOM uint32_t TCIF5      : 1;            /*!< [17..17] Channel 5 Transfer Complete flag                                 */
      __IOM uint32_t HTIF5      : 1;            /*!< [18..18] Channel 5 Half Transfer Complete flag                            */
      __IOM uint32_t TEIF5      : 1;            /*!< [19..19] Channel 5 Transfer Error flag                                    */
      __IOM uint32_t GIF6       : 1;            /*!< [20..20] Channel 6 Global interrupt flag                                  */
      __IOM uint32_t TCIF6      : 1;            /*!< [21..21] Channel 6 Transfer Complete flag                                 */
      __IOM uint32_t HTIF6      : 1;            /*!< [22..22] Channel 6 Half Transfer Complete flag                            */
      __IOM uint32_t TEIF6      : 1;            /*!< [23..23] Channel 6 Transfer Error flag                                    */
      __IOM uint32_t GIF7       : 1;            /*!< [24..24] Channel 7 Global interrupt flag                                  */
      __IOM uint32_t TCIF7      : 1;            /*!< [25..25] Channel 7 Transfer Complete flag                                 */
      __IOM uint32_t HTIF7      : 1;            /*!< [26..26] Channel 7 Half Transfer Complete flag                            */
      __IOM uint32_t TEIF7      : 1;            /*!< [27..27] Channel 7 Transfer Error flag                                    */
            uint32_t            : 4;
    } bit;
  } ISR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) DMA interrupt flag clear register (DMA_IFCR)               */
    
    struct {
      __IOM uint32_t CGIF1      : 1;            /*!< [0..0] Channel 1 Global interrupt clear                                   */
      __IOM uint32_t CTCIF1     : 1;            /*!< [1..1] Channel 1 Transfer Complete clear                                  */
      __IOM uint32_t CHTIF1     : 1;            /*!< [2..2] Channel 1 Half Transfer clear                                      */
      __IOM uint32_t CTEIF1     : 1;            /*!< [3..3] Channel 1 Transfer Error clear                                     */
      __IOM uint32_t CGIF2      : 1;            /*!< [4..4] Channel 2 Global interrupt clear                                   */
      __IOM uint32_t CTCIF2     : 1;            /*!< [5..5] Channel 2 Transfer Complete clear                                  */
      __IOM uint32_t CHTIF2     : 1;            /*!< [6..6] Channel 2 Half Transfer clear                                      */
      __IOM uint32_t CTEIF2     : 1;            /*!< [7..7] Channel 2 Transfer Error clear                                     */
      __IOM uint32_t CGIF3      : 1;            /*!< [8..8] Channel 3 Global interrupt clear                                   */
      __IOM uint32_t CTCIF3     : 1;            /*!< [9..9] Channel 3 Transfer Complete clear                                  */
      __IOM uint32_t CHTIF3     : 1;            /*!< [10..10] Channel 3 Half Transfer clear                                    */
      __IOM uint32_t CTEIF3     : 1;            /*!< [11..11] Channel 3 Transfer Error clear                                   */
      __IOM uint32_t CGIF4      : 1;            /*!< [12..12] Channel 4 Global interrupt clear                                 */
      __IOM uint32_t CTCIF4     : 1;            /*!< [13..13] Channel 4 Transfer Complete clear                                */
      __IOM uint32_t CHTIF4     : 1;            /*!< [14..14] Channel 4 Half Transfer clear                                    */
      __IOM uint32_t CTEIF4     : 1;            /*!< [15..15] Channel 4 Transfer Error clear                                   */
      __IOM uint32_t CGIF5      : 1;            /*!< [16..16] Channel 5 Global interrupt clear                                 */
      __IOM uint32_t CTCIF5     : 1;            /*!< [17..17] Channel 5 Transfer Complete clear                                */
      __IOM uint32_t CHTIF5     : 1;            /*!< [18..18] Channel 5 Half Transfer clear                                    */
      __IOM uint32_t CTEIF5     : 1;            /*!< [19..19] Channel 5 Transfer Error clear                                   */
      __IOM uint32_t CGIF6      : 1;            /*!< [20..20] Channel 6 Global interrupt clear                                 */
      __IOM uint32_t CTCIF6     : 1;            /*!< [21..21] Channel 6 Transfer Complete clear                                */
      __IOM uint32_t CHTIF6     : 1;            /*!< [22..22] Channel 6 Half Transfer clear                                    */
      __IOM uint32_t CTEIF6     : 1;            /*!< [23..23] Channel 6 Transfer Error clear                                   */
      __IOM uint32_t CGIF7      : 1;            /*!< [24..24] Channel 7 Global interrupt clear                                 */
      __IOM uint32_t CTCIF7     : 1;            /*!< [25..25] Channel 7 Transfer Complete clear                                */
      __IOM uint32_t CHTIF7     : 1;            /*!< [26..26] Channel 7 Half Transfer clear                                    */
      __IOM uint32_t CTEIF7     : 1;            /*!< [27..27] Channel 7 Transfer Error clear                                   */
            uint32_t            : 4;
    } bit;
  } IFCR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000008) DMA channel configuration register (DMA_CCR)               */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t HTIE       : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t TEIE       : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DIR        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t CIRC       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PINC       : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MINC       : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PSIZE      : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MSIZE      : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t MEM2MEM    : 1;            /*!< [14..14] Memory to memory mode                                            */
            uint32_t            : 17;
    } bit;
  } CCR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) DMA channel 1 number of data register                      */
    
    struct {
      __IOM uint32_t NDT        : 16;           /*!< [15..0] Number of data to transfer                                        */
            uint32_t            : 16;
    } bit;
  } CNDTR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000010) DMA channel 1 peripheral address register                  */
    
    struct {
      __IOM uint32_t PA         : 32;           /*!< [31..0] Peripheral address                                                */
    } bit;
  } CPAR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000014) DMA channel 1 memory address register                      */
    
    struct {
      __IOM uint32_t MA         : 32;           /*!< [31..0] Memory address                                                    */
    } bit;
  } CMAR1;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) DMA channel configuration register (DMA_CCR)               */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t HTIE       : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t TEIE       : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DIR        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t CIRC       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PINC       : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MINC       : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PSIZE      : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MSIZE      : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t MEM2MEM    : 1;            /*!< [14..14] Memory to memory mode                                            */
            uint32_t            : 17;
    } bit;
  } CCR2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000020) DMA channel 2 number of data register                      */
    
    struct {
      __IOM uint32_t NDT        : 16;           /*!< [15..0] Number of data to transfer                                        */
            uint32_t            : 16;
    } bit;
  } CNDTR2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000024) DMA channel 2 peripheral address register                  */
    
    struct {
      __IOM uint32_t PA         : 32;           /*!< [31..0] Peripheral address                                                */
    } bit;
  } CPAR2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000028) DMA channel 2 memory address register                      */
    
    struct {
      __IOM uint32_t MA         : 32;           /*!< [31..0] Memory address                                                    */
    } bit;
  } CMAR2;
  __IM  uint32_t  RESERVED1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000030) DMA channel configuration register (DMA_CCR)               */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t HTIE       : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t TEIE       : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DIR        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t CIRC       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PINC       : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MINC       : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PSIZE      : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MSIZE      : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t MEM2MEM    : 1;            /*!< [14..14] Memory to memory mode                                            */
            uint32_t            : 17;
    } bit;
  } CCR3;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000034) DMA channel 3 number of data register                      */
    
    struct {
      __IOM uint32_t NDT        : 16;           /*!< [15..0] Number of data to transfer                                        */
            uint32_t            : 16;
    } bit;
  } CNDTR3;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000038) DMA channel 3 peripheral address register                  */
    
    struct {
      __IOM uint32_t PA         : 32;           /*!< [31..0] Peripheral address                                                */
    } bit;
  } CPAR3;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000003C) DMA channel 3 memory address register                      */
    
    struct {
      __IOM uint32_t MA         : 32;           /*!< [31..0] Memory address                                                    */
    } bit;
  } CMAR3;
  __IM  uint32_t  RESERVED2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000044) DMA channel configuration register (DMA_CCR)               */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t HTIE       : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t TEIE       : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DIR        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t CIRC       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PINC       : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MINC       : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PSIZE      : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MSIZE      : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t MEM2MEM    : 1;            /*!< [14..14] Memory to memory mode                                            */
            uint32_t            : 17;
    } bit;
  } CCR4;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000048) DMA channel 4 number of data register                      */
    
    struct {
      __IOM uint32_t NDT        : 16;           /*!< [15..0] Number of data to transfer                                        */
            uint32_t            : 16;
    } bit;
  } CNDTR4;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000004C) DMA channel 4 peripheral address register                  */
    
    struct {
      __IOM uint32_t PA         : 32;           /*!< [31..0] Peripheral address                                                */
    } bit;
  } CPAR4;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000050) DMA channel 4 memory address register                      */
    
    struct {
      __IOM uint32_t MA         : 32;           /*!< [31..0] Memory address                                                    */
    } bit;
  } CMAR4;
  __IM  uint32_t  RESERVED3;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000058) DMA channel configuration register (DMA_CCR)               */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t HTIE       : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t TEIE       : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DIR        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t CIRC       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PINC       : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MINC       : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PSIZE      : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MSIZE      : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t MEM2MEM    : 1;            /*!< [14..14] Memory to memory mode                                            */
            uint32_t            : 17;
    } bit;
  } CCR5;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000005C) DMA channel 5 number of data register                      */
    
    struct {
      __IOM uint32_t NDT        : 16;           /*!< [15..0] Number of data to transfer                                        */
            uint32_t            : 16;
    } bit;
  } CNDTR5;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000060) DMA channel 5 peripheral address register                  */
    
    struct {
      __IOM uint32_t PA         : 32;           /*!< [31..0] Peripheral address                                                */
    } bit;
  } CPAR5;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000064) DMA channel 5 memory address register                      */
    
    struct {
      __IOM uint32_t MA         : 32;           /*!< [31..0] Memory address                                                    */
    } bit;
  } CMAR5;
  __IM  uint32_t  RESERVED4;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000006C) DMA channel configuration register (DMA_CCR)               */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t HTIE       : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t TEIE       : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DIR        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t CIRC       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PINC       : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MINC       : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PSIZE      : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MSIZE      : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t MEM2MEM    : 1;            /*!< [14..14] Memory to memory mode                                            */
            uint32_t            : 17;
    } bit;
  } CCR6;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000070) DMA channel 6 number of data register                      */
    
    struct {
      __IOM uint32_t NDT        : 16;           /*!< [15..0] Number of data to transfer                                        */
            uint32_t            : 16;
    } bit;
  } CNDTR6;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000074) DMA channel 6 peripheral address register                  */
    
    struct {
      __IOM uint32_t PA         : 32;           /*!< [31..0] Peripheral address                                                */
    } bit;
  } CPAR6;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000078) DMA channel 6 memory address register                      */
    
    struct {
      __IOM uint32_t MA         : 32;           /*!< [31..0] Memory address                                                    */
    } bit;
  } CMAR6;
  __IM  uint32_t  RESERVED5;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000080) DMA channel configuration register (DMA_CCR)               */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Channel enable                                                     */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] Transfer complete interrupt enable                                 */
      __IOM uint32_t HTIE       : 1;            /*!< [2..2] Half Transfer interrupt enable                                     */
      __IOM uint32_t TEIE       : 1;            /*!< [3..3] Transfer error interrupt enable                                    */
      __IOM uint32_t DIR        : 1;            /*!< [4..4] Data transfer direction                                            */
      __IOM uint32_t CIRC       : 1;            /*!< [5..5] Circular mode                                                      */
      __IOM uint32_t PINC       : 1;            /*!< [6..6] Peripheral increment mode                                          */
      __IOM uint32_t MINC       : 1;            /*!< [7..7] Memory increment mode                                              */
      __IOM uint32_t PSIZE      : 2;            /*!< [9..8] Peripheral size                                                    */
      __IOM uint32_t MSIZE      : 2;            /*!< [11..10] Memory size                                                      */
      __IOM uint32_t PL         : 2;            /*!< [13..12] Channel Priority level                                           */
      __IOM uint32_t MEM2MEM    : 1;            /*!< [14..14] Memory to memory mode                                            */
            uint32_t            : 17;
    } bit;
  } CCR7;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000084) DMA channel 7 number of data register                      */
    
    struct {
      __IOM uint32_t NDT        : 16;           /*!< [15..0] Number of data to transfer                                        */
            uint32_t            : 16;
    } bit;
  } CNDTR7;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000088) DMA channel 7 peripheral address register                  */
    
    struct {
      __IOM uint32_t PA         : 32;           /*!< [31..0] Peripheral address                                                */
    } bit;
  } CPAR7;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000008C) DMA channel 7 memory address register                      */
    
    struct {
      __IOM uint32_t MA         : 32;           /*!< [31..0] Memory address                                                    */
    } bit;
  } CMAR7;
} DMA_Type;                                     /*!< Size = 144 (0x90)                                                         */



/* =========================================================================================================================== */
/* ================                                           eCAP                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief eCAP (eCAP)
  */

typedef struct {                                /*!< (@ 0x50002000) eCAP Structure                                             */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) control register 1                                         */
    
    struct {
      __IOM uint32_t CEN        : 1;            /*!< [0..0] Counter enable                                                     */
      __IOM uint32_t UDIS       : 1;            /*!< [1..1] Update disable                                                     */
      __IOM uint32_t URS        : 1;            /*!< [2..2] Update request source                                              */
      __IOM uint32_t OPM        : 1;            /*!< [3..3] One-pulse mode                                                     */
      __IOM uint32_t DIR        : 1;            /*!< [4..4] Direction                                                          */
      __IOM uint32_t CMS        : 2;            /*!< [6..5] Center-aligned mode selection                                      */
      __IOM uint32_t ARPE       : 1;            /*!< [7..7] Auto-reload preload enable                                         */
      __IOM uint32_t CKD        : 2;            /*!< [9..8] Clock division                                                     */
            uint32_t            : 22;
    } bit;
  } CR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) control register 2                                         */
    
    struct {
            uint32_t            : 3;
      __IOM uint32_t CCDS       : 1;            /*!< [3..3] Capture DMA selection                                              */
      __IOM uint32_t MMS        : 3;            /*!< [6..4] Master mode selection                                              */
      __IOM uint32_t TI1S       : 1;            /*!< [7..7] TI1 selection                                                      */
            uint32_t            : 24;
    } bit;
  } CR2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000008) slave mode control register                                */
    
    struct {
      __IOM uint32_t SMS        : 3;            /*!< [2..0] Slave mode selection                                               */
            uint32_t            : 1;
      __IOM uint32_t TS         : 3;            /*!< [6..4] Trigger selection                                                  */
      __IOM uint32_t MSM        : 1;            /*!< [7..7] Master/Slave mode                                                  */
      __IOM uint32_t ETF        : 4;            /*!< [11..8] External trigger filter                                           */
      __IOM uint32_t ETPS       : 2;            /*!< [13..12] External trigger prescaler                                       */
      __IOM uint32_t ECE        : 1;            /*!< [14..14] External clock enable                                            */
      __IOM uint32_t ETP        : 1;            /*!< [15..15] External trigger polarity                                        */
            uint32_t            : 16;
    } bit;
  } SMCR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) DMA/Interrupt enable register                              */
    
    struct {
      __IOM uint32_t UIE        : 1;            /*!< [0..0] Update interrupt enable                                            */
      __IOM uint32_t CC1IE      : 1;            /*!< [1..1] Capture 1 interrupt enable                                         */
      __IOM uint32_t CC2IE      : 1;            /*!< [2..2] Capture 2 interrupt enable                                         */
      __IOM uint32_t CC3IE      : 1;            /*!< [3..3] Capture 3 interrupt enable                                         */
      __IOM uint32_t CC4IE      : 1;            /*!< [4..4] Capture 4 interrupt enable                                         */
            uint32_t            : 1;
      __IOM uint32_t TIE        : 1;            /*!< [6..6] Trigger interrupt enable                                           */
            uint32_t            : 1;
      __IOM uint32_t UDE        : 1;            /*!< [8..8] Update DMA request enable                                          */
      __IOM uint32_t CC1DE      : 1;            /*!< [9..9] Capture 1 DMA request enable                                       */
      __IOM uint32_t CC2DE      : 1;            /*!< [10..10] Capture 2 DMA request enable                                     */
      __IOM uint32_t CC3DE      : 1;            /*!< [11..11] Capture 3 DMA request enable                                     */
      __IOM uint32_t CC4DE      : 1;            /*!< [12..12] Capture 4 DMA request enable                                     */
            uint32_t            : 1;
      __IOM uint32_t TDE        : 1;            /*!< [14..14] Trigger DMA request enable                                       */
            uint32_t            : 17;
    } bit;
  } DIER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000010) status register                                            */
    
    struct {
      __IOM uint32_t UIF        : 1;            /*!< [0..0] Update interrupt flag                                              */
      __IOM uint32_t CC1IF      : 1;            /*!< [1..1] Capture 1 interrupt flag                                           */
      __IOM uint32_t CC2IF      : 1;            /*!< [2..2] Capture 2 interrupt flag                                           */
      __IOM uint32_t CC3IF      : 1;            /*!< [3..3] Capture 3 interrupt flag                                           */
      __IOM uint32_t CC4IF      : 1;            /*!< [4..4] Capture 4 interrupt flag                                           */
            uint32_t            : 1;
      __IOM uint32_t TIF        : 1;            /*!< [6..6] Trigger interrupt flag                                             */
            uint32_t            : 2;
      __IOM uint32_t CC1OF      : 1;            /*!< [9..9] Capture 1 overcapture flag                                         */
      __IOM uint32_t CC2OF      : 1;            /*!< [10..10] Capture 2 overcapture flag                                       */
      __IOM uint32_t CC3OF      : 1;            /*!< [11..11] Capture 3 overcapture flag                                       */
      __IOM uint32_t CC4OF      : 1;            /*!< [12..12] Capture 4 overcapture flag                                       */
            uint32_t            : 19;
    } bit;
  } SR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000014) event generation register                                  */
    
    struct {
      __IOM uint32_t UG         : 1;            /*!< [0..0] Update generation                                                  */
      __IOM uint32_t CC1G       : 1;            /*!< [1..1] Capture 1 generation                                               */
      __IOM uint32_t CC2G       : 1;            /*!< [2..2] Capture 2 generation                                               */
      __IOM uint32_t CC3G       : 1;            /*!< [3..3] Capture 3 generation                                               */
      __IOM uint32_t CC4G       : 1;            /*!< [4..4] Capture 4 generation                                               */
            uint32_t            : 1;
      __IOM uint32_t TG         : 1;            /*!< [6..6] Trigger generation                                                 */
            uint32_t            : 25;
    } bit;
  } EGR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000018) capture/compare mode register 1 (input mode)               */
    
    struct {
      __IOM uint32_t CC1S       : 2;            /*!< [1..0] Capture 1 selection                                                */
      __IOM uint32_t IC1PSC     : 2;            /*!< [3..2] Input capture 1 prescaler                                          */
      __IOM uint32_t IC1F       : 4;            /*!< [7..4] Input capture 1 filter                                             */
      __IOM uint32_t CC2S       : 2;            /*!< [9..8] Capture 2 selection                                                */
      __IOM uint32_t IC2PSC     : 2;            /*!< [11..10] Input capture 2 prescaler                                        */
      __IOM uint32_t IC2F       : 4;            /*!< [15..12] Input capture 2 filter                                           */
            uint32_t            : 16;
    } bit;
  } CCMR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) capture/compare mode register 2 (input mode)               */
    
    struct {
      __IOM uint32_t CC3S       : 2;            /*!< [1..0] Capture 3 selection                                                */
      __IOM uint32_t IC3PSC     : 2;            /*!< [3..2] Input capture 3 prescaler                                          */
      __IOM uint32_t IC3F       : 4;            /*!< [7..4] Input capture 3 filter                                             */
      __IOM uint32_t CC4S       : 2;            /*!< [9..8] Capture 4 selection                                                */
      __IOM uint32_t IC4PSC     : 2;            /*!< [11..10] Input capture 4 prescaler                                        */
      __IOM uint32_t IC4F       : 4;            /*!< [15..12] Input capture 4 filter                                           */
            uint32_t            : 16;
    } bit;
  } CCMR2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000020) capture/compare enable register                            */
    
    struct {
      __IOM uint32_t CC1E       : 1;            /*!< [0..0] Capture 1 enable                                                   */
      __IOM uint32_t CC1P       : 1;            /*!< [1..1] Capture 1 Polarity                                                 */
            uint32_t            : 2;
      __IOM uint32_t CC2E       : 1;            /*!< [4..4] Capture 2 enable                                                   */
      __IOM uint32_t CC2P       : 1;            /*!< [5..5] Capture 2 Polarity                                                 */
            uint32_t            : 2;
      __IOM uint32_t CC3E       : 1;            /*!< [8..8] Capture 3 enable                                                   */
      __IOM uint32_t CC3P       : 1;            /*!< [9..9] Capture 3 Polarity                                                 */
            uint32_t            : 2;
      __IOM uint32_t CC4E       : 1;            /*!< [12..12] Capture 4 enable                                                 */
      __IOM uint32_t CC4P       : 1;            /*!< [13..13] Capture 3 Polarity                                               */
            uint32_t            : 18;
    } bit;
  } CCER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000024) counter                                                    */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] counter value                                                     */
            uint32_t            : 16;
    } bit;
  } CNT;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000028) prescaler                                                  */
    
    struct {
      __IOM uint32_t PSC        : 16;           /*!< [15..0] Prescaler value                                                   */
            uint32_t            : 16;
    } bit;
  } PSC;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000002C) auto-reload register                                       */
    
    struct {
      __IOM uint32_t ARR        : 16;           /*!< [15..0] Auto-reload value                                                 */
            uint32_t            : 16;
    } bit;
  } ARR;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000034) capture/compare register 1                                 */
    
    struct {
      __IOM uint32_t CCR1       : 16;           /*!< [15..0] Capture 1 value                                                   */
            uint32_t            : 16;
    } bit;
  } CCR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000038) capture/compare register 2                                 */
    
    struct {
      __IOM uint32_t CCR2       : 16;           /*!< [15..0] Capture 2 value                                                   */
            uint32_t            : 16;
    } bit;
  } CCR2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000003C) capture/compare register 3                                 */
    
    struct {
      __IOM uint32_t CCR3       : 16;           /*!< [15..0] Capture value                                                     */
            uint32_t            : 16;
    } bit;
  } CCR3;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000040) capture/compare register 4                                 */
    
    struct {
      __IOM uint32_t CCR4       : 16;           /*!< [15..0] Capture value                                                     */
            uint32_t            : 16;
    } bit;
  } CCR4;
} eCAP_Type;                                    /*!< Size = 68 (0x44)                                                          */



/* =========================================================================================================================== */
/* ================                                           TIM0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Basic Timer 0 (TIM0)
  */

typedef struct {                                /*!< (@ 0x40006000) TIM0 Structure                                             */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) Control the output of TRIG when overflows occur.           */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Counter enables.                                                   */
      __IOM uint32_t EXTEN      : 1;            /*!< [1..1] Control hardware trig counter counts.                              */
      __IOM uint32_t TRGEN      : 1;            /*!< [2..2] Control the output of TRIG when overflows occur.                   */
            uint32_t            : 29;
    } bit;
  } CR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) Count Value Register                                       */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] Count value.                                                      */
            uint32_t            : 16;
    } bit;
  } CNT;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000008) Interrupt Enable Register.                                 */
    
    struct {
      __IOM uint32_t OVE        : 1;            /*!< [0..0] Overflow interrupt enables the controller.                         */
            uint32_t            : 31;
    } bit;
  } IER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) State Register                                             */
    
    struct {
      __IOM uint32_t OVF        : 1;            /*!< [0..0] Overflow interrupt flag.                                           */
            uint32_t            : 31;
    } bit;
  } SR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000010) Clear Register                                             */
    
    struct {
      __IOM uint32_t OVCLR      : 1;            /*!< [0..0] Overflow interrupt clear                                           */
            uint32_t            : 31;
    } bit;
  } CLR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000014) Period Register                                            */
    
    struct {
      __IOM uint32_t PRD        : 16;           /*!< [15..0] Period register. Overflow when the count is equal to
                                                     PRD.                                                                      */
            uint32_t            : 16;
    } bit;
  } PRD;
} TIM_Type;                                     /*!< Size = 24 (0x18)                                                          */



/* =========================================================================================================================== */
/* ================                                           WWDG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Window Watch Dog (WWDG)
  */

typedef struct {                                /*!< (@ 0x40009000) WWDG Structure                                             */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) Control register                                           */
    
    struct {
      __IOM uint32_t T          : 7;            /*!< [6..0] 7-bit counter                                                      */
      __IOM uint32_t WDGA       : 1;            /*!< [7..7] Activation bit.                                                    */
            uint32_t            : 24;
    } bit;
  } CR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) Configuration register                                     */
    
    struct {
      __IOM uint32_t W          : 7;            /*!< [6..0] Window value                                                       */
      __IOM uint32_t WDGTB      : 2;            /*!< [8..7] prescaler                                                          */
      __IOM uint32_t EWI        : 1;            /*!< [9..9] Early wakeup interrupt                                             */
            uint32_t            : 22;
    } bit;
  } CFR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000008) Status register                                            */
    
    struct {
      __IOM uint32_t EWIF       : 1;            /*!< [0..0] Early wakeup interrupt flag                                        */
            uint32_t            : 31;
    } bit;
  } SR;
} WWDG_Type;                                    /*!< Size = 12 (0xc)                                                           */



/* =========================================================================================================================== */
/* ================                                           IWDG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Indipendent Watch Dog (IWDG)
  */

typedef struct {                                /*!< (@ 0x40018000) IWDG Structure                                             */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) Key register (IWDG_KR)                                     */
    
    struct {
      __IOM uint32_t KEY        : 16;           /*!< [15..0] Key value                                                         */
            uint32_t            : 16;
    } bit;
  } KR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) Prescaler register (IWDG_PR)                               */
    
    struct {
      __IOM uint32_t PR         : 3;            /*!< [2..0] Prescaler divider                                                  */
            uint32_t            : 29;
    } bit;
  } PR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000008) Reload register (IWDG_RLR)                                 */
    
    struct {
      __IOM uint32_t RL         : 12;           /*!< [11..0] Watchdog counter reload value                                     */
            uint32_t            : 20;
    } bit;
  } RLR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) Status register (IWDG_SR)                                  */
    
    struct {
      __IOM uint32_t PVU        : 1;            /*!< [0..0] Watchdog prescaler value update                                    */
      __IOM uint32_t RVU        : 1;            /*!< [1..1] Watchdog counter reload value update                               */
            uint32_t            : 30;
    } bit;
  } SR;
} IWDG_Type;                                    /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                            LIN                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief LIN (LIN)
  */

typedef struct {                                /*!< (@ 0x4000A000) LIN Structure                                              */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) The LINCR1 register consists of control bits
                                                                    used to configure features of the LINFlexD.
                                                                    When accessing the LINCR1 register, each
                                                                    reserved bit should be written with its
                                                                    original reset value.                                      */
    
    struct {
      __IOM uint32_t INIT       : 1;            /*!< [0..0] Set by software to switch the hardware into Initialization
                                                     mode. When software clears the INIT bit (and if the SLEEP
                                                     bit is also 0), the LINFlexD enters Normal mode. INIT is
                                                     effective in both LIN and UART modes.                                     */
      __IOM uint32_t SLEEP      : 1;            /*!< [1..1] Set by software to request LINFlexD to enter Sleep mode.
                                                     The SLEEP bit is cleared by software to exit sleep mode.
                                                     If LINCR1.AUTOWU and LINSR.WUF are set, SLEEP is automatically
                                                     cleared by hardware to exit sleep mode. SLEEP is effective
                                                     in both LIN and UART modes.                                               */
      __IOM uint32_t RBLM       : 1;            /*!< [2..2] Receive Buffer Locked Mode.                                        */
      __IOM uint32_t SSBL       : 1;            /*!< [3..3] Sets the number of bit times for break field detection
                                                     in slave mode.                                                            */
      __IOM uint32_t MME        : 1;            /*!< [4..4] Master Mode Enable.                                                */
      __IOM uint32_t LBKM       : 1;            /*!< [5..5] Enables or disables Loop Back mode as described in Loop
                                                     Back Mode.                                                                */
            uint32_t            : 1;
      __IOM uint32_t BF         : 1;            /*!< [7..7] Controls the receive filter bypass function.                       */
      __IOM uint32_t MBL        : 4;            /*!< [11..8] Controls the length of the break field generated in
                                                     LIN master mode.                                                          */
      __IOM uint32_t AUTOWU     : 1;            /*!< [12..12] Automatic Wake-Up Mode. This bit controls the behavior
                                                     of the LINFlex hardware during Sleep mode.                                */
      __IOM uint32_t LASE       : 1;            /*!< [13..13] Enables the autosynchronization, feature described
                                                     in Automatic Resynchronization.                                           */
      __IOM uint32_t CFD        : 1;            /*!< [14..14] Checksum field disable.This bit disables the checksum
                                                     field transmission.                                                       */
      __IOM uint32_t CCD        : 1;            /*!< [15..15] Checksum calculation disable.This bit disables the
                                                     checksum calculation.                                                     */
      __IOM uint32_t NLSE       : 1;            /*!< [16..16] NLSE enables/disables capture of the LIN state (LINSR.LINS)
                                                     whenever a bit error flag occurs (LINESR.BEF is set to
                                                     1).                                                                       */
            uint32_t            : 15;
    } bit;
  } LINCR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) LIN interrupt enable register                              */
    
    struct {
      __IOM uint32_t HRIE       : 1;            /*!< [0..0] Header Received Interrupt Enable                                   */
      __IOM uint32_t DTIE       : 1;            /*!< [1..1] Data Transmitted Interrupt Enable                                  */
      __IOM uint32_t DRIE       : 1;            /*!< [2..2] Data Reception Complete Interrupt Enable                           */
      __IOM uint32_t TOIE       : 1;            /*!< [3..3] Timout Interrupt Enable                                            */
            uint32_t            : 1;
      __IOM uint32_t WUIE       : 1;            /*!< [5..5] Wake-up Interrupt Enable                                           */
      __IOM uint32_t LSIE       : 1;            /*!< [6..6] LIN State Interrupt Enable                                         */
      __IOM uint32_t BOIE       : 1;            /*!< [7..7] Buffer Overrun Interrupt Enable                                    */
      __IOM uint32_t FEIE       : 1;            /*!< [8..8] Framing Error Interrupt Enable                                     */
            uint32_t            : 2;
      __IOM uint32_t HEIE       : 1;            /*!< [11..11] Header Error Interrupt Enable                                    */
      __IOM uint32_t CEIE       : 1;            /*!< [12..12] Checksum Error Interrupt Enable                                  */
      __IOM uint32_t BEIE       : 1;            /*!< [13..13] Bit Error Interrupt Enable                                       */
      __IOM uint32_t OCIE       : 1;            /*!< [14..14] Output Compare Interrupt Enable                                  */
      __IOM uint32_t SZIE       : 1;            /*!< [15..15] Stuck at Zero Interrupt Enable                                   */
            uint32_t            : 16;
    } bit;
  } LINIER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000008) The LINSR register contains status bits indicating
                                                                    the state of the LINFlexD hardware. Reset
                                                                    value of RDI reflects the LINFlexD_RX pin
                                                                    state.                                                     */
    
    struct {
      __IOM uint32_t HRF        : 1;            /*!< [0..0] HRF is set by hardware when header reception completes
                                                     and one of the following conditions is true. All filters
                                                     are inactive and LINCR1.BF = 1. No match in any filter
                                                     and LINCR1.BF = 1. Tx filter match. HRF is reset by hardware
                                                     in Initialization mode and at end of completed or aborted
                                                     frame.                                                                    */
      __IOM uint32_t DTF        : 1;            /*!< [1..1] DTF is set by hardware and indicates that data transmission
                                                     has completed. DTF is cleared by hardware in Initialization
                                                     mode. DTF is not set in LIN mode when a bit error occurs
                                                     and LINCR2.IOBE = 0.                                                      */
      __IOM uint32_t DRF        : 1;            /*!< [2..2] DRF is set by hardware and indicates that data reception
                                                     has completed. DRF is cleared by hardware in Initialization
                                                     mode. DRF is not set when a framing error or checksum error
                                                     occurs.                                                                   */
            uint32_t            : 2;
      __IOM uint32_t WUF        : 1;            /*!< [5..5] WUF is set by hardware when a falling edge is detected
                                                     on the LINFlexD_RX pin in either of the following conditions:
                                                     The LINFlexD is in slave mode and in Sleep mode. The LINFlexD
                                                     is in master mode is in either Sleep mode or Idle state.
                                                     WUF is cleared by hardware in Initialization mode.                        */
      __IM  uint32_t RDI        : 1;            /*!< [6..6] Receive Data Input                                                 */
      __IM  uint32_t RXBUSY     : 1;            /*!< [7..7] Receiver Busy Flag                                                 */
      __IOM uint32_t DRBNE      : 1;            /*!< [8..8] DRBNE is set by hardware as soon as the first byte of
                                                     response is received and stored in DATA (when there is
                                                     at least one data byte in reception buffer). Software should
                                                     clear DRBNE after reading all the buffers. DRBNE can be
                                                     checked by software in the case of a response timeout event.
                                                     DRBNE is cleared by hardware in Initialization mode.                      */
      __IOM uint32_t RMB        : 1;            /*!< [9..9] Release Message Buffer                                             */
            uint32_t            : 2;
      __IM  uint32_t LINS       : 4;            /*!< [15..12] LIN modes / normal mode states                                   */
      __IM  uint32_t RDC        : 3;            /*!< [18..16] RDC contains the number of entries (bytes) in the receive
                                                     data buffer in LIN mode.                                                  */
      __IOM uint32_t AUTOSYNC_COMP : 1;         /*!< [19..19] AUTOSYNC_COMP is set when autosynchronization is enabled
                                                     (LINCR1.LASE is set) and autosynchronization is complete.
                                                     After AUTOSYNC_COMP is set, the contents of LINIBRR and
                                                     LINFBRR registers can be read.                                            */
            uint32_t            : 12;
    } bit;
  } LINSR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) The LINESR register contains status bits for
                                                                    various error conditions. For detailed descriptions
                                                                    the error conditions.                                      */
    
    struct {
      __IOM uint32_t NF         : 1;            /*!< [0..0] NF is set by hardware when noise is detected in a receive
                                                     character. NF is cleared by hardware in Initialization
                                                     mode.                                                                     */
            uint32_t            : 6;
      __IOM uint32_t BOF        : 1;            /*!< [7..7] BOF is set by hardware when a new byte is received and
                                                     LINSR.RMB bit is not cleared. BOF is cleared by hardware
                                                     in Initialization mode.                                                   */
      __IOM uint32_t FEF        : 1;            /*!< [8..8] FEF is set by hardware when a framing error (invalid
                                                     stop bit) occurs. FEF is cleared by hardware in Initialization
                                                     mode.                                                                     */
      __IOM uint32_t IDPEF      : 1;            /*!< [9..9] IDPEF is set by hardware LINFlexD detects an error in
                                                     the ID parity. IDPEF is cleared by hardware in Initialization
                                                     mode.                                                                     */
      __IOM uint32_t SDEF       : 1;            /*!< [10..10] SDEF is set by hardware when a break delimiter error
                                                     occurs because a break delimiter is too short (less than
                                                     one bit time). SDEF is cleared by hardware in Initialization
                                                     mode.                                                                     */
      __IOM uint32_t SFEF       : 1;            /*!< [11..11] SFEF is set by hardware when a sync field error occurs
                                                     due to an inconsistent sync field. SFEF is cleared by hardware
                                                     in Initialization mode.                                                   */
      __IOM uint32_t CEF        : 1;            /*!< [12..12] CEF is set by hardware when the received checksum does
                                                     not match the hardware calculated checksum. CEF is cleared
                                                     by hardware in Initialization mode. CEF is never set if
                                                     LINCR1.CCD or LINCR1.CFD is set.                                          */
      __IOM uint32_t BEF        : 1;            /*!< [13..13] BEF is set by hardware when the LINFlexD detects a
                                                     bit error. BEF is cleared by hardware in Initialization
                                                     mode.                                                                     */
      __IOM uint32_t OCF        : 1;            /*!< [14..14] In master mode, OCF is set when counter LINTCSR.CNT
                                                     matches the content of LINOCR.OC2. In slave mode, OCF is
                                                     set when the content of the counter LINTCSR.CNT matches
                                                     the content of LINOCR.OC1 or LINOCR.OC2. If OCF is set
                                                     when LINTCSR.MODE = 0 and LINTCSR.IOT = 1, the LINFlexD
                                                     goes to Idle state. When LINTCSR.MODE = 0, OCF is cleared
                                                     by hardware in Initialization mode. When LINTCSR.MODE =
                                                     1, OCF maintains its status regardless of the LIN state.                  */
      __IOM uint32_t SZF        : 1;            /*!< [15..15] Set by hardware when a stuck-at-zero timeout error
                                                     occurs.                                                                   */
            uint32_t            : 16;
    } bit;
  } LINESR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000010) The UARTCR register contains control bits for
                                                                    UART mode. Always write 0 to reserved bits
                                                                    when writing to UARTCR. In UART mode, the
                                                                    LINFlexD does not support communication
                                                                    with Special Word Length (UARTCR.WLS = 1)
                                                                    in buffer mode. In UART mode, the LINFlexD
                                                                    supports communication with Special Word
                                                                    Length (UARTCR.WLS = 1) in FIFO mode only
                                                                    with UARTCR.WL[1:0] = 11.                                  */
    
    struct {
      __IOM uint32_t UART       : 1;            /*!< [0..0] UART Mode Enable                                                   */
      __IOM uint32_t WL0        : 1;            /*!< [1..1] Word Length in UART Mode.
                                                     7bits data + parity, when WL1 = 0, WL0 = 0;
                                                     8bits data, when WL1 = 0, WL0 = 1, PCE = 0;
                                                     8bits data + parity, when WL1 = 0, WL0 = 1, PCE = 1;
                                                     15bits data + parity, when WL1 = 1, WL0 = 0;
                                                     16bits data, when WL1 = 1, WL0 = 1, PCE = 0;
                                                     16bits data + parity, when WL1 = 1, WL0 = 1, PCE = 1;                     */
      __IOM uint32_t PCE        : 1;            /*!< [2..2] Parity Control Enable                                              */
      __IOM uint32_t PC0        : 1;            /*!< [3..3] Parity Control;
                                                     even, when PC1 = 0, PC0 = 0;
                                                     odd, when PC1 = 0, PC0 = 1;
                                                     logic0, when PC1 = 1, PC0 = 0;
                                                     logic1, when PC1 = 1, PC0 = 1;                                            */
      __IOM uint32_t TXEN       : 1;            /*!< [4..4] Transmitter Enable                                                 */
      __IOM uint32_t RXEN       : 1;            /*!< [5..5] Receive Enable                                                     */
      __IOM uint32_t PC1        : 1;            /*!< [6..6] Parity Control                                                     */
      __IOM uint32_t WL1        : 1;            /*!< [7..7] Word Length in UART Mode                                           */
      __IOM uint32_t TFBM       : 1;            /*!< [8..8] Tx FIFO/Buffer Mode                                                */
      __IOM uint32_t RFBM       : 1;            /*!< [9..9] Rx FIFO/Buffer Mode                                                */
      __IOM uint32_t RDFL_RFC   : 3;            /*!< [12..10] The RDFL_RFC field has one of two functions depending
                                                     on the mode of operation. UART Buffer Mode: When the LINFlexD
                                                     is in UART buffer mode (RFBM = 0), RDFL_RFC is read/write
                                                     and defines the number of bytes to be received: x00: 1
                                                     byte x01: 2 bytes x10: 3 bytes x11: 4 bytes The first bit
                                                     is reserved and not implemented. When the UART data length
                                                     is configured as half-word (WL = 10 or 11), the only valid
                                                     values for RDFL_RFC are x01 and x11. RDFL_RFC should be
                                                     programmed to be greater than or equal to NEF (num                        */
      __IOM uint32_t TDFL_TFC   : 3;            /*!< [15..13] The TDFL_TFC field has one of two functions depending
                                                     on the mode of operation. UART Buffer Mode: When the LINFlexD
                                                     is in UART buffer mode (TFBM = 0), TDFL_TFC is read/write
                                                     and defines the number of bytes to be transmitted. x00:
                                                     1 byte x01: 2 bytes x10: 3 bytes x11: 4 bytes The first
                                                     bit is reserved and not implemented. When the UART data
                                                     length is configured as half-word (WL = 10 or 11), the
                                                     only valid values for TDFL_TFC are x01 and x11. UART FIFO
                                                     Mode: When the LINFlexD is in UART FIFO mode (TFBM = 1),                  */
      __IOM uint32_t WLS        : 1;            /*!< [16..16] Special Word Length in UART Mode.                                */
      __IOM uint32_t SBUR       : 2;            /*!< [18..17] Number of Stop Bits in UART Reception Mode                       */
      __IOM uint32_t DTU        : 1;            /*!< [19..19] Disable Timeout in UART mode                                     */
      __IOM uint32_t NEF        : 3;            /*!< [22..20] The NEF bits set the number of expected frames in UART
                                                     reception mode. If the DTU bit is set, then the UART timeout
                                                     counter is reset after the configured number of frames
                                                     have been received. NEF can be read in any mode, but can
                                                     be written only during Initialization mode.                               */
      __IOM uint32_t ROSE       : 1;            /*!< [23..23] Reduced Oversampling Enable.                                     */
      __IOM uint32_t OSR        : 4;            /*!< [27..24] Selects the number of samples taken for a bit when
                                                     reduced oversampling is enabled. The values allowed for
                                                     OSR are 4, 5, 6, and 8. When idle state monitoring is enabled
                                                     (MIS = 1), the allowed OSR values are 4 and 8. OSR can
                                                     be read in any mode, but can be written only during Initialization
                                                     mode.                                                                     */
      __IOM uint32_t CSP        : 3;            /*!< [30..28] The CSP bits select the sample point during reduced
                                                     oversampling. CSP can have the following range of values
                                                     for the specified oversampling rate:                                      */
      __IOM uint32_t MIS        : 1;            /*!< [31..31] Monitor Idle State                                               */
    } bit;
  } UARTCR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000014) The UARTSR register contains status bits for
                                                                    UART mode.                                                 */
    
    struct {
      __IOM uint32_t NF         : 1;            /*!< [0..0] Set by hardware when noise is detected in the received
                                                     character. NF reflects the same value as LINESR.NF when
                                                     the LINFlexD is not in Initialization mode and the UARTCR.UART
                                                     = 1. During reduced oversampling (UARTCR.ROSE = 1), the
                                                     NF bit is enabled only when UARTCR.OSR = 8.                               */
      __IOM uint32_t DTF_TFF    : 1;            /*!< [1..1] The DTF_TFF bit function depends on whether the LINFlexD
                                                     is operating in UART buffer mode or UART FIFO mode. UART
                                                     Buffer Mode: In UART buffer mode (RFBM = 0), the DTF (data
                                                     transmitted flag) function of DTF_TFF is used. DTF is set
                                                     by hardware in UART buffer mode when data transmission
                                                     completes. An interrupt is generated if LINIER.DTIE = 1.
                                                     DTF reflects the same value as LINSR.DTF when the LINFlexD
                                                     is not in Initialization mode and UARTCR.UART = 1. DTF
                                                     can be read/cleared by software. Writing 1 clears DTF.                    */
      __IOM uint32_t DRF_RFE    : 1;            /*!< [2..2] The DRF_RFE bit function depends on whether the LINFlexD
                                                     is operating in UART buffer mode or UART FIFO mode. UART
                                                     Buffer Mode: In UART buffer mode (RFBM = 0), the DRF (data
                                                     received flag) function of DRF_RFE is used. DRF is set
                                                     by hardware in UART buffer mode when the number of bytes
                                                     programmed in UARTCR.RDFL are received. An interrupt is
                                                     generated if LINIER.DRIE = 1. DRF is set when the configured
                                                     number of valid stop bits are received for the last frame.
                                                     DRF is set regardless of parity error, overrun err                        */
      __IOM uint32_t TO         : 1;            /*!< [3..3] TO is set by hardware when a UART timeout occurs - in
                                                     other words, the value of UARTCTO becomes equal to the
                                                     preset value of the timeout . An interrupt is generated
                                                     if LINIER.TOIE equals to 1. The GCR.SR bit should be used
                                                     to reset the receiver FSM to the Idle state in the event
                                                     of timeout for UART reception in both UART buffer and UART
                                                     FIFO modes.                                                               */
      __IM  uint32_t RFNE       : 1;            /*!< [4..4] RFNE is set by hardware in UART FIFO mode (RFBM = 1),
                                                     when there is at least one data byte present in the receive
                                                     FIFO. RFNE is a read-only bit for debugging purposes. RFNE
                                                     can be used by software in case of a timeout event.                       */
      __IOM uint32_t WUF        : 1;            /*!< [5..5] WUF is set by hardware when a falling edge is detected
                                                     on the LINFlexD_RX pin in Sleep mode. An interrupt is generated
                                                     if LINIER.WUIE = 1. WUF reflects the same value as LINSR.WUF
                                                     when the LINFlexD is not in Initialization mode and UARTCR.UART
                                                     = 1.                                                                      */
      __IM  uint32_t RDI        : 1;            /*!< [6..6] Reflects the current state of the LINFlexD_RX pin when
                                                     UARTCR.UART = 1                                                           */
      __IOM uint32_t BOF        : 1;            /*!< [7..7] In UART buffer mode, BOF is set by hardware when there
                                                     is a new byte received and the RMB bit is not cleared.
                                                     If LINCR.RBLM = 1, the newly received message is discarded.
                                                     If LINCR.RBLM = 0, the newly received message overwrites
                                                     the buffer. In UART FIFO mode, BOF is set when there is
                                                     a new byte received and the Rx FIFO is full. In UART FIFO
                                                     mode, once Rx FIFO is full, the new received message is
                                                     discarded regardless of the value of the RBLM bit. When
                                                     BOF is set, an interrupt is generated if LINIER.BOIE =
                                                     1.                                                                        */
      __IOM uint32_t FEF        : 1;            /*!< [8..8] FEF is set by hardware when the LINFlexD detects a framing
                                                     error (invalid stop bit). An interrupt is generated if
                                                     LINIER.FEIE = 1. FEF reflects the same value as LINESR.FEF
                                                     when the LINFlexD is not in Initialization mode and UARTCR.UART
                                                     = 1.                                                                      */
      __IOM uint32_t RMB        : 1;            /*!< [9..9] Release Message Buffer                                             */
      __IOM uint32_t PE         : 4;            /*!< [13..10] Indicates parity error in corresponding receive data
                                                     byte.                                                                     */
      __IOM uint32_t OCF        : 1;            /*!< [14..14] OCF Output Compare Flag                                          */
      __IOM uint32_t SZF        : 1;            /*!< [15..15] SZF is set by hardware when 100 dominant bits are detected.
                                                     An interrupt is generated if LINIER.SZIE = 1. SZF reflects
                                                     the same value as LINESR.SZF when the LINFlexD is not in
                                                     Initialization mode and UARTCR.UART = 1.                                  */
            uint32_t            : 16;
    } bit;
  } UARTSR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000018) The LINTCSR register contains control and status
                                                                    bits for the LIN timeout feature. When LINTCSR.MODE
                                                                    = 0, any activity on the transmit or receive
                                                                    pins will cause an unwanted change in the
                                                                    value of the 8-bit field Output Compare
                                                                    Value 2 (OC2) of the LIN Output Compare
                                                                    register (LINOCR). If the LINFlexD is enabled
                                                                    in LIN mode and the value of LINTCSR.MODE
                                                                    is changed from 1 to 0, the old values of
                                                                    LINOCR.OC1 and LINOCR.OC2 are retained.
                                                                    As a consequence, if the LINFlexD is reconfigured
                                                                    from UAR                                                   */
    
    struct {
      __IM  uint32_t CNT        : 8;            /*!< [7..0] The value of the timeout counter. For proper functionality
                                                     of this counter, LINIBRR should be greater than or equal
                                                     to 5.                                                                     */
      __IOM uint32_t TOCE       : 1;            /*!< [8..8] Timeout Conuter Enable                                             */
      __IOM uint32_t IOT        : 1;            /*!< [9..9] Idle on Timeout                                                    */
      __IOM uint32_t MODE       : 1;            /*!< [10..10] LIN timeout mode                                                 */
            uint32_t            : 21;
    } bit;
  } LINTCSR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) The LINOCR register contains the value to be
                                                                    compared to the LINTCSR.CNT value. LINOCR
                                                                    is writable by software only in when the
                                                                    counter is in output compare mode.                         */
    
    struct {
      __IOM uint32_t OC1        : 8;            /*!< [7..0] Output compare value 1.                                            */
      __IOM uint32_t OC2        : 8;            /*!< [15..8] Output compare value 2.                                           */
            uint32_t            : 16;
    } bit;
  } LINOCR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000020) The LINTOCR register contains the LIN mode response
                                                                    and header timeout values.                                 */
    
    struct {
      __IOM uint32_t HTO        : 7;            /*!< [6..0] HTO specifies the header timeout duration (in bit time).
                                                     HTO can be written only for slave mode. The header timeout
                                                     should be programmed without considering 11 bits of break
                                                     field.                                                                    */
            uint32_t            : 1;
      __IOM uint32_t RTO        : 4;            /*!< [11..8] Response Timeout Value - The response timeout duration(in
                                                     bit time for 1 byte).                                                     */
            uint32_t            : 20;
    } bit;
  } LINTOCR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000024) LINFBRR sets the fractional part of the LIN baud
                                                                    rate. When LINCR1.LASE = 1, LINFBRR should
                                                                    be read only after LINSR.AUTOSYNC_COMP is
                                                                    set to obtain the correct value. LINFBRR
                                                                    cannot be used when reduced oversampling
                                                                    is enabled (UARTCR.ROSE = 1).                              */
    
    struct {
      __IOM uint32_t FBR        : 4;            /*!< [3..0] Fractional Baud Rate.                                              */
            uint32_t            : 28;
    } bit;
  } LINFBRR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000028) LINIBRR sets the integer part of the LIN baud
                                                                    rate. When LINCR1.LASE = 1, LINIBRR should
                                                                    be read only after LINSR.AUTOSYNC_COMP is
                                                                    set to obtain the correct value.                           */
    
    struct {
      __IOM uint32_t IBR        : 20;           /*!< [19..0] The IBR bits, along with the fractional baud rate bits
                                                     in LINFBRR, set the LIN baud rate. IBR = 0x0: LIN clock
                                                     disabled IBR = 0x1: Mantissa(LDIV) = 1 ... IBR = 0xFFFFE:
                                                     Mantissa(LDIV) = 1048574 IBR = 0xFFFFF: Mantissa(LDIV)
                                                     = 1048575 IBR can be read in any mode, but can be written
                                                     only during Initialization mode.                                          */
            uint32_t            : 12;
    } bit;
  } LINIBRR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000002C) There is a delay between 4 to 6 clock cycles
                                                                    of bus clock for the internal checksums
                                                                    value (which is clocked with ipg_baud_clk/16
                                                                    * LDIV) to reflect on LINCFR. Due to synchronization
                                                                    structures between the two input clocks
                                                                    to the LINFlexD, the write to this register
                                                                    is delayed between 2 to 3 clock cycles of
                                                                    bus clock.                                                 */
    
    struct {
      __IOM uint32_t CF         : 8;            /*!< [7..0] When LINCR1.CCD = 0, the CF bits are read-only and are
                                                     calculated by hardware. When LINCR1.CCD = 1, the CF bits
                                                     can be written by software.                                               */
            uint32_t            : 24;
    } bit;
  } LINCFR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000030) The LINCR2 register contains control and status
                                                                    bits related to buffer operations. When
                                                                    accessing LINCR2, each reserved bit should
                                                                    be written with its original reset value.                  */
    
    struct {
            uint32_t            : 8;
      __IOM uint32_t HTRQ       : 1;            /*!< [8..8] HTRQ is set by software to request the transmission of
                                                     a LIN header. HTRQ is cleared by hardware when the request
                                                     has been completed or on abort request. HTRQ has no effect
                                                     in UART mode. In master mode, if both HTRQ and ABRQ are
                                                     set at the same time then ABRQ has no effect. Similarly,
                                                     in slave mode after header reception, if DTRQ and ABRQ
                                                     are simultaneously set then ABRQ has no effect.                           */
      __IOM uint32_t ABRQ       : 1;            /*!< [9..9] ABRQ is set by software to abort the current transmission.
                                                     The LINFlexD aborts the transmission at the end of the
                                                     current bit. ABRQ is cleared by hardware when the transmission
                                                     has been aborted. ABRQ can abort a wakeup request and can
                                                     also be used in UART mode.                                                */
      __IOM uint32_t DTRQ       : 1;            /*!< [10..10] DTRQ is set by software in slave mode to request the
                                                     transmission of the LIN data field stored in the buffer
                                                     data register. DTRQ can be set only when LINSR.HRF = 1
                                                     (to ensure that data transmission is requested only after
                                                     a header reception). DTRQ is cleared by hardware when the
                                                     request has been completed, or on abort request or error
                                                     condition. In master mode, DTRQ is set by hardware when
                                                     BIDR.DIR = 1 and header transmission is complete.                         */
      __IOM uint32_t DDRQ       : 1;            /*!< [11..11] DDRQ is set by software to stop data reception if the
                                                     frame does not concern the node. DDRQ is reset by hardware
                                                     once the LINFlexD ignores the response and moves to Idle
                                                     state. For a LIN slave, DDRQ can be set only when LINSR.HRF
                                                     = 1 and the identifier is software-filtered.                              */
      __IOM uint32_t WURQ       : 1;            /*!< [12..12] Setting WURQ generates a wakeup request. The character
                                                     sent during wakeup is copied from DATA0. WURQ is reset
                                                     by hardware when the wakeup character has been transmitted.
                                                     WURQ cannot be set in Sleep mode. Software must exit Sleep
                                                     mode before setting WURQ. Bit error is not checked when
                                                     transmitting the wakeup request.                                          */
      __IOM uint32_t IOPE       : 1;            /*!< [13..13] Idle on Identifier Parity Error                                  */
      __IOM uint32_t IOBE       : 1;            /*!< [14..14] Idle on Bit Error                                                */
      __IOM uint32_t TBDE       : 1;            /*!< [15..15] Two-Bit Delimiter Enable.                                        */
            uint32_t            : 16;
    } bit;
  } LINCR2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000034) The BIDR register contains bits that provide
                                                                    information about the identifier of the
                                                                    transaction and other related information.
                                                                    All the fields (ID, CSS, DIR, DFL) of the
                                                                    BIDR register must be updated when an ID
                                                                    filter (enabled) in Slave mode (Tx or Rx)
                                                                    matches the ID received.                                   */
    
    struct {
      __IOM uint32_t ID         : 6;            /*!< [5..0] Identifier part of the identifier field without the identifier
                                                     parity. The ID field can be written only in master mode
                                                     (LINCR1.MME = 1).                                                         */
            uint32_t            : 2;
      __IOM uint32_t CCS        : 1;            /*!< [8..8] Controls the type of checksum applied on the current
                                                     message.                                                                  */
      __IOM uint32_t DIR        : 1;            /*!< [9..9] Controls the direction of the data field.                          */
      __IOM uint32_t DFL        : 3;            /*!< [12..10] Number of data bytes in the response part of the frame.
                                                     DFL = Number of data bytes - 1.                                           */
            uint32_t            : 3;
      __IOM uint32_t CCS_A      : 1;            /*!< [16..16] Controls the type of checksum applied on the current
                                                     message.                                                                  */
            uint32_t            : 15;
    } bit;
  } BIDR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000038) Bytes 0-3 of the 8 byte data buffer.                       */
    
    struct {
      __IOM uint32_t DATA0      : 8;            /*!< [7..0] data0.                                                             */
      __IOM uint32_t DATA1      : 8;            /*!< [15..8] data1.                                                            */
      __IOM uint32_t DATA2      : 8;            /*!< [23..16] data2.                                                           */
      __IOM uint32_t DATA3      : 8;            /*!< [31..24] data3.                                                           */
    } bit;
  } BDRL;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000003C) Bytes 4-7 of the 8 byte data buffer.                       */
    
    struct {
      __IOM uint32_t DATA4      : 8;            /*!< [7..0] data4.                                                             */
      __IOM uint32_t DATA5      : 8;            /*!< [15..8] data5.                                                            */
      __IOM uint32_t DATA6      : 8;            /*!< [23..16] data6.                                                           */
      __IOM uint32_t DATA7      : 8;            /*!< [31..24] data7.                                                           */
    } bit;
  } BDRM;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000040) The IFER register enables/disables the identifier
                                                                    filters. There is one filter active (FACT)
                                                                    bit for each filter.                                       */
    
    struct {
      __IOM uint32_t FACT       : 16;           /*!< [15..0] One bit for each identifier filter. Software sets FACT[n]
                                                     to activate the filter n in identifier list mode. In identifier
                                                     mask mode, FACT[2n+1] have no effect on the corresponding
                                                     filters as they act as mask for identifier 2n. FACT[n]
                                                     can be read in any mode, but can be written only during
                                                     Initialization mode.                                                      */
            uint32_t            : 16;
    } bit;
  } IFER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000044) The IFMI register contains the index corresponding
                                                                    to the received identifier. It can be used
                                                                    to read or write the data directly in RAM.                 */
    
    struct {
      __IM  uint32_t IFMI       : 5;            /*!< [4..0] Contains the index corresponding to the received identifier.
                                                     Upon a filter match with filter x, IFMI[N:0] = x+1. On
                                                     no match, IFMI is equal to 0x00. IFMI can be used to directly
                                                     write or read the data in RAM.                                            */
            uint32_t            : 27;
    } bit;
  } IFMI;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000048) The IFMR register configures the modes of filters.
                                                                    There is one IFM bit for each pair of filters.             */
    
    struct {
      __IOM uint32_t IFM        : 8;            /*!< [7..0] 0: Filters 2n and 2n+1 are in identifier list mode. 1:
                                                     Filters 2n and 2n+1 are in mask mode. Filter 2n+1 is the
                                                     mask for filter 2n. IFM[n] can be read in any mode, but
                                                     can be written only during Initialization mode.                           */
            uint32_t            : 24;
    } bit;
  } IFMR;
  
  union {
    __IOM uint32_t reg[16];                     /*!< (@ 0x0000004C) There is an Identifier Filter Control Register
                                                                    (IFCRn) for each filter. The IFCRn registers
                                                                    are read-only in Normal mode and can be
                                                                    written only in Initialization mode.                       */
    
    struct {
      __IOM uint32_t ID         : 6;            /*!< [5..0] Identifier part of the identifier field without the identifier
                                                     parity.                                                                   */
            uint32_t            : 2;
      __IOM uint32_t CCS        : 1;            /*!< [8..8] Controls the type of checksum applied on the current
                                                     message.                                                                  */
      __IOM uint32_t DIR        : 1;            /*!< [9..9] Controls the direction of the data field.                          */
      __IOM uint32_t DFL        : 3;            /*!< [12..10] Number of data bytes in the response part of the frame.
                                                     DFL = Number of data bytes - 1.                                           */
            uint32_t            : 19;
    } bit[16];
  } IFCR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000008C) The GCR register contains control bits that apply
                                                                    to both LIN and UART modes. The GCR register
                                                                    is read-only in Normal mode and can be written
                                                                    only in Initialization mode.                               */
    
    struct {
      __IOM uint32_t SR         : 1;            /*!< [0..0] Writing 1 to SR executes a soft reset of the LINFlexD
                                                     (FSMs, FIFO pointers, counters, timers, status and error
                                                     registers) without modifying the configuration registers.
                                                     SR should be cleared by software to perform further operations
                                                     (SR is not cleared by hardware). The SR bit can be written
                                                     only be software in Initialization mode. The read value
                                                     of SR is always 0. When writing 1 to SR, below register
                                                     fields are reset:                                                         */
      __IOM uint32_t STOP       : 1;            /*!< [1..1] Controls the number of stop bits transmitted for all
                                                     fields (delimiter, sync, ID, checksum, payload).                          */
      __IOM uint32_t RDLIS      : 1;            /*!< [2..2] Controls the data inversion of received data (payload
                                                     only).                                                                    */
      __IOM uint32_t TDLIS      : 1;            /*!< [3..3] Controls the data inversion of transmitted data (payload
                                                     only).                                                                    */
      __IOM uint32_t RDFBM      : 1;            /*!< [4..4] Controls whether the first bit of received data (payload
                                                     only) is mapped to the most or least significant bit from
                                                     the respective buffer data register.                                      */
      __IOM uint32_t TDFBM      : 1;            /*!< [5..5] Controls whether the first bit of transmit data (payload
                                                     only) is the most or least significant bit from the respective
                                                     buffer data register.                                                     */
            uint32_t            : 26;
    } bit;
  } GCR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000090) The UARTPTO register contains the preset value
                                                                    of the timeout register in UART mode and
                                                                    is programmed according to the number of
                                                                    bits to be received or to monitor the idle
                                                                    state of the reception line. The UARTPTO
                                                                    register can be written by software at any
                                                                    time.                                                      */
    
    struct {
      __IOM uint32_t PTO        : 12;           /*!< [11..0] PTO defines the preset value of timeout counter. A zero
                                                     value is forbidden; otherwise, the UARTSR[TO] status bit
                                                     is immediately set.                                                       */
            uint32_t            : 20;
    } bit;
  } UARTPTO;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000094) The UARTCTO register contains the current timeout
                                                                    value in UART mode. UARTCTO is used with
                                                                    the UARTPTO register to monitor the number
                                                                    of bits received by UART or to monitor the
                                                                    idle state of the reception line. UART timeout
                                                                    works in both CPU and DMA modes. The timeout
                                                                    counter: Starts at zero and counts upward.
                                                                    Is clocked with ipg_baud_clk / (16 * LDIV)
                                                                    synchronized to bus clock (when UARTCR.ROSE
                                                                    = 0). Is clocked with ipg_baud_clk / (UARTCR.OSR
                                                                    * LINIBRR.IBR) synchronized to bus clock
                                                                    (when U                                                    */
    
    struct {
      __IM  uint32_t CTO        : 12;           /*!< [11..0] CTO defines the current value of the timeout counter.
                                                     CTO is a read-only field. CTO is reset every time UARTPTO
                                                     is written, or UARTCTO = UARTPTO, or by hard/soft reset.
                                                     When the CTO value matches the preset value (UARTPTO.PTO),
                                                     the status bit UARTSR.TO is set.                                          */
            uint32_t            : 20;
    } bit;
  } UARTCTO;
  __IM  uint32_t  RESERVED[26];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000100) LINOUT Register                                            */
    
    struct {
      __IOM uint32_t TXEN       : 1;            /*!< [0..0] Enable LIN Tx.                                                     */
      __IOM uint32_t RXEN       : 1;            /*!< [1..1] Enable LIN rx.                                                     */
      __IOM uint32_t TXPU_1K    : 1;            /*!< [2..2] TX 1K pull-up enable.                                              */
      __IOM uint32_t TXPU_30K   : 1;            /*!< [3..3] TX 30K pull-up enable.                                             */
      __IOM uint32_t SLOPE_ENHANCE : 1;         /*!< [4..4] lin slope enhance.                                                 */
      __IOM uint32_t SLOPE_SEL  : 4;            /*!< [8..5] TX recessive to dominant slope control.                            */
      __IOM uint32_t STR        : 2;            /*!< [10..9] TX short current control.                                         */
            uint32_t            : 21;
    } bit;
  } LINOUTPHY;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000104) LININ Register                                             */
    
    struct {
      __IOM uint32_t TXEN       : 1;            /*!< [0..0] Enable LIN Tx.                                                     */
      __IOM uint32_t RXEN       : 1;            /*!< [1..1] Enable LIN rx.                                                     */
      __IOM uint32_t TXPU       : 1;            /*!< [2..2] TX 30K pull-up enable.                                             */
      __IOM uint32_t SLOPE_ENHANCE : 1;         /*!< [3..3] lin slope enhance.                                                 */
      __IOM uint32_t SLOPE_SEL  : 4;            /*!< [7..4] TX recessive to dominant slope control.                            */
      __IOM uint32_t STR        : 2;            /*!< [9..8] TX short current control.                                          */
            uint32_t            : 22;
    } bit;
  } LININPHY;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000108) LIN SWITCH Register                                        */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] LINS connects with LINM.                                           */
            uint32_t            : 31;
    } bit;
  } LINSWITCH;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000010C) LIN MODE Register                                          */
    
    struct {
      __IOM uint32_t switch_dbg_en : 1;         /*!< [0..0] switch dbg enable.                                                 */
      __IOM uint32_t switch_dbg_sel : 2;        /*!< [2..1] switch dbg select.                                                 */
      __IOM uint32_t switch_linc_slave : 1;     /*!< [3..3] lin controler connected with lins phy or linm phy.                 */
      __IOM uint32_t switch_monitor_en : 1;     /*!< [4..4] when linc connects with linsphy, this bit control whether
                                                     monitor tx, rx by pad.                                                    */
            uint32_t            : 19;
      __OM  uint32_t KEY        : 8;            /*!< [31..24] Only when KEY is 0xA5, write bit 0-4 is effective.               */
    } bit;
  } LINTESTMODE;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000110) LIN PHYCFG Register                                        */
    
    struct {
      __IOM uint32_t STOTEN     : 1;            /*!< [0..0] slave timeout detect enable                                        */
      __IOM uint32_t MTOTEN     : 1;            /*!< [1..1] master timeout detect enable                                       */
      __IOM uint32_t DUTEN      : 1;            /*!< [2..2] duty set enable                                                    */
      __IOM uint32_t DUTSEL     : 1;            /*!< [3..3] 0: duty increment; 1: duty decrement                               */
            uint32_t            : 12;
      __IOM uint32_t TXDUTCNT   : 8;            /*!< [23..16] tx duty count                                                    */
            uint32_t            : 8;
    } bit;
  } LINPHYCFG;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000114) LIN PHYIE Register                                         */
    
    struct {
      __IOM uint32_t STXTOE     : 1;            /*!< [0..0] slave tx timeout enable                                            */
      __IOM uint32_t MTXTOE     : 1;            /*!< [1..1] master tx timeout enable                                           */
            uint32_t            : 30;
    } bit;
  } LINPHYIE;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000118) LIN PHY Stauts Register                                    */
    
    struct {
      __IM  uint32_t STXTOF     : 1;            /*!< [0..0] slave tx timeout status                                            */
      __IM  uint32_t MTXTOF     : 1;            /*!< [1..1] master tx timeout status                                           */
            uint32_t            : 30;
    } bit;
  } LINPHYSR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000011C) LIN PHY Stauts Clear Register                              */
    
    struct {
      __OM  uint32_t STXTOCLR   : 1;            /*!< [0..0] slave tx timeout status clear                                      */
      __OM  uint32_t MTXTOCLR   : 1;            /*!< [1..1] slave tx timeout status clear                                      */
            uint32_t            : 30;
    } bit;
  } LINPHYCLR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000120) LIN PHY Timeout Count Register                             */
    
    struct {
      __IOM uint32_t MTOT       : 22;           /*!< [21..0] master tx timeout count                                           */
            uint32_t            : 10;
    } bit;
  } LINPHYMTOCNT;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000124) LIN PHY Timeout Count Register                             */
    
    struct {
      __IOM uint32_t STOT       : 22;           /*!< [21..0] slave tx timeout count                                            */
            uint32_t            : 10;
    } bit;
  } LINPHYSTOCNT;
} LIN_Type;                                     /*!< Size = 296 (0x128)                                                        */



/* =========================================================================================================================== */
/* ================                                            CAN                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief CAN (CAN)
  */

typedef struct {                                /*!< (@ 0x40017000) CAN Structure                                              */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) Core Release Register                                      */
    
    struct {
      __IM  uint32_t DAY        : 8;            /*!< [7..0] Time Stamp Day                                                     */
      __IM  uint32_t MON        : 8;            /*!< [15..8] Time Stamp Month                                                  */
      __IM  uint32_t YEAR       : 4;            /*!< [19..16] Time Stamp Year                                                  */
      __IM  uint32_t SUBSTEP    : 4;            /*!< [23..20] Sub-step of Core Release                                         */
      __IM  uint32_t STEP       : 4;            /*!< [27..24] Step of Core Release                                             */
      __IM  uint32_t REL        : 4;            /*!< [31..28] Core Release                                                     */
    } bit;
  } CREL;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) Endian Register                                            */
    
    struct {
      __IM  uint32_t ETV        : 32;           /*!< [31..0] Endianness Test Value                                             */
    } bit;
  } ENDN;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) Data Bit Timing & Prescaler Register                       */
    
    struct {
      __IOM uint32_t DSJW       : 4;            /*!< [3..0] Data (Re)Synchronization Jump Width                                */
      __IOM uint32_t DTSEG2     : 4;            /*!< [7..4] Data time segment after sample point                               */
      __IOM uint32_t DTSEG1     : 5;            /*!< [12..8] Data time segment before sample point                             */
            uint32_t            : 3;
      __IOM uint32_t DBRP       : 5;            /*!< [20..16] Data Bit Rate Prescaler.                                         */
            uint32_t            : 2;
      __IOM uint32_t TDC        : 1;            /*!< [23..23] Transmitter Delay Compensation                                   */
            uint32_t            : 8;
    } bit;
  } DBTP;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000010) Test Register                                              */
    
    struct {
            uint32_t            : 4;
      __IOM uint32_t LBCK       : 1;            /*!< [4..4] Loop Back ModeBit0 = Reset value, Loop Back Mode is disabled1
                                                     = Loop Back Mode is enabled                                               */
      __IOM uint32_t TX         : 2;            /*!< [6..5] Control of Transmit Pin.0x0 Reset value, m_ can tx controlled
                                                     by the CAN Core, updated at the end of the CAN bit time.01
                                                     Sample Point can be monitored at pin m can tx.10 Dominant(0)
                                                     level at pin m can tx.11 Recessive(1) level at pin m can
                                                     tx.                                                                       */
      __IM  uint32_t RX         : 1;            /*!< [7..7] Receive PinMonitors the actual value of pin m can rx0=
                                                     The CAN bus is dominant(m can rx='0')1= The CAN bus is
                                                     recessive(m can rx='1'                                                    */
            uint32_t            : 5;
      __IM  uint32_t PVAL       : 1;            /*!< [13..13] Prepared Valid0 = Value of TXBNP not valid1 = Value
                                                     of TXBNP valid                                                            */
            uint32_t            : 2;
      __IM  uint32_t TXBNS      : 5;            /*!< [20..16] Tx Buffer Number Started                                         */
      __IM  uint32_t SVAL       : 1;            /*!< [21..21] Started Valid.0 = Value of TXBNS not valid1 = Value
                                                     of TXBNS valid                                                            */
            uint32_t            : 10;
    } bit;
  } TEST;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000014) RAM Watchdog                                               */
    
    struct {
      __IOM uint32_t WDC        : 8;            /*!< [7..0] Watchdog Configuration                                             */
      __IM  uint32_t WDV        : 8;            /*!< [15..8] Watchdog Value                                                    */
            uint32_t            : 16;
    } bit;
  } RWD;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000018) CC Control Register                                        */
    
    struct {
      __IOM uint32_t INIT       : 1;            /*!< [0..0] Initialization                                                     */
      __IOM uint32_t CCE        : 1;            /*!< [1..1] Configuration Change Enable                                        */
      __IOM uint32_t ASM        : 1;            /*!< [2..2] Restricted Operation Mode                                          */
      __IM  uint32_t CSA        : 1;            /*!< [3..3] Clock Stop Acknowledge                                             */
      __IOM uint32_t CSR        : 1;            /*!< [4..4] Clock Stop Request                                                 */
      __IOM uint32_t MON        : 1;            /*!< [5..5] Bus Monitoring Mode                                                */
      __IOM uint32_t DAR        : 1;            /*!< [6..6] Disable Automatic Retransmission                                   */
      __IOM uint32_t TEST       : 1;            /*!< [7..7] Test Mode Enable                                                   */
      __IOM uint32_t FDOE       : 1;            /*!< [8..8] FD Operation Enable                                                */
      __IOM uint32_t BRSE       : 1;            /*!< [9..9] Bit Rate Switch Enable0 = Bit rate switching for transmissions
                                                     disabled1 = Bit rate switching for transmissions enabled                  */
      __IOM uint32_t UTSU       : 1;            /*!< [10..10] UUse Timestamping Unit0= internal time stamping1=External
                                                     time stamping by TSU                                                      */
      __IOM uint32_t WMM        : 1;            /*!< [11..11] MMWide Message Marker0 = 8-bit Message Marker used1
                                                     = 16-bit Message Marker used, replacing 16-bit timestamps
                                                     in Tx Event FIFO                                                          */
      __IOM uint32_t PXHD       : 1;            /*!< [12..12] Protocol Exception Handling Disable0 = Protocol exception
                                                     handling enabled1 = Protocol exception handling disabled                  */
      __IOM uint32_t EFBI       : 1;            /*!< [13..13] Edge Filtering during Bus Integration0 = Edge filtering
                                                     disabled1 = Two consecutive dominant tg required to detect
                                                     an edge for hard synchronization                                          */
      __IOM uint32_t TXP        : 1;            /*!< [14..14] Transmit Pause0 = Transmit pause disabled1 = Transmit
                                                     pause enabled                                                             */
      __IOM uint32_t NISO       : 1;            /*!< [15..15] Non lSO Operation0 = CAN FD frame format according
                                                     to lSO 11898-1:20151 = CAN FD frame format according to
                                                     Bosch CAN FD Specification V1.0                                           */
            uint32_t            : 16;
    } bit;
  } CCCR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) Nominal Bit Timing & Prescaler Register                    */
    
    struct {
      __IOM uint32_t NTSEG2     : 7;            /*!< [6..0] Nominal Time segment after sample point                            */
            uint32_t            : 1;
      __IOM uint32_t NTSEG1     : 8;            /*!< [15..8] Nominal Time segment before sample point                          */
      __IOM uint32_t NBRP       : 9;            /*!< [24..16] Nominal Bit Rate Prescaler                                       */
      __IOM uint32_t NSJW       : 7;            /*!< [31..25] Nominal (Re)Synchronization Jump Width                           */
    } bit;
  } NBTP;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000020) Timestamp Counter Configuration                            */
    
    struct {
      __IOM uint32_t TSS        : 2;            /*!< [1..0] Timestamp Select00= Timestamp counter value always Ox000001=
                                                     Timestamp counter value incremented according to TCP10=
                                                     External timestamp counter value used11= Same as 00                       */
            uint32_t            : 14;
      __IOM uint32_t TCP        : 4;            /*!< [19..16] Timestamp Counter Prescaler                                      */
            uint32_t            : 12;
    } bit;
  } TSCC;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000024) Timestamp Counter Value                                    */
    
    struct {
      __IOM uint32_t TSC        : 16;           /*!< [15..0] Timestamp Counter                                                 */
            uint32_t            : 16;
    } bit;
  } TSCV;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000028) Timeout Counter Configuration                              */
    
    struct {
      __IOM uint32_t ETOC       : 1;            /*!< [0..0] Enable Timeout Counter                                             */
      __IOM uint32_t TOS        : 2;            /*!< [2..1] Timeout Select00 = Continuous operation01 = Timeout controlled
                                                     by Tx Event FIFO10 = Timeout controlled by Rx FIFO 011
                                                     = Timeout controlled by Rx FIFO 1                                         */
            uint32_t            : 13;
      __IOM uint32_t TOP        : 16;           /*!< [31..16] Timeout Period                                                   */
    } bit;
  } TOCC;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000002C) Timeout Counter Value                                      */
    
    struct {
      __IOM uint32_t TOC        : 16;           /*!< [15..0] Timeout Counter                                                   */
            uint32_t            : 16;
    } bit;
  } TOCV;
  __IM  uint32_t  RESERVED1[4];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000040) Error Counter Register                                     */
    
    struct {
      __IM  uint32_t TEC        : 8;            /*!< [7..0] Transmit Error Counter                                             */
      __IM  uint32_t REC        : 7;            /*!< [14..8] Receive Error Counter                                             */
            uint32_t            : 1;
      __IM  uint32_t CEL        : 8;            /*!< [23..16] CAN Error Logging                                                */
            uint32_t            : 8;
    } bit;
  } ECR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000044) Protocol Status Register                                   */
    
    struct {
      __IM  uint32_t LEC        : 3;            /*!< [2..0] Last Error CodeO = No Error: No error occurred since
                                                     LEC has been reset by successful reception or transmis-sion.1
                                                     = Stuff Error: More than 5 equal bits in a sequence have
                                                     occurred in a part of a received mes-sage where this is
                                                     not allowed.2 = Form Error: A fixed format part of a received
                                                     frame has the wrong format.3 = AckError: The message transmitted
                                                     by the M_ CAN was not acknowledged by another node.4 =
                                                     Bit1Error: During the transmission of a message (with the
                                                     exception of the arbitration                                              */
      __IM  uint32_t ACT        : 2;            /*!< [4..3] Activity00 = Synchronizing - node is synchronizing on
                                                     CAN communication01 = Idle - node is neither receiver nor
                                                     transmitter10 = Receiver - node is operating as receiver11
                                                     = Transmitter - node is operating as transmitter                          */
      __IM  uint32_t EP         : 1;            /*!< [5..5] Error Passive                                                      */
      __IM  uint32_t EW         : 1;            /*!< [6..6] Warning Status                                                     */
      __IM  uint32_t BO         : 1;            /*!< [7..7] Bus_Off Status                                                     */
      __IM  uint32_t DLEC       : 3;            /*!< [10..8] Data PhaseLast Error Code                                         */
      __IM  uint32_t RESI       : 1;            /*!< [11..11] ESI flag of last received CAN FD Message                         */
      __IM  uint32_t RBRS       : 1;            /*!< [12..12] BRS flag of last received CAN FD Message                         */
      __IM  uint32_t RFDF       : 1;            /*!< [13..13] This bit is set independent of acceptance filtering.0
                                                     = Since this bit was reset by the CPU, no CAN FD message
                                                     has been received1 = Message in CAN FD format with FDF
                                                     flag set has been received                                                */
      __IM  uint32_t PXE        : 1;            /*!< [14..14] Protocol Exception Event                                         */
            uint32_t            : 1;
      __IM  uint32_t TDCV       : 7;            /*!< [22..16] Transmitter Delay Compensation Value                             */
            uint32_t            : 9;
    } bit;
  } PSR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000048) Transmitter Delay Compensation Register                    */
    
    struct {
      __IOM uint32_t TDCF       : 7;            /*!< [6..0] Transmitter Delay Compensation Filter Window Length                */
            uint32_t            : 1;
      __IOM uint32_t TDCO       : 7;            /*!< [14..8] Transmitter Delay Compensation SSP Offset                         */
            uint32_t            : 17;
    } bit;
  } TDCR;
  __IM  uint32_t  RESERVED2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000050) Interrupt Register                                         */
    
    struct {
      __IOM uint32_t RF0N       : 1;            /*!< [0..0] Rx FIFO 0 New Message                                              */
      __IOM uint32_t RF0W       : 1;            /*!< [1..1] Rx FlFO 0 Watermark Reached                                        */
      __IOM uint32_t RF0F       : 1;            /*!< [2..2] Rx FIFO 0 Full                                                     */
      __IOM uint32_t RF0L       : 1;            /*!< [3..3] Rx FIFO 0 Message Lost                                             */
      __IOM uint32_t RF1N       : 1;            /*!< [4..4] Rx FIFO 1 New Message                                              */
      __IOM uint32_t RF1W       : 1;            /*!< [5..5] Rx FIFO 1 Watermark Reached                                        */
      __IOM uint32_t RF1F       : 1;            /*!< [6..6] Rx FIFO 1 Full                                                     */
      __IOM uint32_t RF1L       : 1;            /*!< [7..7] Rx FIFO 1 Message Lost                                             */
      __IOM uint32_t HPM        : 1;            /*!< [8..8] High Priority Message                                              */
      __IOM uint32_t TC         : 1;            /*!< [9..9] Transmission Completed                                             */
      __IOM uint32_t TCF        : 1;            /*!< [10..10] Transmission Cancellation Finished                               */
      __IOM uint32_t TFE        : 1;            /*!< [11..11] Tx FIFO Empty                                                    */
      __IOM uint32_t TEFN       : 1;            /*!< [12..12] Tx Event FIFO New Entry                                          */
      __IOM uint32_t TEFW       : 1;            /*!< [13..13] Tx Event FlFO Watermark Reached                                  */
      __IOM uint32_t TEFF       : 1;            /*!< [14..14] Tx Event FIFO Full                                               */
      __IOM uint32_t TEFL       : 1;            /*!< [15..15] Tx Event FIFO Element Lost                                       */
      __IOM uint32_t TSW        : 1;            /*!< [16..16] Timestamp Wraparound                                             */
      __IOM uint32_t MRAF       : 1;            /*!< [17..17] Message RAM Access Failure                                       */
      __IOM uint32_t TOO        : 1;            /*!< [18..18] Timeout Occurred                                                 */
      __IOM uint32_t DRX        : 1;            /*!< [19..19] Message stored to Dedicated Rx Buffer                            */
      __IOM uint32_t BEC        : 1;            /*!< [20..20] Bit Error Corrected                                              */
      __IOM uint32_t BEU        : 1;            /*!< [21..21] Bit Error Uncorrected                                            */
      __IOM uint32_t ELO        : 1;            /*!< [22..22] Error Logging Overflow                                           */
      __IOM uint32_t EP         : 1;            /*!< [23..23] Error Passive                                                    */
      __IOM uint32_t EW         : 1;            /*!< [24..24] Warning Status                                                   */
      __IOM uint32_t BO         : 1;            /*!< [25..25] Bus_Off Status                                                   */
      __IOM uint32_t WDI        : 1;            /*!< [26..26] Watchdog Interrupt                                               */
      __IOM uint32_t PEA        : 1;            /*!< [27..27] Protocol Error in Arbitration Phase(Nominal Bit Time
                                                     is used)                                                                  */
      __IOM uint32_t PED        : 1;            /*!< [28..28] Protocol Error in Data Phase (Data Bit Time is used)             */
      __IOM uint32_t ARA        : 1;            /*!< [29..29] Access to Reserved Address                                       */
            uint32_t            : 2;
    } bit;
  } IR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000054) Interrupt Enable                                           */
    
    struct {
      __IOM uint32_t RF0NE      : 1;            /*!< [0..0] Rx FIFO 0 New Message Interrupt Enable                             */
      __IOM uint32_t RF0WE      : 1;            /*!< [1..1] Rx FIFO 0 Watermark Reached Interrupt Enable                       */
      __IOM uint32_t RF0FE      : 1;            /*!< [2..2] Rx FIFO 0 Full Interrupt Enable                                    */
      __IOM uint32_t RF0LE      : 1;            /*!< [3..3] Rx FIFO 0 Message Lost Interrupt Enable                            */
      __IOM uint32_t RF1NE      : 1;            /*!< [4..4] Rx FlFO 1 New Message Interrupt Enable                             */
      __IOM uint32_t RF1WE      : 1;            /*!< [5..5] Rx FlFO 1 Watermark Reached Interrupt Enable                       */
      __IOM uint32_t RF1FE      : 1;            /*!< [6..6] Rx FIFO 1 Full Interrupt Enable                                    */
      __IOM uint32_t RF1LE      : 1;            /*!< [7..7] Rx FIFO 1 Message Lost Interrupt Enable                            */
      __IOM uint32_t HPME       : 1;            /*!< [8..8] High Priority Message Interrupt Enable                             */
      __IOM uint32_t TCE        : 1;            /*!< [9..9] Transmission Completed Interrupt Enable                            */
      __IOM uint32_t TCFE       : 1;            /*!< [10..10] Transmission Cancellation Finished Interrupt Enable              */
      __IOM uint32_t TFEE       : 1;            /*!< [11..11] Tx FIFO E mpty Interrupt Enable                                  */
      __IOM uint32_t TEFNE      : 1;            /*!< [12..12] Tx Event FIFO New Entry Interrupt Enable                         */
      __IOM uint32_t TEFWE      : 1;            /*!< [13..13] Tx Event FIFO Watermark Reached Interrupt Enable                 */
      __IOM uint32_t TEFFE      : 1;            /*!< [14..14] Tx Event FIFO Full Interrupt Enable                              */
      __IOM uint32_t TEFLE      : 1;            /*!< [15..15] Tx Event FIFO Event Lost Interrupt Enable                        */
      __IOM uint32_t TSWE       : 1;            /*!< [16..16] Timestamp Wraparound Interrupt Enable                            */
      __IOM uint32_t MRAFE      : 1;            /*!< [17..17] Message RAM Access Failure Interrupt Enable                      */
      __IOM uint32_t TOOE       : 1;            /*!< [18..18] Timeout Occurred Interrupt Enable                                */
      __IOM uint32_t DRXE       : 1;            /*!< [19..19] Message stored to Dedicated Rx Buffer Interrupt Enable           */
      __IOM uint32_t BECE       : 1;            /*!< [20..20] Bit Error Corrected Interrupt Enable                             */
      __IOM uint32_t BEUE       : 1;            /*!< [21..21] Bit Error Uncorrected Interrupt Enable                           */
      __IOM uint32_t ELOE       : 1;            /*!< [22..22] Error Logging Overflow Interrupt Enable                          */
      __IOM uint32_t EPE        : 1;            /*!< [23..23] Error Passive Interrupt Enable                                   */
      __IOM uint32_t EWE        : 1;            /*!< [24..24] Warning Status Interrupt Enable                                  */
      __IOM uint32_t BOE        : 1;            /*!< [25..25] Bus_Off Status Interrupt Enable                                  */
      __IOM uint32_t WDIE       : 1;            /*!< [26..26] Watchdog Interrupt Enable                                        */
      __IOM uint32_t PEAE       : 1;            /*!< [27..27] Protocol Error in Arbitration Phase Enable                       */
      __IOM uint32_t PEDE       : 1;            /*!< [28..28] Protocol Error in Data Phase Enable                              */
      __IOM uint32_t ARAE       : 1;            /*!< [29..29] Access to Reserved Address Enable                                */
            uint32_t            : 2;
    } bit;
  } IE;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000058) Interrupt Line Select                                      */
    
    struct {
      __IOM uint32_t RF0NL      : 1;            /*!< [0..0] Rx FIFO 0 New Message Interrupt Line                               */
      __IOM uint32_t RF0WL      : 1;            /*!< [1..1] Rx FIFO 0 Watermark Reached Interrupt Line                         */
      __IOM uint32_t RF0FL      : 1;            /*!< [2..2] Rx FIFO 0 Full Interrupt Line                                      */
      __IOM uint32_t RF0LL      : 1;            /*!< [3..3] Rx FIFO 0 Message Lost Interrupt Line                              */
      __IOM uint32_t RF1NL      : 1;            /*!< [4..4] Rx FIFO 1 New Message Interrupt Line                               */
      __IOM uint32_t RF1WL      : 1;            /*!< [5..5] Rx FIFO 1 Watermark Reached Interrupt Line                         */
      __IOM uint32_t RF1FL      : 1;            /*!< [6..6] Rx FIFO 1 Full Interrupt Line                                      */
      __IOM uint32_t RF1LL      : 1;            /*!< [7..7] Rx FlFO 1 Message Lost Interrupt Line                              */
      __IOM uint32_t HPML       : 1;            /*!< [8..8] High Priority Message Interrupt Line                               */
      __IOM uint32_t TCL        : 1;            /*!< [9..9] Transmission Completed Interrupt Line                              */
      __IOM uint32_t TCFL       : 1;            /*!< [10..10] Transmission Cancellation Finished Interrupt Line                */
      __IOM uint32_t TFEL       : 1;            /*!< [11..11] Tx FIFO E mpty Interrupt Line                                    */
      __IOM uint32_t TEFNL      : 1;            /*!< [12..12] Tx Event FIFO New Entry Interrupt Line                           */
      __IOM uint32_t TEFWL      : 1;            /*!< [13..13] Tx Event FIFO Watermark Reached Interrupt Line                   */
      __IOM uint32_t TEFFL      : 1;            /*!< [14..14] Tx Event FIFO F ull Interrupt Line                               */
      __IOM uint32_t TEFLL      : 1;            /*!< [15..15] Tx Event FIFO Event Lost Interrupt Line                          */
      __IOM uint32_t TSWL       : 1;            /*!< [16..16] Timestamp Wraparound Interrupt Line                              */
      __IOM uint32_t MRAFL      : 1;            /*!< [17..17] Message RAM Access Failure Interrupt Line                        */
      __IOM uint32_t TOOL       : 1;            /*!< [18..18] Timeout Occurred Interrupt Line                                  */
      __IOM uint32_t DRXL       : 1;            /*!< [19..19] Message stored to [Dedicated Rx Buffer Interrupt Line            */
      __IOM uint32_t BECL       : 1;            /*!< [20..20] Bit Error Corrected Interrupt Line                               */
      __IOM uint32_t BEUL       : 1;            /*!< [21..21] Bit Error Uncorrected Interrupt Line                             */
      __IOM uint32_t ELOL       : 1;            /*!< [22..22] Error Logging Overflow Interrupt Line                            */
      __IOM uint32_t EPL        : 1;            /*!< [23..23] Error Passive Interrupt Line                                     */
      __IOM uint32_t EWL        : 1;            /*!< [24..24] Warning Status Interrupt Line                                    */
      __IOM uint32_t BOL        : 1;            /*!< [25..25] Bus_Off Status Interrupt Line                                    */
      __IOM uint32_t WDIL       : 1;            /*!< [26..26] Watchdog Interrupt Line                                          */
      __IOM uint32_t PEAL       : 1;            /*!< [27..27] Protocol Error in Arbitration Phase Line                         */
      __IOM uint32_t PEDL       : 1;            /*!< [28..28] Protocol Error in Data Phase Line                                */
      __IOM uint32_t ARAL       : 1;            /*!< [29..29] Access to Reserved Address Line                                  */
            uint32_t            : 2;
    } bit;
  } ILS;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000005C) Interrupt Line Enable                                      */
    
    struct {
      __IOM uint32_t EINTO      : 1;            /*!< [0..0] Enable Interrupt Line 0                                            */
      __IOM uint32_t EINT1      : 1;            /*!< [1..1] Enable Interrupt Line 1                                            */
            uint32_t            : 30;
    } bit;
  } ILE;
  __IM  uint32_t  RESERVED3[8];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000080) Global Filter Configuration                                */
    
    struct {
      __IOM uint32_t RRFE       : 1;            /*!< [0..0] Reject Remote Frames Extended                                      */
      __IOM uint32_t RRFS       : 1;            /*!< [1..1] Reject Remote Frames Standard                                      */
      __IOM uint32_t ANFE       : 2;            /*!< [3..2] Accept Non-matching Frames Extended00 = Accept in Rx
                                                     FIFO 001 = Accept in Rx FIFO 11x = Reject                                 */
      __IOM uint32_t ANFS       : 2;            /*!< [5..4] Accept Non-matching Frames Standard00 = Accept in Rx
                                                     FIFO 001 = Accept in Rx FIFO 11x = Reject                                 */
            uint32_t            : 26;
    } bit;
  } GFC;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000084) Standard ID Filter Configuration                           */
    
    struct {
            uint32_t            : 2;
      __IOM uint32_t FLSSA      : 14;           /*!< [15..2] Filter List Standard Start Address                                */
      __IOM uint32_t LSS        : 8;            /*!< [23..16] List Size Standard0 = No standard Message I D filter1-128
                                                     = Number of standard Message I D filter elements>128 =
                                                     Values greater than 128 are interpreted as 128                            */
            uint32_t            : 8;
    } bit;
  } SIDFC;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000088) Extended ID Filter Configuration                           */
    
    struct {
            uint32_t            : 2;
      __IOM uint32_t FLESA      : 14;           /*!< [15..2] Start Address                                                     */
      __IOM uint32_t LSE        : 7;            /*!< [22..16] List Size Extended0 = No extended Message I D filter1-64
                                                     = Number of extended Message I D filter elements>64 = Values
                                                     greater than 64 are interpreted as 64                                     */
            uint32_t            : 9;
    } bit;
  } XIDFC;
  __IM  uint32_t  RESERVED4;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000090) Extended ID AND Mask                                       */
    
    struct {
      __IOM uint32_t EIDM       : 29;           /*!< [28..0] Extended ID Mask                                                  */
            uint32_t            : 3;
    } bit;
  } XIDAM;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000094) High Priority Message Status                               */
    
    struct {
      __IM  uint32_t BIDX       : 6;            /*!< [5..0] Buffer Index                                                       */
      __IM  uint32_t MSI        : 2;            /*!< [7..6] Message Storage Indicator00 = No FIFO selected01 = FIFO
                                                     message lost10 = Message stored in FIFO 011 = Message stored
                                                     in FlFO 1                                                                 */
      __IM  uint32_t FIDX       : 7;            /*!< [14..8] Filter Index                                                      */
      __IM  uint32_t FLST       : 1;            /*!< [15..15] Filter List0 = Standard Filter List1 = Extended Filter
                                                     List                                                                      */
            uint32_t            : 16;
    } bit;
  } HPMS;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000098) New Data 1                                                 */
    
    struct {
      __IOM uint32_t ND0        : 1;            /*!< [0..0] New Data                                                           */
      __IOM uint32_t ND1        : 1;            /*!< [1..1] New Data                                                           */
      __IOM uint32_t ND2        : 1;            /*!< [2..2] New Data                                                           */
      __IOM uint32_t ND3        : 1;            /*!< [3..3] New Data                                                           */
      __IOM uint32_t ND4        : 1;            /*!< [4..4] New Data                                                           */
      __IOM uint32_t ND5        : 1;            /*!< [5..5] New Data                                                           */
      __IOM uint32_t ND6        : 1;            /*!< [6..6] New Data                                                           */
      __IOM uint32_t ND7        : 1;            /*!< [7..7] New Data                                                           */
      __IOM uint32_t ND8        : 1;            /*!< [8..8] New Data                                                           */
      __IOM uint32_t ND9        : 1;            /*!< [9..9] New Data                                                           */
      __IOM uint32_t ND10       : 1;            /*!< [10..10] New Data                                                         */
      __IOM uint32_t ND11       : 1;            /*!< [11..11] New Data                                                         */
      __IOM uint32_t ND12       : 1;            /*!< [12..12] New Data                                                         */
      __IOM uint32_t ND13       : 1;            /*!< [13..13] New Data                                                         */
      __IOM uint32_t ND14       : 1;            /*!< [14..14] New Data                                                         */
      __IOM uint32_t ND15       : 1;            /*!< [15..15] New Data                                                         */
      __IOM uint32_t ND16       : 1;            /*!< [16..16] New Data                                                         */
      __IOM uint32_t ND17       : 1;            /*!< [17..17] New Data                                                         */
      __IOM uint32_t ND18       : 1;            /*!< [18..18] New Data                                                         */
      __IOM uint32_t ND19       : 1;            /*!< [19..19] New Data                                                         */
      __IOM uint32_t ND20       : 1;            /*!< [20..20] New Data                                                         */
      __IOM uint32_t ND21       : 1;            /*!< [21..21] New Data                                                         */
      __IOM uint32_t ND22       : 1;            /*!< [22..22] New Data                                                         */
      __IOM uint32_t ND23       : 1;            /*!< [23..23] New Data                                                         */
      __IOM uint32_t ND24       : 1;            /*!< [24..24] New Data                                                         */
      __IOM uint32_t ND25       : 1;            /*!< [25..25] New Data                                                         */
      __IOM uint32_t ND26       : 1;            /*!< [26..26] New Data                                                         */
      __IOM uint32_t ND27       : 1;            /*!< [27..27] New Data                                                         */
      __IOM uint32_t ND28       : 1;            /*!< [28..28] New Data                                                         */
      __IOM uint32_t ND29       : 1;            /*!< [29..29] New Data                                                         */
      __IOM uint32_t ND30       : 1;            /*!< [30..30] New Data                                                         */
      __IOM uint32_t ND31       : 1;            /*!< [31..31] New Data                                                         */
    } bit;
  } NDAT1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000009C) New Data 2                                                 */
    
    struct {
      __IOM uint32_t ND32       : 1;            /*!< [0..0] New Data                                                           */
      __IOM uint32_t ND33       : 1;            /*!< [1..1] New Data                                                           */
      __IOM uint32_t ND34       : 1;            /*!< [2..2] New Data                                                           */
      __IOM uint32_t ND35       : 1;            /*!< [3..3] New Data                                                           */
      __IOM uint32_t ND36       : 1;            /*!< [4..4] New Data                                                           */
      __IOM uint32_t ND37       : 1;            /*!< [5..5] New Data                                                           */
      __IOM uint32_t ND38       : 1;            /*!< [6..6] New Data                                                           */
      __IOM uint32_t ND39       : 1;            /*!< [7..7] New Data                                                           */
      __IOM uint32_t ND40       : 1;            /*!< [8..8] New Data                                                           */
      __IOM uint32_t ND41       : 1;            /*!< [9..9] New Data                                                           */
      __IOM uint32_t ND42       : 1;            /*!< [10..10] New Data                                                         */
      __IOM uint32_t ND43       : 1;            /*!< [11..11] New Data                                                         */
      __IOM uint32_t ND44       : 1;            /*!< [12..12] New Data                                                         */
      __IOM uint32_t ND45       : 1;            /*!< [13..13] New Data                                                         */
      __IOM uint32_t ND46       : 1;            /*!< [14..14] New Data                                                         */
      __IOM uint32_t ND47       : 1;            /*!< [15..15] New Data                                                         */
      __IOM uint32_t ND48       : 1;            /*!< [16..16] New Data                                                         */
      __IOM uint32_t ND49       : 1;            /*!< [17..17] New Data                                                         */
      __IOM uint32_t ND50       : 1;            /*!< [18..18] New Data                                                         */
      __IOM uint32_t ND51       : 1;            /*!< [19..19] New Data                                                         */
      __IOM uint32_t ND52       : 1;            /*!< [20..20] New Data                                                         */
      __IOM uint32_t ND53       : 1;            /*!< [21..21] New Data                                                         */
      __IOM uint32_t ND54       : 1;            /*!< [22..22] New Data                                                         */
      __IOM uint32_t ND55       : 1;            /*!< [23..23] New Data                                                         */
      __IOM uint32_t ND56       : 1;            /*!< [24..24] New Data                                                         */
      __IOM uint32_t ND57       : 1;            /*!< [25..25] New Data                                                         */
      __IOM uint32_t ND58       : 1;            /*!< [26..26] New Data                                                         */
      __IOM uint32_t ND59       : 1;            /*!< [27..27] New Data                                                         */
      __IOM uint32_t ND60       : 1;            /*!< [28..28] New Data                                                         */
      __IOM uint32_t ND61       : 1;            /*!< [29..29] New Data                                                         */
      __IOM uint32_t ND62       : 1;            /*!< [30..30] New Data                                                         */
      __IOM uint32_t ND63       : 1;            /*!< [31..31] New Data                                                         */
    } bit;
  } NDAT2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000A0) Rx FIFO 0 Configuration                                    */
    
    struct {
            uint32_t            : 2;
      __IOM uint32_t F0SA       : 14;           /*!< [15..2] Rx FIFO 0 Start Address                                           */
      __IOM uint32_t F0S        : 7;            /*!< [22..16] Rx FIFO 0 Size0 = No Rx FIFO 01-64 = Number of Rx FIFO
                                                     O elements>64 = Values greater than 64 are interpreted
                                                     as 64                                                                     */
            uint32_t            : 1;
      __IOM uint32_t F0WM       : 7;            /*!< [30..24] RX FIFO 0 Watermark0 = Watermark interrupt disabled1-64
                                                     = Level for Rx FIFO O watermark interrupt (IR.RF0W)>64
                                                     = Watermark interrupt disabled                                            */
      __IOM uint32_t F0OM       : 1;            /*!< [31..31] FIFO 0 Operation Mode0 = FIFO O blocking mode1 = FIFO
                                                     O overwrite mode                                                          */
    } bit;
  } RXF0C;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000A4) Rx FIFO 0 Status                                           */
    
    struct {
      __IM  uint32_t F0FL       : 7;            /*!< [6..0] Rx FIFO 0 Fill Level                                               */
            uint32_t            : 1;
      __IM  uint32_t F0GI       : 6;            /*!< [13..8] Rx FIFO 0 Get Index                                               */
            uint32_t            : 2;
      __IM  uint32_t F0PI       : 6;            /*!< [21..16] Rx FIFO 0 Put Index                                              */
            uint32_t            : 2;
      __IM  uint32_t F0F        : 1;            /*!< [24..24] Rx FIFO O Full0 = Rx FIFO O not full1 = Rx FIFO O full           */
      __IM  uint32_t RF0L       : 1;            /*!< [25..25] Rx FIFO 0 Message Lost0 = No Rx FIFO O message lost1
                                                     = Rx FlFO O message lost, also set after write attempt
                                                     to Rx FlFO O of size zero                                                 */
            uint32_t            : 6;
    } bit;
  } RXF0S;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000A8) Rx FIFO 0 Acknowledge                                      */
    
    struct {
      __IOM uint32_t F0AI       : 6;            /*!< [5..0] Rx FIFO 0 Acknowledge Index                                        */
            uint32_t            : 26;
    } bit;
  } RXF0A;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000AC) Rx Buffer Configuration                                    */
    
    struct {
            uint32_t            : 2;
      __IOM uint32_t RBSA       : 14;           /*!< [15..2] Rx Buffer Start AddresS                                           */
            uint32_t            : 16;
    } bit;
  } RXBC;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000B0) Rx FIFO 1 Configuration                                    */
    
    struct {
            uint32_t            : 2;
      __IOM uint32_t F1SA       : 14;           /*!< [15..2] Rx FIFO 1 Start Address                                           */
      __IOM uint32_t F1S        : 7;            /*!< [22..16] Rx FIFO 1 Size0 = The Rx FlFO 1 elements are indexed
                                                     from 0 to F1S - 11-64 = No Rx FIFO 1>64 = Number of Rx
                                                     FIFO 1 elements                                                           */
            uint32_t            : 1;
      __IOM uint32_t F1WM       : 7;            /*!< [30..24] Rx FlFO 1 Watermark0 = Watermark interrupt disabled1-64
                                                     = Level for Rx FIFO 1 watermark interrupt (IR.RF1W)>64
                                                     = Watermark interrupt disabled                                            */
      __IOM uint32_t F1OM       : 1;            /*!< [31..31] FIFO 1 Operation Mode0 = FIFO 1 blocking mode1 = FIFO
                                                     1 overwrite mode                                                          */
    } bit;
  } RXF1C;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000B4) Rx FIFO 1 Status                                           */
    
    struct {
      __IM  uint32_t F1FL       : 7;            /*!< [6..0] Rx FIFO 1 Fill Level                                               */
            uint32_t            : 1;
      __IM  uint32_t F1GI       : 6;            /*!< [13..8] Rx FIFO 1 Get Index                                               */
            uint32_t            : 2;
      __IM  uint32_t F1PI       : 6;            /*!< [21..16] Rx FIFO 1 Put Index                                              */
            uint32_t            : 2;
      __IM  uint32_t F1F        : 1;            /*!< [24..24] Rx FIFO 1 Full0 = Rx FIFO 1 not full1 = Rx FIFO 1 full           */
      __IM  uint32_t RF1L       : 1;            /*!< [25..25] Rx FIFO 1 Message Lost0 = No Rx FIFO 1 message lost1
                                                     = Rx FIFO 1 message lost, also set after write attempt
                                                     to Rx FIFO 1 of size zero                                                 */
            uint32_t            : 4;
      __IM  uint32_t DMS        : 2;            /*!< [31..30] Debug Message Status00 = Idle state, wait for reception
                                                     of debug messages, DMA request is cleared01 = Debug message
                                                     A received10 = Debug messages A, B received11 = Debug messages
                                                     A, B, C received, DMA request is set                                      */
    } bit;
  } RXF1S;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000B8) Rx FIFO 1 Acknowledge                                      */
    
    struct {
      __IOM uint32_t F1Al       : 6;            /*!< [5..0] Rx FIFO 1 Acknowledge Index                                        */
            uint32_t            : 26;
    } bit;
  } RXF1A;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000BC) Rx Buffer / FIFO Element Size Configuration                */
    
    struct {
      __IOM uint32_t F0DS       : 3;            /*!< [2..0] Rx FIFO 0 Data Field Size000 = 8 byte data field001 =
                                                     12 byte data field010 = 16 byte data field011 = 20 byte
                                                     data field100 = 24 byte data field101 = 32 byte data field110
                                                     = 48 byte data field111 = 64 byte data field                              */
            uint32_t            : 1;
      __IOM uint32_t F1DS       : 3;            /*!< [6..4] Rx FIFO 1 Data Field Size000 = 8 byte data field001 =
                                                     12 byte data field010 = 16 byte data field011 = 20 byte
                                                     data field100 = 24 byte data field101 = 32 byte data field110
                                                     = 48 byte data field111 = 64 byte data field                              */
            uint32_t            : 1;
      __IOM uint32_t RBDS       : 3;            /*!< [10..8] Rx Buffer Data Field Size000 = 8 byte data field001
                                                     = 12 byte data field010 = 16 byte data field011 = 20 byte
                                                     data field100 = 24 byte data field101 = 32 byte data field110
                                                     = 48 byte data field111 = 64 byte data field                              */
            uint32_t            : 21;
    } bit;
  } RXESC;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000C0) Tx Buffer Configuration                                    */
    
    struct {
            uint32_t            : 2;
      __IOM uint32_t TBSA       : 14;           /*!< [15..2] Tx Buffers Start Address                                          */
      __IOM uint32_t NDTB       : 6;            /*!< [21..16] Number of Dedicated Transmit Buffers0 = No Dedicated
                                                     Tx Buffers1-32 = Number of Dedicated Tx Buffers>32 = Values
                                                     greater than 32 are interpreted as 32                                     */
            uint32_t            : 2;
      __IOM uint32_t TFQS       : 6;            /*!< [29..24] Transmit FIFO/Queue Size0 = No Tx FIF O/Queue1-32 =
                                                     Number of Tx Buffers used for Tx FIF O/Queue>32 = Values
                                                     greater than 32 are interpreted as 32                                     */
      __IOM uint32_t TFQM       : 1;            /*!< [30..30] Tx FIFO/Queue Mode0 = Tx FIFO operation1 = Tx Queue
                                                     operation                                                                 */
            uint32_t            : 1;
    } bit;
  } TXBC;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000C4) Tx FIFO/Queue Status                                       */
    
    struct {
      __IM  uint32_t TFFL       : 6;            /*!< [5..0] Tx FIFO Free Level                                                 */
            uint32_t            : 2;
      __IM  uint32_t TFGI       : 5;            /*!< [12..8] Tx FIFO Get Index                                                 */
            uint32_t            : 3;
      __IM  uint32_t TFQPI      : 5;            /*!< [20..16] Tx FIFO/Queue Put Index                                          */
      __IM  uint32_t TFQF       : 1;            /*!< [21..21] Tx FIFO/Queue Full0 = Tx FIFO/Queue not full1 = Tx
                                                     FIFO/Queue full                                                           */
            uint32_t            : 10;
    } bit;
  } TXFQS;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000C8) Tx Buffer Element Size Configuration                       */
    
    struct {
      __IOM uint32_t TBDS       : 3;            /*!< [2..0] Tx Buffer Data Field Size000 = 8 byte data field001 =
                                                     12 byte data field010 = 16 byte data field011 = 20 byte
                                                     data field100 = 24 byte data field101 = 32 byte data field110
                                                     = 48 byte data field111 = 64 byte data field                              */
            uint32_t            : 29;
    } bit;
  } TXESC;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000CC) Tx Buffer Request Pending                                  */
    
    struct {
      __IM  uint32_t TRP0       : 1;            /*!< [0..0] Transmission Request Pending                                       */
      __IM  uint32_t TRP1       : 1;            /*!< [1..1] Transmission Request Pending                                       */
      __IM  uint32_t TRP2       : 1;            /*!< [2..2] Transmission Request Pending                                       */
      __IM  uint32_t TRP3       : 1;            /*!< [3..3] Transmission Request Pending                                       */
      __IM  uint32_t TRP4       : 1;            /*!< [4..4] Transmission Request Pending                                       */
      __IM  uint32_t TRP5       : 1;            /*!< [5..5] Transmission Request Pending                                       */
      __IM  uint32_t TRP6       : 1;            /*!< [6..6] Transmission Request Pending                                       */
      __IM  uint32_t TRP7       : 1;            /*!< [7..7] Transmission Request Pending                                       */
      __IM  uint32_t TRP8       : 1;            /*!< [8..8] Transmission Request Pending                                       */
      __IM  uint32_t TRP9       : 1;            /*!< [9..9] Transmission Request Pending                                       */
      __IM  uint32_t TRP10      : 1;            /*!< [10..10] Transmission Request Pending                                     */
      __IM  uint32_t TRP11      : 1;            /*!< [11..11] Transmission Request Pending                                     */
      __IM  uint32_t TRP12      : 1;            /*!< [12..12] Transmission Request Pending                                     */
      __IM  uint32_t TRP13      : 1;            /*!< [13..13] Transmission Request Pending                                     */
      __IM  uint32_t TRP14      : 1;            /*!< [14..14] Transmission Request Pending                                     */
      __IM  uint32_t TRP15      : 1;            /*!< [15..15] Transmission Request Pending                                     */
      __IM  uint32_t TRP16      : 1;            /*!< [16..16] Transmission Request Pending                                     */
      __IM  uint32_t TRP17      : 1;            /*!< [17..17] Transmission Request Pending                                     */
      __IM  uint32_t TRP18      : 1;            /*!< [18..18] Transmission Request Pending                                     */
      __IM  uint32_t TRP19      : 1;            /*!< [19..19] Transmission Request Pending                                     */
      __IM  uint32_t TRP20      : 1;            /*!< [20..20] Transmission Request Pending                                     */
      __IM  uint32_t TRP21      : 1;            /*!< [21..21] Transmission Request Pending                                     */
      __IM  uint32_t TRP22      : 1;            /*!< [22..22] Transmission Request Pending                                     */
      __IM  uint32_t TRP23      : 1;            /*!< [23..23] Transmission Request Pending                                     */
      __IM  uint32_t TRP24      : 1;            /*!< [24..24] Transmission Request Pending                                     */
      __IM  uint32_t TRP25      : 1;            /*!< [25..25] Transmission Request Pending                                     */
      __IM  uint32_t TRP26      : 1;            /*!< [26..26] Transmission Request Pending                                     */
      __IM  uint32_t TRP27      : 1;            /*!< [27..27] Transmission Request Pending                                     */
      __IM  uint32_t TRP28      : 1;            /*!< [28..28] Transmission Request Pending                                     */
      __IM  uint32_t TRP29      : 1;            /*!< [29..29] Transmission Request Pending                                     */
      __IM  uint32_t TRP30      : 1;            /*!< [30..30] Transmission Request Pending                                     */
      __IM  uint32_t TRP31      : 1;            /*!< [31..31] Transmission Request Pending                                     */
    } bit;
  } TXBRP;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000D0) Tx Buffer Add Request                                      */
    
    struct {
      __IOM uint32_t AR0        : 1;            /*!< [0..0] Add Request                                                        */
      __IOM uint32_t AR1        : 1;            /*!< [1..1] Add Request                                                        */
      __IOM uint32_t AR2        : 1;            /*!< [2..2] Add Request                                                        */
      __IOM uint32_t AR3        : 1;            /*!< [3..3] Add Request                                                        */
      __IOM uint32_t AR4        : 1;            /*!< [4..4] Add Request                                                        */
      __IOM uint32_t AR5        : 1;            /*!< [5..5] Add Request                                                        */
      __IOM uint32_t AR6        : 1;            /*!< [6..6] Add Request                                                        */
      __IOM uint32_t AR7        : 1;            /*!< [7..7] Add Request                                                        */
      __IOM uint32_t AR8        : 1;            /*!< [8..8] Add Request                                                        */
      __IOM uint32_t AR9        : 1;            /*!< [9..9] Add Request                                                        */
      __IOM uint32_t AR10       : 1;            /*!< [10..10] Add Request                                                      */
      __IOM uint32_t AR11       : 1;            /*!< [11..11] Add Request                                                      */
      __IOM uint32_t AR12       : 1;            /*!< [12..12] Add Request                                                      */
      __IOM uint32_t AR13       : 1;            /*!< [13..13] Add Request                                                      */
      __IOM uint32_t AR14       : 1;            /*!< [14..14] Add Request                                                      */
      __IOM uint32_t AR15       : 1;            /*!< [15..15] Add Request                                                      */
      __IOM uint32_t AR16       : 1;            /*!< [16..16] Add Request                                                      */
      __IOM uint32_t AR17       : 1;            /*!< [17..17] Add Request                                                      */
      __IOM uint32_t AR18       : 1;            /*!< [18..18] Add Request                                                      */
      __IOM uint32_t AR19       : 1;            /*!< [19..19] Add Request                                                      */
      __IOM uint32_t AR20       : 1;            /*!< [20..20] Add Request                                                      */
      __IOM uint32_t AR21       : 1;            /*!< [21..21] Add Request                                                      */
      __IOM uint32_t AR22       : 1;            /*!< [22..22] Add Request                                                      */
      __IOM uint32_t AR23       : 1;            /*!< [23..23] Add Request                                                      */
      __IOM uint32_t AR24       : 1;            /*!< [24..24] Add Request                                                      */
      __IOM uint32_t AR25       : 1;            /*!< [25..25] Add Request                                                      */
      __IOM uint32_t AR26       : 1;            /*!< [26..26] Add Request                                                      */
      __IOM uint32_t AR27       : 1;            /*!< [27..27] Add Request                                                      */
      __IOM uint32_t AR28       : 1;            /*!< [28..28] Add Request                                                      */
      __IOM uint32_t AR29       : 1;            /*!< [29..29] Add Request                                                      */
      __IOM uint32_t AR30       : 1;            /*!< [30..30] Add Request                                                      */
      __IOM uint32_t AR31       : 1;            /*!< [31..31] Add Request                                                      */
    } bit;
  } TXBAR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000D4) Tx Buffer Cancellation Request                             */
    
    struct {
      __IOM uint32_t CR0        : 1;            /*!< [0..0] Cancellation Request                                               */
      __IOM uint32_t CR1        : 1;            /*!< [1..1] Cancellation Request                                               */
      __IOM uint32_t CR2        : 1;            /*!< [2..2] Cancellation Request                                               */
      __IOM uint32_t CR3        : 1;            /*!< [3..3] Cancellation Request                                               */
      __IOM uint32_t CR4        : 1;            /*!< [4..4] Cancellation Request                                               */
      __IOM uint32_t CR5        : 1;            /*!< [5..5] Cancellation Request                                               */
      __IOM uint32_t CR6        : 1;            /*!< [6..6] Cancellation Request                                               */
      __IOM uint32_t CR7        : 1;            /*!< [7..7] Cancellation Request                                               */
      __IOM uint32_t CR8        : 1;            /*!< [8..8] Cancellation Request                                               */
      __IOM uint32_t CR9        : 1;            /*!< [9..9] Cancellation Request                                               */
      __IOM uint32_t CR10       : 1;            /*!< [10..10] Cancellation Request                                             */
      __IOM uint32_t CR11       : 1;            /*!< [11..11] Cancellation Request                                             */
      __IOM uint32_t CR12       : 1;            /*!< [12..12] Cancellation Request                                             */
      __IOM uint32_t CR13       : 1;            /*!< [13..13] Cancellation Request                                             */
      __IOM uint32_t CR14       : 1;            /*!< [14..14] Cancellation Request                                             */
      __IOM uint32_t CR15       : 1;            /*!< [15..15] Cancellation Request                                             */
      __IOM uint32_t CR16       : 1;            /*!< [16..16] Cancellation Request                                             */
      __IOM uint32_t CR17       : 1;            /*!< [17..17] Cancellation Request                                             */
      __IOM uint32_t CR18       : 1;            /*!< [18..18] Cancellation Request                                             */
      __IOM uint32_t CR19       : 1;            /*!< [19..19] Cancellation Request                                             */
      __IOM uint32_t CR20       : 1;            /*!< [20..20] Cancellation Request                                             */
      __IOM uint32_t CR21       : 1;            /*!< [21..21] Cancellation Request                                             */
      __IOM uint32_t CR22       : 1;            /*!< [22..22] Cancellation Request                                             */
      __IOM uint32_t CR23       : 1;            /*!< [23..23] Cancellation Request                                             */
      __IOM uint32_t CR24       : 1;            /*!< [24..24] Cancellation Request                                             */
      __IOM uint32_t CR25       : 1;            /*!< [25..25] Cancellation Request                                             */
      __IOM uint32_t CR26       : 1;            /*!< [26..26] Cancellation Request                                             */
      __IOM uint32_t CR27       : 1;            /*!< [27..27] Cancellation Request                                             */
      __IOM uint32_t CR28       : 1;            /*!< [28..28] Cancellation Request                                             */
      __IOM uint32_t CR29       : 1;            /*!< [29..29] Cancellation Request                                             */
      __IOM uint32_t CR30       : 1;            /*!< [30..30] Cancellation Request                                             */
      __IOM uint32_t CR31       : 1;            /*!< [31..31] Cancellation Request                                             */
    } bit;
  } TXBCR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000D8) Tx Buffer Transmission Occurred                            */
    
    struct {
      __IM  uint32_t TO0        : 1;            /*!< [0..0] Transmission Occurred                                              */
      __IM  uint32_t TO1        : 1;            /*!< [1..1] Transmission Occurred                                              */
      __IM  uint32_t TO2        : 1;            /*!< [2..2] Transmission Occurred                                              */
      __IM  uint32_t TO3        : 1;            /*!< [3..3] Transmission Occurred                                              */
      __IM  uint32_t TO4        : 1;            /*!< [4..4] Transmission Occurred                                              */
      __IM  uint32_t TO5        : 1;            /*!< [5..5] Transmission Occurred                                              */
      __IM  uint32_t TO6        : 1;            /*!< [6..6] Transmission Occurred                                              */
      __IM  uint32_t TO7        : 1;            /*!< [7..7] Transmission Occurred                                              */
      __IM  uint32_t TO8        : 1;            /*!< [8..8] Transmission Occurred                                              */
      __IM  uint32_t TO9        : 1;            /*!< [9..9] Transmission Occurred                                              */
      __IM  uint32_t TO10       : 1;            /*!< [10..10] Transmission Occurred                                            */
      __IM  uint32_t TO11       : 1;            /*!< [11..11] Transmission Occurred                                            */
      __IM  uint32_t TO12       : 1;            /*!< [12..12] Transmission Occurred                                            */
      __IM  uint32_t TO13       : 1;            /*!< [13..13] Transmission Occurred                                            */
      __IM  uint32_t TO14       : 1;            /*!< [14..14] Transmission Occurred                                            */
      __IM  uint32_t TO15       : 1;            /*!< [15..15] Transmission Occurred                                            */
      __IM  uint32_t TO16       : 1;            /*!< [16..16] Transmission Occurred                                            */
      __IM  uint32_t TO17       : 1;            /*!< [17..17] Transmission Occurred                                            */
      __IM  uint32_t TO18       : 1;            /*!< [18..18] Transmission Occurred                                            */
      __IM  uint32_t TO19       : 1;            /*!< [19..19] Transmission Occurred                                            */
      __IM  uint32_t TO20       : 1;            /*!< [20..20] Transmission Occurred                                            */
      __IM  uint32_t TO21       : 1;            /*!< [21..21] Transmission Occurred                                            */
      __IM  uint32_t TO22       : 1;            /*!< [22..22] Transmission Occurred                                            */
      __IM  uint32_t TO23       : 1;            /*!< [23..23] Transmission Occurred                                            */
      __IM  uint32_t TO24       : 1;            /*!< [24..24] Transmission Occurred                                            */
      __IM  uint32_t TO25       : 1;            /*!< [25..25] Transmission Occurred                                            */
      __IM  uint32_t TO26       : 1;            /*!< [26..26] Transmission Occurred                                            */
      __IM  uint32_t TO27       : 1;            /*!< [27..27] Transmission Occurred                                            */
      __IM  uint32_t TO28       : 1;            /*!< [28..28] Transmission Occurred                                            */
      __IM  uint32_t TO29       : 1;            /*!< [29..29] Transmission Occurred                                            */
      __IM  uint32_t TO30       : 1;            /*!< [30..30] Transmission Occurred                                            */
      __IM  uint32_t TO31       : 1;            /*!< [31..31] Transmission Occurred                                            */
    } bit;
  } TXBTO;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000DC) Tx Buffer Cancellation Finished                            */
    
    struct {
      __IM  uint32_t CF0        : 1;            /*!< [0..0] Cancellation Finished                                              */
      __IM  uint32_t CF1        : 1;            /*!< [1..1] Cancellation Finished                                              */
      __IM  uint32_t CF2        : 1;            /*!< [2..2] Cancellation Finished                                              */
      __IM  uint32_t CF3        : 1;            /*!< [3..3] Cancellation Finished                                              */
      __IM  uint32_t CF4        : 1;            /*!< [4..4] Cancellation Finished                                              */
      __IM  uint32_t CF5        : 1;            /*!< [5..5] Cancellation Finished                                              */
      __IM  uint32_t CF6        : 1;            /*!< [6..6] Cancellation Finished                                              */
      __IM  uint32_t CF7        : 1;            /*!< [7..7] Cancellation Finished                                              */
      __IM  uint32_t CF8        : 1;            /*!< [8..8] Cancellation Finished                                              */
      __IM  uint32_t CF9        : 1;            /*!< [9..9] Cancellation Finished                                              */
      __IM  uint32_t CF10       : 1;            /*!< [10..10] Cancellation Finished                                            */
      __IM  uint32_t CF11       : 1;            /*!< [11..11] Cancellation Finished                                            */
      __IM  uint32_t CF12       : 1;            /*!< [12..12] Cancellation Finished                                            */
      __IM  uint32_t CF13       : 1;            /*!< [13..13] Cancellation Finished                                            */
      __IM  uint32_t CF14       : 1;            /*!< [14..14] Cancellation Finished                                            */
      __IM  uint32_t CF15       : 1;            /*!< [15..15] Cancellation Finished                                            */
      __IM  uint32_t CF16       : 1;            /*!< [16..16] Cancellation Finished                                            */
      __IM  uint32_t CF17       : 1;            /*!< [17..17] Cancellation Finished                                            */
      __IM  uint32_t CF18       : 1;            /*!< [18..18] Cancellation Finished                                            */
      __IM  uint32_t CF19       : 1;            /*!< [19..19] Cancellation Finished                                            */
      __IM  uint32_t CF20       : 1;            /*!< [20..20] Cancellation Finished                                            */
      __IM  uint32_t CF21       : 1;            /*!< [21..21] Cancellation Finished                                            */
      __IM  uint32_t CF22       : 1;            /*!< [22..22] Cancellation Finished                                            */
      __IM  uint32_t CF23       : 1;            /*!< [23..23] Cancellation Finished                                            */
      __IM  uint32_t CF24       : 1;            /*!< [24..24] Cancellation Finished                                            */
      __IM  uint32_t CF25       : 1;            /*!< [25..25] Cancellation Finished                                            */
      __IM  uint32_t CF26       : 1;            /*!< [26..26] Cancellation Finished                                            */
      __IM  uint32_t CF27       : 1;            /*!< [27..27] Cancellation Finished                                            */
      __IM  uint32_t CF28       : 1;            /*!< [28..28] Cancellation Finished                                            */
      __IM  uint32_t CF29       : 1;            /*!< [29..29] Cancellation Finished                                            */
      __IM  uint32_t CF30       : 1;            /*!< [30..30] Cancellation Finished                                            */
      __IM  uint32_t CF31       : 1;            /*!< [31..31] Cancellation Finished                                            */
    } bit;
  } TXBCF;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000E0) Tx Buffer Transmission Interrupt Enable                    */
    
    struct {
      __IM  uint32_t TIE0       : 1;            /*!< [0..0] Transmission Interrupt Enable                                      */
      __IM  uint32_t TIE1       : 1;            /*!< [1..1] Transmission Interrupt Enable                                      */
      __IM  uint32_t TIE2       : 1;            /*!< [2..2] Transmission Interrupt Enable                                      */
      __IM  uint32_t TIE3       : 1;            /*!< [3..3] Transmission Interrupt Enable                                      */
      __IM  uint32_t TIE4       : 1;            /*!< [4..4] Transmission Interrupt Enable                                      */
      __IM  uint32_t TIE5       : 1;            /*!< [5..5] Transmission Interrupt Enable                                      */
      __IM  uint32_t TIE6       : 1;            /*!< [6..6] Transmission Interrupt Enable                                      */
      __IM  uint32_t TIE7       : 1;            /*!< [7..7] Transmission Interrupt Enable                                      */
      __IM  uint32_t TIE8       : 1;            /*!< [8..8] Transmission Interrupt Enable                                      */
      __IM  uint32_t TIE9       : 1;            /*!< [9..9] Transmission Interrupt Enable                                      */
      __IM  uint32_t TIE10      : 1;            /*!< [10..10] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE11      : 1;            /*!< [11..11] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE12      : 1;            /*!< [12..12] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE13      : 1;            /*!< [13..13] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE14      : 1;            /*!< [14..14] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE15      : 1;            /*!< [15..15] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE16      : 1;            /*!< [16..16] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE17      : 1;            /*!< [17..17] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE18      : 1;            /*!< [18..18] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE19      : 1;            /*!< [19..19] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE20      : 1;            /*!< [20..20] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE21      : 1;            /*!< [21..21] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE22      : 1;            /*!< [22..22] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE23      : 1;            /*!< [23..23] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE24      : 1;            /*!< [24..24] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE25      : 1;            /*!< [25..25] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE26      : 1;            /*!< [26..26] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE27      : 1;            /*!< [27..27] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE28      : 1;            /*!< [28..28] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE29      : 1;            /*!< [29..29] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE30      : 1;            /*!< [30..30] Transmission Interrupt Enable                                    */
      __IM  uint32_t TIE31      : 1;            /*!< [31..31] Transmission Interrupt Enable                                    */
    } bit;
  } TXBTIE;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000E4) Tx Buffer Cancellation Finished Interrupt Enable           */
    
    struct {
      __IM  uint32_t CFIE0      : 1;            /*!< [0..0] Cancellation Finished Interrupt Enable                             */
      __IM  uint32_t CFIE1      : 1;            /*!< [1..1] Cancellation Finished Interrupt Enable                             */
      __IM  uint32_t CFIE2      : 1;            /*!< [2..2] Cancellation Finished Interrupt Enable                             */
      __IM  uint32_t CFIE3      : 1;            /*!< [3..3] Cancellation Finished Interrupt Enable                             */
      __IM  uint32_t CFIE4      : 1;            /*!< [4..4] Cancellation Finished Interrupt Enable                             */
      __IM  uint32_t CFIE5      : 1;            /*!< [5..5] Cancellation Finished Interrupt Enable                             */
      __IM  uint32_t CFIE6      : 1;            /*!< [6..6] Cancellation Finished Interrupt Enable                             */
      __IM  uint32_t CFIE7      : 1;            /*!< [7..7] Cancellation Finished Interrupt Enable                             */
      __IM  uint32_t CFIE8      : 1;            /*!< [8..8] Cancellation Finished Interrupt Enable                             */
      __IM  uint32_t CFIE9      : 1;            /*!< [9..9] Cancellation Finished Interrupt Enable                             */
      __IM  uint32_t CFIE10     : 1;            /*!< [10..10] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE11     : 1;            /*!< [11..11] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE12     : 1;            /*!< [12..12] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE13     : 1;            /*!< [13..13] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE14     : 1;            /*!< [14..14] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE15     : 1;            /*!< [15..15] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE16     : 1;            /*!< [16..16] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE17     : 1;            /*!< [17..17] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE18     : 1;            /*!< [18..18] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE19     : 1;            /*!< [19..19] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE20     : 1;            /*!< [20..20] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE21     : 1;            /*!< [21..21] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE22     : 1;            /*!< [22..22] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE23     : 1;            /*!< [23..23] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE24     : 1;            /*!< [24..24] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE25     : 1;            /*!< [25..25] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE26     : 1;            /*!< [26..26] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE27     : 1;            /*!< [27..27] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE28     : 1;            /*!< [28..28] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE29     : 1;            /*!< [29..29] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE30     : 1;            /*!< [30..30] Cancellation Finished Interrupt Enable                           */
      __IM  uint32_t CFIE31     : 1;            /*!< [31..31] Cancellation Finished Interrupt Enable                           */
    } bit;
  } TXBCIE;
  __IM  uint32_t  RESERVED5[2];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000F0) Tx Event FIFO Configuration                                */
    
    struct {
            uint32_t            : 2;
      __IOM uint32_t EFSA       : 14;           /*!< [15..2] Event FIFO Start Address                                          */
      __IOM uint32_t EFS        : 6;            /*!< [21..16] Event FIFO Size0 = Tx Event FIFO disabled1-32 = Number
                                                     of Tx Event FlFO elements>32 = Values greater than 32 are
                                                     interpreted as 32                                                         */
            uint32_t            : 2;
      __IOM uint32_t EFWM       : 6;            /*!< [29..24] Event FIFO Watermark0 = Watermark interrupt disabled1-32
                                                     = Level for Tx Event FIFO watermark interrupt (IR. TEF
                                                     W)>32 = Watermark interrupt disabled                                      */
            uint32_t            : 2;
    } bit;
  } TXEFC;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000F4) Tx Event FIFO Status                                       */
    
    struct {
      __IM  uint32_t EFFL       : 6;            /*!< [5..0] Event FIFO Fill Level                                              */
            uint32_t            : 2;
      __IM  uint32_t EFGI       : 5;            /*!< [12..8] Event FIFO Get Index                                              */
            uint32_t            : 3;
      __IM  uint32_t EFPI       : 5;            /*!< [20..16] Event FIFO Put Index                                             */
            uint32_t            : 3;
      __IM  uint32_t EFF        : 1;            /*!< [24..24] Event FIFO Ful0 = Tx Event FIF O not ful1 = Tx Event
                                                     FIF O full                                                                */
      __IM  uint32_t TEFL       : 1;            /*!< [25..25] Tx Event FIFO Element Lost0 = No Tx Event FIFO element
                                                     lost1 = Tx Event FlFO element lost, also set after write
                                                     attempt to Tx Event FlFO of size zero.                                    */
            uint32_t            : 6;
    } bit;
  } TXEFS;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x000000F8) Tx Event FIFO Acknowledge                                  */
    
    struct {
      __IOM uint32_t EFAI       : 5;            /*!< [4..0] Event FIFO Acknowledge Index                                       */
            uint32_t            : 27;
    } bit;
  } TXEFA;
} CAN_Type;                                     /*!< Size = 252 (0xfc)                                                         */



/* =========================================================================================================================== */
/* ================                                            RCC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief RCC (RCC)
  */

typedef struct {                                /*!< (@ 0x40003000) RCC Structure                                              */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) CLK_DIV                                                    */
    
    struct {
      __IOM uint32_t CLK_DIV_FACTOR : 4;        /*!< [3..0] clock divider factor                                               */
      __OM  uint32_t CLK_DIV_UP : 1;            /*!< [4..4] Writting 1 to makeing CLK_DIV Update.                              */
      __IOM uint32_t CLKSEL     : 2;            /*!< [6..5] CLKSEL                                                             */
            uint32_t            : 1;
      __IOM uint32_t PCLK_DIV   : 2;            /*!< [9..8] PCLK_DIV                                                           */
            uint32_t            : 2;
      __OM  uint32_t PCLK_DIV_UP : 1;           /*!< [12..12] Writting 1 to this bit makes the PCLK_DIV update.                */
      __IOM uint32_t CSS_EN     : 1;            /*!< [13..13] Clock Safely State check function ctrl. Writting 1
                                                     to enable, 0 to disable.                                                  */
      __IM  uint32_t CSS_FLAG   : 1;            /*!< [14..14] Clock fail status, 1 for fail, 0 for not fail.                   */
            uint32_t            : 17;
    } bit;
  } CLK_DIV;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) CLK_GATE_APB                                               */
    
    struct {
            uint32_t            : 1;
      __IOM uint32_t CLK_EN_UART0 : 1;          /*!< [1..1] clock enable of pclk_uart01'b1: Enable 1'b0: Disable               */
      __IOM uint32_t CLK_EN_TIM2 : 1;           /*!< [2..2] clock enable of pclk_tim21'b1: Enable 1'b0: Disable                */
      __IOM uint32_t CLK_EN_TIM1 : 1;           /*!< [3..3] clock enable of pclk_tim11'b1: Enable 1'b0: Disable                */
      __IOM uint32_t CLK_EN_TIM0 : 1;           /*!< [4..4] clock enable of pclk_tim01'b1: Enable 1'b0: Disable                */
      __IOM uint32_t CLK_EN_SYSCTRL : 1;        /*!< [5..5] clock enable of pclk_sysctrl1'b1: Enable 1'b0: Disable             */
            uint32_t            : 1;
      __IOM uint32_t CLK_EN_ADC0 : 1;           /*!< [7..7] clock enable of pclk_adc01'b1: Enable 1'b0: Disable                */
      __IOM uint32_t CLK_EN_ADC1 : 1;           /*!< [8..8] clock enable of pclk_adc11'b1: Enable 1'b0: Disable                */
      __IOM uint32_t CLK_EN_SPI0 : 1;           /*!< [9..9] clock enable of pclk_adc11'b1: Enable 1'b0: Disable                */
      __IOM uint32_t CLK_EN_SPI1 : 1;           /*!< [10..10] clock enable of pclk_spi01'b1: Enable 1'b0: Disable              */
      __IOM uint32_t CLK_EN_EPWM : 1;           /*!< [11..11] clock enable of pclk_epwm1'b1: Enable 1'b0: Disable              */
      __IOM uint32_t CLK_EN_ECAP : 1;           /*!< [12..12] clock enable of pclk_ecap1'b1: Enable 1'b0: Disable              */
      __IOM uint32_t CLK_EN_EDIAG : 1;          /*!< [13..13] clock enable of pclk_ediag1'b1: Enable 1'b0: Disable             */
            uint32_t            : 1;
      __IOM uint32_t CLK_EN_CAN : 1;            /*!< [15..15] clock enable of pclk_can1'b1: Enable 1'b0: Disable               */
      __IOM uint32_t CLK_EN_IWDG : 1;           /*!< [16..16] clock enable of pclk_iwdg1'b1: Enable 1'b0: Disable              */
      __IOM uint32_t CLK_EN_DFLASH : 1;         /*!< [17..17] clock enable of pclk_dflash1'b1: Enable 1'b0: Disable            */
            uint32_t            : 14;
    } bit;
  } CLK_GATE_APB;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) CLK_GATE_AHB                                               */
    
    struct {
      __IOM uint32_t CLK_EN_GPIO : 1;           /*!< [0..0] clock enable of hclk_gpio1'b1: Enable 1'b0: Disable                */
      __IOM uint32_t CLK_EN_DMA : 1;            /*!< [1..1] clock enable of hclk_dma1'b1: Enable 1'b0: Disable                 */
      __IOM uint32_t CLK_EN_ESCI : 1;           /*!< [2..2] clock enable of hclk_eSCI1'b1: Enable 1'b0: Disable                */
            uint32_t            : 29;
    } bit;
  } CLK_GATE_AHB;
  __IM  uint32_t  RESERVED1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000014) SYSTEM_SOFTWARE_RESET                                      */
    
    struct {
      __IOM uint32_t SYS_SW_RST : 1;            /*!< [0..0] System software reset, works only after that SYS_SW_RST_EN
                                                     was wrote 0x5A.1'b1: Reset 1'b0: Release reset                            */
            uint32_t            : 23;
      __OM  uint32_t SYS_SW_RST_EN : 8;         /*!< [31..24] System software reset protection bit.Writting 0x5A
                                                     to SYS_SW_RST_EN to make sys_sw_rst work1'b1: enable, 1'b0:
                                                     disable                                                                   */
    } bit;
  } SYSTEM_SOFTWARE_RESET;
  __IM  uint32_t  RESERVED2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) MODULE_SW_RESET_APB                                        */
    
    struct {
      __IOM uint32_t sw_rst_wwdg : 1;           /*!< [0..0] software reset of prstn_wwdg1'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_UART0 : 1;          /*!< [1..1] software reset of prstn_uart01'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_TIM2 : 1;           /*!< [2..2] software reset of prstn_tim2, reserved1'b1: Reset 1'b0:
                                                     Release reset                                                             */
      __IOM uint32_t SW_RST_TIM1 : 1;           /*!< [3..3] software reset of prstn_tim11'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_TIM0 : 1;           /*!< [4..4] software reset of prstn_tim01'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_SYSCTRL : 1;        /*!< [5..5] software reset of prstn_sysctrl1'b1: Reset 1'b0: Release
                                                     reset                                                                     */
            uint32_t            : 1;
      __IOM uint32_t SW_RST_ADC0 : 1;           /*!< [7..7] software reset of prstn_adc01'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_ADC1 : 1;           /*!< [8..8] software reset of prstn_adc11'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_SPI0 : 1;           /*!< [9..9] software reset of prstn_spi01'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_SPI1 : 1;           /*!< [10..10] software reset of prstn_spi11'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_EPWM : 1;           /*!< [11..11] software reset of prstn_epwm1'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_ECAP : 1;           /*!< [12..12] software reset of prstn_ecap1'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_EDIAG : 1;          /*!< [13..13] software reset of prstn_ediag1'b1: Reset 1'b0: Release
                                                     reset                                                                     */
            uint32_t            : 1;
      __IOM uint32_t SW_RST_CAN0 : 1;           /*!< [15..15] software reset of prstn_can01'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_IWDG : 1;           /*!< [16..16] software reset of prstn_iwdg1'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_DFLASH : 1;         /*!< [17..17] software reset of prstn_dflash1'b1: Reset 1'b0: Release
                                                     reset                                                                     */
            uint32_t            : 14;
    } bit;
  } MODULE_SW_RESET_APB;
  __IM  uint32_t  RESERVED3;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000024) MODULE_SW_RESET_AHB                                        */
    
    struct {
      __IOM uint32_t SW_RST_GPIO : 1;           /*!< [0..0] software reset of hrstn_gpio1'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_DMA : 1;            /*!< [1..1] software reset of hrstn_dma1'b1: Reset 1'b0: Release
                                                     reset                                                                     */
      __IOM uint32_t SW_RST_ESCI : 1;           /*!< [2..2] software reset of hrstn_eSCI1'b1: Reset 1'b0: Release
                                                     reset                                                                     */
            uint32_t            : 29;
    } bit;
  } MODULE_SW_RESET_AHB;
  __IM  uint32_t  RESERVED4[6];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000040) PLL_CFG1                                                   */
    
    struct {
      __IOM uint32_t PLL_EN     : 1;            /*!< [0..0] PLL enable 1'b1: Enable 1'b0: Disable                              */
      __IM  uint32_t PLL_STABLE : 1;            /*!< [1..1] PLL STABLE FLAG1'b1:PLL STABLE 1'b0:PLL NOT STABLE                 */
      __IOM uint32_t PLL_REF_SEL : 1;           /*!< [2..2] PLL reference clock selection : 0 for cystal, 1 for ROSC48MHz      */
            uint32_t            : 1;
      __IOM uint32_t PLL_POSTDIV : 2;           /*!< [5..4] output clock divider setting of VCO, F_out=Fvco/(2^PLL_POSTDIV)    */
            uint32_t            : 2;
      __IOM uint32_t PLL_PREDIV : 2;            /*!< [9..8] Prediv factor , input clock pre-divider setting, Fpfd=F_input/(2^PLL_PR
                                                     DIV)                                                                      */
            uint32_t            : 6;
      __IOM uint32_t PLL_LOOPDIV : 8;           /*!< [23..16] PLL loop divider setting                                         */
            uint32_t            : 6;
      __IOM uint32_t PLL_REF_DIV : 2;           /*!< [31..30] Div factor of ROSC48MHz as PLL reference clock                   */
    } bit;
  } PLL_CFG1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000044) PLL_CFG2                                                   */
    
    struct {
      __IOM uint32_t PLL_LPF_C  : 1;            /*!< [0..0] PLL LPF C setting:0:1.2pF1:2.3pF                                   */
      __IOM uint32_t PLL_LPF_RSEL : 3;          /*!< [3..1] PLL LPF R setting:000:5K(default)001:8K010:13K011:18K100:23K101:31.4K11
                                                     :41.4K111:51.4K                                                           */
            uint32_t            : 4;
      __IOM uint32_t PLL_KVCO   : 1;            /*!< [8..8] PLL CCO KVCO setting:0:300MHz/V1:400MHz/V                          */
      __IOM uint32_t PLL_CCOBAND : 1;           /*!< [9..9] PLL CCO Band setting, Vctl from 0.6V to 2V:0:400MHz band1:700MHz-
                                                     band                                                                      */
      __IOM uint32_t PLL_ICP    : 4;            /*!< [13..10] PLL charge pump current setting                                  */
            uint32_t            : 2;
      __IOM uint32_t PLL_CKUSABLE_DIVSEL : 10;  /*!< [25..16] PLL_CKUSABLE_DIVSEL sets the cycle number to wait before
                                                     VCO can output steady CK_OUT. output clock stable time:Tstale=1/Fpfd
                                                     * code                                                                    */
            uint32_t            : 2;
      __IOM uint32_t PLL_LDOVREFSEL : 3;        /*!< [30..28] PLL LDO vref setting                                             */
            uint32_t            : 1;
    } bit;
  } PLL_CFG2;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000048) PLL_DBG                                                    */
    
    struct {
      __IOM uint32_t PLL_DIG_DBG : 3;           /*!< [2..0] Digital signal DBG out select: 3'b000: powl (internal
                                                     Power on signal)001: copy of ck usable signal010: copy
                                                     of PLL's output clock011: copy of loop frequency divider's
                                                     output clock100: copy of input fre divider's output clock101:
                                                     copy of input crystal's clock110: PLL_EN signal111: 1.5V
                                                     copy of ISO_EN signal                                                     */
            uint32_t            : 13;
      __IOM uint32_t PLL_ANA_DBG : 3;           /*!< [18..16] Analog signal DBG out select: 3'b000: copy of loop
                                                     frequency divider's output clock001: copy of PLL's output
                                                     clock 010: PLL_EN signal011: copy of ck usable signal100:
                                                     powl (internal Power on signal)101: CP's mirrored Vctl
                                                     voltage (Internal op-amp's output voltage)110: CP's output
                                                     voltage111: 2.8V LDO's output voltage                                     */
            uint32_t            : 12;
      __IM  uint32_t PLL_DBG_OUT : 1;           /*!< [31..31] PLL debug out signal                                             */
    } bit;
  } PLL_DBG;
  __IM  uint32_t  RESERVED5[5];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000060) CIR                                                        */
    
    struct {
      __IOM uint32_t PLL_IE     : 1;            /*!< [0..0] PLL interrupt enable1'b1:PLL interrupt enable 1'b0:PLL
                                                     interrupt not enable                                                      */
            uint32_t            : 7;
      __IM  uint32_t PLL_STABLT_INT_FLAG : 1;   /*!< [8..8] PLL stable interrupt flag 1'b1:PLL interrupt enable 1'b0:PLL
                                                     interrupt not enable                                                      */
            uint32_t            : 7;
      __OM  uint32_t PLL_STABLT_INT_CLR : 1;    /*!< [16..16] Writting 1 to clear pll stable interrupt. Reading has
                                                     no effect.                                                                */
            uint32_t            : 15;
    } bit;
  } CIR;
  __IM  uint32_t  RESERVED6[3];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000070) EXTAL_CFG                                                  */
    
    struct {
      __IOM uint32_t IN_EN      : 1;            /*!< [0..0] Extal input enable                                                 */
      __IOM uint32_t OUT_EN     : 1;            /*!< [1..1] Extal output enable                                                */
            uint32_t            : 14;
      __OM  uint32_t STG        : 3;            /*!< [18..16] STG                                                              */
            uint32_t            : 13;
    } bit;
  } EXTAL_CFG;
  __IM  uint32_t  RESERVED7[37];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000108) RST_REASON                                                 */
    
    struct {
      __IM  uint32_t RST_REASON_STATUS : 4;     /*!< [3..0] Reason of the latest reset:4'b0001: power on reset4'b0010:
                                                     watch dog reset4'b0011: system software reset4'b0100: cm0
                                                     reset4'b0111: over temperature reset by ADC4'b1000: ldo50
                                                     over voltage reset4'b1001: ldo50 under voltage reset4'b1010:
                                                     ldo15 over voltage reset4'b1011: ldo15 under voltage reset4'b1100:
                                                     over temperature reset by BG4'b1101: iwdg reset                           */
            uint32_t            : 28;
    } bit;
  } RST_REASON;
  __IM  uint32_t  RESERVED8;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000110) LDO1P5_CFG                                                 */
    
    struct {
      __IOM uint32_t d2a_uv15_en : 1;           /*!< [0..0] 1.5V LDO under voltage enable, 1'b1: enable, 1'b0: disable         */
      __IOM uint32_t d2a_ov15_en : 1;           /*!< [1..1] 1.5V LDO over voltage enable, 1'b1: enable, 1'b0: disable          */
            uint32_t            : 2;
      __IOM uint32_t d2a_uv15_level : 3;        /*!< [6..4] Selects the reference level for UV15 comparator register
                                                     range:1.18V~1.65Vdefault:0x8, Vrise=1.35V, hys=50mV                       */
            uint32_t            : 1;
      __IOM uint32_t d2a_ov15_level : 3;        /*!< [10..8] Selects the reference level for OV15 comparator register
                                                     range:1.52V~1.82Vdefault:0x8, Vrise=1.65V, hys=50mV                       */
            uint32_t            : 21;
    } bit;
  } LDO1P5_CFG;
  __IM  uint32_t  RESERVED9;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000118) LDO5P0_CFG                                                 */
    
    struct {
      __IOM uint32_t d2a_uv50_en : 1;           /*!< [0..0] 5V LDO under voltage enable1'b1: enable, 1'b0: disable             */
      __IOM uint32_t d2a_ov50_en : 1;           /*!< [1..1] 5V LDO over voltage enable1'b1: enable, 1'b0: disable              */
      __IOM uint32_t d2a_en_test_avdd50_div : 1;/*!< [2..2] 5V LDO test/debug enable1'b1: enable, 1'b0: disable                */
            uint32_t            : 1;
      __IOM uint32_t d2a_uv50_level : 3;        /*!< [6..4] Selects the reference level for UV50 comparator register
                                                     range:3.6V~4.7Vdefault:0x8, Vrise=4V, hys=220mV                           */
            uint32_t            : 1;
      __IOM uint32_t d2a_ov50_level : 3;        /*!< [10..8] Selects the reference level for OV50 comparator register
                                                     range:5.2V~6.8Vdefault:0x8, Vrise=6V, hys=190mV                           */
            uint32_t            : 21;
    } bit;
  } LDO5P0_CFG;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000011C) BG_OTP_CFG                                                 */
    
    struct {
      __IOM uint32_t d2a_otp_en : 1;            /*!< [0..0] OTP enable1'b1: enable, 1'b0: disable                              */
      __IOM uint32_t d2a_bg_bf_en : 1;          /*!< [1..1] BG buffer enable1'b1: enable, 1'b0: disable                        */
            uint32_t            : 2;
      __IOM uint32_t d2a_otp_sel : 4;           /*!< [7..4] Over temperature protection. Select the OVP_TEMP threshold
                                                     level for the monitor.Default:OTP_SEL[3:0]=1000.Rising:
                                                     155.4 Falling: 136.4 HYS: 20                                              */
            uint32_t            : 24;
    } bit;
  } BG_OTP_CFG;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000120) VT_RST_ENABLE                                              */
    
    struct {
            uint32_t            : 2;
      __IOM uint32_t OV15_RST_EN : 1;           /*!< [2..2] 1.5VOV reset enable1'b1: enable, 1'b0: disable                     */
      __IOM uint32_t UV15_RST_EN : 1;           /*!< [3..3] 1.5VUV reset enable1'b1: enable, 1'b0: disable                     */
      __IOM uint32_t OTP_RST_EN : 1;            /*!< [4..4] ADC OTP reset enable1'b1: enable, 1'b0: disable                    */
      __IOM uint32_t OV50_RST_EN : 1;           /*!< [5..5] 5V over voltage reset enable1'b1: enable, 1'b0: disable            */
      __IOM uint32_t UV50_RST_EN : 1;           /*!< [6..6] 5V UV reset enable1'b1: enable, 1'b0: disable                      */
      __IOM uint32_t BG_OTP_RST_EN : 1;         /*!< [7..7] BG OTP reset enable1'b1: enable, 1'b0: disable                     */
      __IOM uint32_t LDO15OC_RST_EN : 1;        /*!< [8..8] LD15 over current reset enable1'b1: enable, 1'b0: disable          */
      __IOM uint32_t IWDG       : 1;            /*!< [9..9] IWDG reset enable1'b1: enable, 1'b0: disable                       */
            uint32_t            : 22;
    } bit;
  } VT_RST_ENABLE;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000124) INT_STATUS                                                 */
    
    struct {
            uint32_t            : 2;
      __IM  uint32_t OV15_LV    : 1;            /*!< [2..2] 1.5V over voltage interrupt status1'b1: interrupt, 1'b0:
                                                     no interrupt                                                              */
      __IM  uint32_t UV15_LV    : 1;            /*!< [3..3] 1.5V under voltage interrupt status1'b1: interrupt, 1'b0:
                                                     no interrupt                                                              */
            uint32_t            : 1;
      __IM  uint32_t OV50_LV    : 1;            /*!< [5..5] 5V over voltage interrupt status1'b1: interrupt, 1'b0:
                                                     no interrupt                                                              */
      __IM  uint32_t UV50_LV    : 1;            /*!< [6..6] 5V under voltage interrupt status1'b1: interrupt, 1'b0:
                                                     no interrupt                                                              */
      __IM  uint32_t BG_OTP_LV  : 1;            /*!< [7..7] BG OTP interrupt status1'b1: interrupt, 1'b0: no interrupt         */
      __IM  uint32_t LDO15OC_OTP_LV : 1;        /*!< [8..8] LD15 over current interrupt status1'b1: interrupt, 1'b0:
                                                     no interrupt                                                              */
            uint32_t            : 23;
    } bit;
  } INT_STATUS;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000128) INT_ENABLE                                                 */
    
    struct {
            uint32_t            : 2;
      __IOM uint32_t OV15_INT_EN : 1;           /*!< [2..2] 1.5V over voltage interrupt enable1'b1: enable, 1'b0:
                                                     disable                                                                   */
      __IOM uint32_t UV15_INT_EN : 1;           /*!< [3..3] 1.5V under voltage interrupt enable1'b1: enable, 1'b0:
                                                     disable                                                                   */
            uint32_t            : 1;
      __IOM uint32_t OV50_INT_EN : 1;           /*!< [5..5] 5V over voltage interrupt enable1'b1: enable, 1'b0: disable        */
      __IOM uint32_t UV50_INT_EN : 1;           /*!< [6..6] 5V under voltage interrupt enable1'b1: enable, 1'b0:
                                                     disable                                                                   */
      __IOM uint32_t BG_OTP_INT_EN : 1;         /*!< [7..7] BG OTP interrupt enable1'b1: enable, 1'b0: disable                 */
      __IOM uint32_t LDP15OC_INT_EN : 1;        /*!< [8..8] LDO15 over current interrupt status1'b1: interrupt, 1'b0:
                                                     no interrupt                                                              */
            uint32_t            : 23;
    } bit;
  } INT_ENABLE;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000012C) INT_CLEAR                                                  */
    
    struct {
            uint32_t            : 2;
      __OM  uint32_t OV15_INT_CLR : 1;          /*!< [2..2] Level interrupt, Writting 0 or 1 can not clear the interrupt
                                                     state.                                                                    */
      __OM  uint32_t UV15_INT_CLR : 1;          /*!< [3..3] Level interrupt, Writting 0 or 1 can not clear the interrupt
                                                     state.                                                                    */
            uint32_t            : 1;
      __OM  uint32_t OV50_INT_CLR : 1;          /*!< [5..5] Level interrupt, Writting 0 or 1 can not clear the interrupt
                                                     state.                                                                    */
      __OM  uint32_t UV50_INT_CLR : 1;          /*!< [6..6] Level interrupt, Writting 0 or 1 can not clear the interrupt
                                                     state.                                                                    */
      __OM  uint32_t BG_OTP_INT_CLR : 1;        /*!< [7..7] Level interrupt, Writting 0 or 1 can not clear the interrupt
                                                     state.                                                                    */
      __OM  uint32_t LDO15OC_INT_CLR : 1;       /*!< [8..8] Level interrupt, Writting 0 or 1 can not clear the interrupt
                                                     state.                                                                    */
            uint32_t            : 23;
    } bit;
  } INT_CLEAR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000130) BIAS_CFG                                                   */
    
    struct {
      __IOM uint32_t d2a_ibias_en : 1;          /*!< [0..0] When EN_IBIAS=1.5V, IBIAS is on.1'b1: enable, 1'b0: disable        */
            uint32_t            : 31;
    } bit;
  } BIAS_CFG;
  __IM  uint32_t  RESERVED10[19];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000180) CLK_MUX                                                    */
    
    struct {
      __IOM uint32_t osc_dbg_sel : 1;           /*!< [0..0] osc clock selection1'b0: output 16-dived-dbg_clk clock1'b1:
                                                     output always-on-256KHz clock                                             */
      __IOM uint32_t lin_baud_clk_sel : 1;      /*!< [1..1] lin baud clock selection1'b0: osc clock 48Mhz is selected1'b1:
                                                     system clock                                                              */
      __IOM uint32_t dbg_clk_sel : 2;           /*!< [3..2] 0 for ROSC48M,1 for PLL reference clock, 2 for extal,
                                                     3 for PLL output                                                          */
            uint32_t            : 12;
      __IOM uint32_t ADC_DIV    : 2;            /*!< [17..16] Div factor of ADC_CLK. 0                                         */
            uint32_t            : 2;
      __OM  uint32_t ADC_DIV_UP : 1;            /*!< [20..20] Writting 1 to makeing ADC_DIV Update.                            */
      __IOM uint32_t ADC_CLK_SEL : 1;           /*!< [21..21] 0 for 48MHz OSC, 1 for system clock                              */
            uint32_t            : 10;
    } bit;
  } CLK_MUX;
  __IM  uint32_t  RESERVED11[31];
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000200) SSC_CFG                                                    */
    
    struct {
      __IOM uint32_t ssc_mode   : 2;            /*!< [1..0] ssc_mode                                                           */
            uint32_t            : 1;
      __IOM uint32_t ssc_en     : 1;            /*!< [3..3] SSC control bit1'b1: enable, 1'b0: disable                         */
      __IOM uint32_t ssc_freq_step : 4;         /*!< [7..4] step of ssc frequency                                              */
      __IOM uint32_t ssc_freq_range : 4;        /*!< [11..8] range of ssc frequency                                            */
            uint32_t            : 4;
      __IOM uint32_t ssc_freq_stay : 7;         /*!< [22..16] Keeping time of each step                                        */
            uint32_t            : 9;
    } bit;
  } SSC_CFG;
} RCC_Type;                                     /*!< Size = 516 (0x204)                                                        */



/* =========================================================================================================================== */
/* ================                                           eDIAG                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief eDIAG (eDIAG)
  */

typedef struct {                                /*!< (@ 0x50004000) eDIAG Structure                                            */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) Status Register                                            */
    
    struct {
      __IM  uint32_t OUT_SYNC   : 1;            /*!< [0..0] Before digital filtering                                           */
      __IM  uint32_t OUT_VALID  : 1;            /*!< [1..1] After filtering                                                    */
      __IM  uint32_t W_OUT      : 1;            /*!< [2..2] Comparison output of phase W                                       */
      __IM  uint32_t V_OUT      : 1;            /*!< [3..3] Comparison output of phase V                                       */
      __IM  uint32_t U_OUT      : 1;            /*!< [4..4] Comparison output of phase U                                       */
            uint32_t            : 6;
      __IM  uint32_t OCD0_NEG_FILED : 1;        /*!< [11..11] OCD0_NEG_FILED                                                   */
      __IM  uint32_t OCD0_POS_FILED : 1;        /*!< [12..12] OCD0_POS_FILED                                                   */
      __IM  uint32_t OCD1_NEG_FILED : 1;        /*!< [13..13] OCD1_NEG_FILED                                                   */
      __IM  uint32_t OCD1_POS_FILED : 1;        /*!< [14..14] OCD1_POS_FILED                                                   */
      __IM  uint32_t LEVEL0_FILED : 1;          /*!< [15..15] LEVEL0_FILED(filtered)                                           */
      __IM  uint32_t LEVEL1_FILED : 1;          /*!< [16..16] LEVEL1_FILED(filtered)                                           */
      __IM  uint32_t UV15_FILED : 1;            /*!< [17..17] UV15_FILED(filtered)                                             */
      __IM  uint32_t OV15_FILED : 1;            /*!< [18..18] OV15_FILED(filtered)                                             */
      __IM  uint32_t UV50_FILED : 1;            /*!< [19..19] UV50_FILED(filtered)                                             */
      __IM  uint32_t OV50_FILED : 1;            /*!< [20..20] OV50_FILED(filtered)                                             */
      __IM  uint32_t OTP_FILED  : 1;            /*!< [21..21] OTP_FILED(filtered)                                              */
      __IM  uint32_t BRK_FILED  : 1;            /*!< [22..22] BRK IO_FILED(filtered)                                           */
            uint32_t            : 9;
    } bit;
  } STS;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) Control Register                                           */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] COMP enable                                                        */
      __IOM uint32_t MODE       : 1;            /*!< [1..1] COMP mode0b -Common mode1b - Window mode                           */
      __IOM uint32_t OUTSEL     : 1;            /*!< [2..2] Output Selection0b - COMP output to PIN directly without
                                                     filter1b - COMP output to PIN witn filter                                 */
      __IOM uint32_t EDGESEL    : 2;            /*!< [4..3] Edge Selection for interrupt00b - Disable01b - Select
                                                     positive edge10b - Select negative edge11b - Select positive
                                                     or negative edge                                                          */
      __IOM uint32_t OTEN       : 1;            /*!< [5..5] Output Trigger Enable                                              */
      __IOM uint32_t OTSEL      : 2;            /*!< [7..6] Output Trigger Selection 00b - COMP output as trigger01b
                                                     - COMP output positive edge as trigger10b - COMP output
                                                     negative edge as trigger11b - COMP output positive/negative
                                                     edge as trigger                                                           */
      __IOM uint32_t PGA0_OCD_EN : 1;           /*!< [8..8] Current sense0 detect enable                                       */
      __IOM uint32_t PGA1_OCD_EN : 1;           /*!< [9..9] Current sense1 detect enable                                       */
      __IOM uint32_t PGA0_OCD_TH : 2;           /*!< [11..10] OC0 threshold setting: 00: 2/20 AVDD01: 4/20 AVDD10:
                                                     5/20 AVDD11: 6/20 AVDD                                                    */
      __IOM uint32_t PGA1_OCD_TH : 2;           /*!< [13..12] OC1 threshold setting: 00: 2/20 AVDD01: 4/20 AVDD10:
                                                     5/20 AVDD11: 6/20 AVDD                                                    */
            uint32_t            : 2;
      __IOM uint32_t LPF        : 3;            /*!< [18..16] The selection of LPF setting: LPF_PHC LPF_PHU000: 141k
                                                     94k001: 282k 188k010: 564k 376k011: 1.129M 752k100: 2.258M
                                                     1.505M101: 4.516M 3.01M110: 9.033M 6.02M111: 18.066M 12.04M               */
      __IOM uint32_t HYS        : 2;            /*!< [20..19] COMP hysterisis setting: 00: 0mV01: 19mV: default10:
                                                     34mV11: 46mV                                                              */
      __IOM uint32_t OFFSET     : 1;            /*!< [21..21] COMP HSY mode: 1'b0: single side1'b1: double side default        */
      __IOM uint32_t SPEED      : 1;            /*!< [22..22] COMP speed mode setting: 1'b0: low speed mode1'b1:
                                                     high speed mode default                                                   */
            uint32_t            : 9;
    } bit;
  } CR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000008) Control1 Register                                          */
    
    struct {
      __IOM uint32_t OCD0_NEG_EN : 1;           /*!< [0..0] OCD0 NEG As the detection signal of eDIAG                          */
      __IOM uint32_t OCD0_POS_EN : 1;           /*!< [1..1] OCD0 POS As the detection signal of eDIAG                          */
      __IOM uint32_t OCD1_NEG_EN : 1;           /*!< [2..2] OCD1 NEG As the detection signal of eDIAG                          */
      __IOM uint32_t OCD1_POS_EN : 1;           /*!< [3..3] OCD1 POS As the detection signal of eDIAG                          */
      __IOM uint32_t LEVEL0_EN  : 1;            /*!< [4..4] LEVEL 0 As the detection signal of eDIAG                           */
      __IOM uint32_t LEVEL1_EN  : 1;            /*!< [5..5] LEVEL 1 As the detection signal of eDIAG                           */
      __IOM uint32_t UV15_EN    : 1;            /*!< [6..6] UV15 As the detection signal of eDIAG                              */
      __IOM uint32_t OV15_EN    : 1;            /*!< [7..7] OV15 As the detection signal of eDIAG                              */
      __IOM uint32_t UV50_EN    : 1;            /*!< [8..8] UV50 As the detection signal of eDIAG                              */
      __IOM uint32_t OV50_EN    : 1;            /*!< [9..9] OV50 As the detection signal of eDIAG                              */
      __IOM uint32_t OTP_EN     : 1;            /*!< [10..10] OTP As the detection signal of eDIAG                             */
      __IOM uint32_t ADC_OTP_EN : 1;            /*!< [11..11] ADC OTP As the detection signal of eDIAG                         */
      __IOM uint32_t BRK_IO_EN  : 1;            /*!< [12..12] BRK IO As the detection signal of eDIAG                          */
            uint32_t            : 7;
      __IOM uint32_t LEVEL0_POL : 1;            /*!< [20..20] LEVEL0 Polarity                                                  */
      __IOM uint32_t LEVEL1_POL : 1;            /*!< [21..21] LEVEL1 Polarity                                                  */
      __IOM uint32_t BRKIO_POL  : 1;            /*!< [22..22] Break IO Polarity                                                */
            uint32_t            : 9;
    } bit;
  } CR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) MUX Register                                               */
    
    struct {
      __IOM uint32_t PHSEL      : 2;            /*!< [1..0] Phase Selection00b - Phase U01b - Phase V10b - Phase
                                                     W11b - GPIO_phase                                                         */
            uint32_t            : 30;
    } bit;
  } MUX;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000010) Interrupt Enable Register                                  */
    
    struct {
      __IOM uint32_t IE         : 1;            /*!< [0..0] Comp Interrupt Enable                                              */
      __IOM uint32_t LEVE0E     : 1;            /*!< [1..1] LEVE 0 Interrupt Enable                                            */
      __IOM uint32_t LEVE1E     : 1;            /*!< [2..2] LEVE 1 Interrupt Enable                                            */
      __IOM uint32_t OCD0_NEGE  : 1;            /*!< [3..3] PGA 0 Over-current NEG Enable                                      */
      __IOM uint32_t OCD0_POSE  : 1;            /*!< [4..4] PGA 0 Over-current POS Enable                                      */
      __IOM uint32_t OCD1_NEGE  : 1;            /*!< [5..5] PGA 1 Over-current NEG Enable                                      */
      __IOM uint32_t OCD1_POSE  : 1;            /*!< [6..6] PGA 1 Over-current POS Enable                                      */
            uint32_t            : 25;
    } bit;
  } IER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000014) Interrupt Status Register                                  */
    
    struct {
      __IM  uint32_t PF         : 1;            /*!< [0..0] Positive Edge Flag                                                 */
      __IM  uint32_t NF         : 1;            /*!< [1..1] Negative Edge Flag                                                 */
      __IM  uint32_t LEVF0F     : 1;            /*!< [2..2] Level 0 Flag                                                       */
      __IM  uint32_t LEVF1F     : 1;            /*!< [3..3] Level 1 Flag                                                       */
      __IM  uint32_t OCD0_NEGF  : 1;            /*!< [4..4] PGA 0 Over-current NEG Flag                                        */
      __IM  uint32_t OCD0_POSF  : 1;            /*!< [5..5] PGA 0 Over-current POS Flag                                        */
      __IM  uint32_t OCD1_NEGF  : 1;            /*!< [6..6] PGA 1 Over-current NEG Flag                                        */
      __IM  uint32_t OCD1_POSF  : 1;            /*!< [7..7] PGA 1 Over-current POS Flag                                        */
            uint32_t            : 24;
    } bit;
  } SR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000018) Interrupt Status Clear Register                            */
    
    struct {
      __OM  uint32_t PFCLR      : 1;            /*!< [0..0] Interrupt clear bit. Write 1 Clear the interrupt status.           */
      __OM  uint32_t NFCLR      : 1;            /*!< [1..1] Interrupt clear bit. Write 1 Clear the interrupt status.           */
      __OM  uint32_t LEVF0CLR   : 1;            /*!< [2..2] Interrupt clear bit. Write 1 Clear the interrupt status.           */
      __OM  uint32_t LEVF1CLR   : 1;            /*!< [3..3] Interrupt clear bit. Write 1 Clear the interrupt status.           */
      __OM  uint32_t OCD0_NEGCLR : 1;           /*!< [4..4] Interrupt clear bit. Write 1 Clear the interrupt status.           */
      __OM  uint32_t OCD0_POSCLR : 1;           /*!< [5..5] Interrupt clear bit. Write 1 Clear the interrupt status.           */
      __OM  uint32_t OCD1_NEGCLR : 1;           /*!< [6..6] Interrupt clear bit. Write 1 Clear the interrupt status.           */
      __OM  uint32_t OCD1_POSCLR : 1;           /*!< [7..7] Interrupt clear bit. Write 1 Clear the interrupt status.           */
            uint32_t            : 24;
    } bit;
  } CLR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000001C) Filter Register                                            */
    
    struct {
      __IOM uint32_t FLTDIV     : 10;           /*!< [9..0] Filter clock divides the frequency                                 */
      __IOM uint32_t FLTWIN     : 5;            /*!< [14..10] Filter window of the filter                                      */
      __IOM uint32_t FLTTH      : 5;            /*!< [19..15] Output threshold of the filter                                   */
            uint32_t            : 12;
    } bit;
  } FILT;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000020) DIA Filter Register                                        */
    
    struct {
      __IOM uint32_t OCD_NEG_FILT_SEL : 3;      /*!< [2..0] Filter time select000:bypass001: 16 clock cycles010:
                                                     32 clock cycles011: 64 clock cycles100: 128 clock cycles101:
                                                     256 clock cycles110:512 clock cycles111: 910 clock cycles                 */
      __IOM uint32_t OCD_POS_FILT_SEL : 3;      /*!< [5..3] Filter time select000:bypass001: 16 clock cycles010:
                                                     32 clock cycles011: 64 clock cycles100: 128 clock cycles101:
                                                     256 clock cycles110:512 clock cycles111: 910 clock cycles                 */
      __IOM uint32_t LEVEL0_FILT_SEL : 3;       /*!< [8..6] Filter time select000:bypass001: 16 clock cycles010:
                                                     32 clock cycles011: 64 clock cycles100: 128 clock cycles101:
                                                     256 clock cycles110:512 clock cycles111: 910 clock cycles                 */
      __IOM uint32_t LEVEL1_FILT_SEL : 3;       /*!< [11..9] Filter time select000:bypass001: 16 clock cycles010:
                                                     32 clock cycles011: 64 clock cycles100: 128 clock cycles101:
                                                     256 clock cycles110:512 clock cycles111: 910 clock cycles                 */
      __IOM uint32_t UV15_FILT_SEL : 3;         /*!< [14..12] Filter time select000:bypass001: 16 clock cycles010:
                                                     32 clock cycles011: 64 clock cycles100: 128 clock cycles101:
                                                     256 clock cycles110:512 clock cycles111: 910 clock cycles                 */
      __IOM uint32_t OV15_FILT_SEL : 3;         /*!< [17..15] Filter time select000:bypass001: 16 clock cycles010:
                                                     32 clock cycles011: 64 clock cycles100: 128 clock cycles101:
                                                     256 clock cycles110:512 clock cycles111: 910 clock cycles                 */
      __IOM uint32_t UV50_FILT_SEL : 3;         /*!< [20..18] Filter time select000:bypass001: 16 clock cycles010:
                                                     32 clock cycles011: 64 clock cycles100: 128 clock cycles101:
                                                     256 clock cycles110:512 clock cycles111: 910 clock cycles                 */
      __IOM uint32_t OV50_FILT_SEL : 3;         /*!< [23..21] Filter time select000:bypass001: 16 clock cycles010:
                                                     32 clock cycles011: 64 clock cycles100: 128 clock cycles101:
                                                     256 clock cycles110:512 clock cycles111: 910 clock cycles                 */
      __IOM uint32_t OTP_FILT_SEL : 3;          /*!< [26..24] Filter time select000:bypass001: 16 clock cycles010:
                                                     32 clock cycles011: 64 clock cycles100: 128 clock cycles101:
                                                     256 clock cycles110:512 clock cycles111: 910 clock cycles                 */
      __IOM uint32_t BRK_FILT_SEL : 3;          /*!< [29..27] Filter time select000:bypass001: 16 clock cycles010:
                                                     32 clock cycles011: 64 clock cycles100: 128 clock cycles101:
                                                     256 clock cycles110:512 clock cycles111: 910 clock cycles                 */
            uint32_t            : 2;
    } bit;
  } FILT_DIA;
} eDIAG_Type;                                   /*!< Size = 36 (0x24)                                                          */



/* =========================================================================================================================== */
/* ================                                           ADC0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief ADC (ADC0)
  */

typedef struct {                                /*!< (@ 0x50000000) ADC0 Structure                                             */
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000000) Config0 Register                                           */
    
    struct {
      __IOM uint32_t ADEN       : 1;            /*!< [0..0] ADC enable0: ADC power off1: ADC power on                          */
      __IOM uint32_t DMAEN      : 1;            /*!< [1..1] DMA transfer enable0: disable1: enable                             */
      __IOM uint32_t CONT       : 1;            /*!< [2..2] Continuous conversion enable0: a single conversion1:
                                                     continuous conversion                                                     */
      __IOM uint32_t PGAEN      : 1;            /*!< [3..3] PGA enable0: PGA power off1: PGA power on                          */
      __IOM uint32_t SEQLENGTH  : 3;            /*!< [6..4] ADC sequence length, the max length is 8000: sequence
                                                     length equal 1001: sequence length equal 2010: sequence
                                                     length equal 3011: sequence length equal 4100: sequence
                                                     length equal 5101: sequence length equal 6110: sequence
                                                     length equal 7111: sequence length equal 8                                */
            uint32_t            : 1;
      __OM  uint32_t SW_TRIG    : 1;            /*!< [8..8] Write 1 to generate a ADC software trigger.                        */
            uint32_t            : 3;
      __IOM uint32_t TRIG_SEL   : 1;            /*!< [12..12] ADC trigger source select0: Software trigger1: Hardware
                                                     trigger from TRIGMUX                                                      */
      __IOM uint32_t PGA_SPD    : 2;            /*!< [14..13] PGA OP bias current select00: 16uA01: 20uA10: 25uA11:
                                                     33uA                                                                      */
            uint32_t            : 17;
    } bit;
  } CR0;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000004) Config1 Register                                           */
    
    struct {
            uint32_t            : 8;
      __IOM uint32_t TACTIVE    : 12;           /*!< [19..8] setting ADC stable time                                           */
            uint32_t            : 12;
    } bit;
  } CR1;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000008) Over Temperature Protect Register                          */
    
    struct {
      __IOM uint32_t OTPEN      : 1;            /*!< [0..0] Over Temperature Portect Enable0: disable1: enable                 */
            uint32_t            : 15;
      __IOM uint32_t TEMPMAX    : 13;           /*!< [28..16] Temperature alarm upper limit value                              */
            uint32_t            : 3;
    } bit;
  } OTP;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x0000000C) Status Register                                            */
    
    struct {
      __IM  uint32_t EOC        : 1;            /*!< [0..0] End of conversion                                                  */
      __IM  uint32_t TRIGERR    : 1;            /*!< [1..1] When ADC sequence sample is not end, another trigger
                                                     asking for sample will set this bit to 1.                                 */
      __IM  uint32_t OTP        : 1;            /*!< [2..2] temp is higher than the max value                                  */
      __IM  uint32_t ADCRDY     : 1;            /*!< [3..3] ADC ready to sample                                                */
      __IM  uint32_t EOT        : 1;            /*!< [4..4] End of transfer                                                    */
            uint32_t            : 27;
    } bit;
  } SR;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000010) Interrupt Enable Register                                  */
    
    struct {
      __IOM uint32_t EOCIE      : 1;            /*!< [0..0] ADC end of conversion interrupt enable                             */
      __IOM uint32_t TRIGERRIE  : 1;            /*!< [1..1] ADC trig error interrupt enable                                    */
      __IOM uint32_t OTPIE      : 1;            /*!< [2..2] ADC over temperature interrupt enable                              */
            uint32_t            : 29;
    } bit;
  } IER;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000014) Clear Interrupt Register                                   */
    
    struct {
      __OM  uint32_t EOCCLR     : 1;            /*!< [0..0] ADC end of conversion interrupt clear                              */
      __OM  uint32_t TRIGERRCLR : 1;            /*!< [1..1] ADC trig error interrupt clear                                     */
      __OM  uint32_t OTPCLR     : 1;            /*!< [2..2] ADC over temperature interrupt clear                               */
            uint32_t            : 1;
      __OM  uint32_t EOTCLR     : 1;            /*!< [4..4] DMA end of transfer flag clear                                     */
            uint32_t            : 27;
    } bit;
  } CIR;
  
  union {
    __IOM uint32_t reg[8];                      /*!< (@ 0x00000018) Logic Channel Config Register                              */
    
    struct {
      __IOM uint32_t CHSEL      : 5;            /*!< [4..0] ADC analog channel select:                                         */
            uint32_t            : 2;
      __IOM uint32_t PGAGAIN    : 3;            /*!< [9..7] PGA gain select                                                    */
      __IOM uint32_t PGASEL     : 2;            /*!< [11..10] PGA channel select00: position cos01: position sin10:
                                                     current sense11: reserve                                                  */
      __IOM uint32_t TRIGDELAY  : 10;           /*!< [21..12] setting channel setup time                                       */
      __IOM uint32_t TSAMP      : 10;           /*!< [31..22] setting ADC sample time                                          */
    } bit[8];
  } CHCFG;
  
  union {
    __IOM uint32_t reg[8];                      /*!< (@ 0x00000038) Logic Channel DATA Register                                */
    
    struct {
      __IM  uint32_t ADC_DATA   : 13;           /*!< [12..0] ADC Logic Channel DATA                                            */
            uint32_t            : 3;
      __IM  uint32_t DISP_CHSEL : 5;            /*!< [20..16] display CHCHG.CHSEL                                              */
            uint32_t            : 11;
    } bit[8];
  } DATA;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000058) Transfer DATA Register                                     */
    
    struct {
      __IM  uint32_t ADC_DATA   : 13;           /*!< [12..0] transfer Channel x DATA                                           */
            uint32_t            : 3;
      __IM  uint32_t DISP_CHSEL : 5;            /*!< [20..16] transfer CHxCHG.CHSEL                                            */
            uint32_t            : 11;
    } bit;
  } TDATA;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t reg;                         /*!< (@ 0x00000060) TEST Register                                              */
    
    struct {
      __IM  uint32_t ANA_CTRL_FSM : 3;          /*!< [2..0] ANA CTRL module state                                              */
            uint32_t            : 1;
      __IM  uint32_t SEQ_CTRL_FSM : 3;          /*!< [6..4] SEQ CTRL module state                                              */
            uint32_t            : 1;
      __IOM uint32_t CNT_VALID  : 1;            /*!< [8..8] 0: ANA hardware data valid1: counter data valid                    */
            uint32_t            : 3;
      __IOM uint32_t ANA_ADC_DEBUG_IN : 3;      /*!< [14..12] digital ADC 3bit debug sel000: ADC_CH_P[12]001: ADC_CH_P[13]010:
                                                     ADC_CH_P[14]011: ADC_CH_P[15]100: EN_ADC_H101: PGA_N110:
                                                     PGA_P111: VREFP                                                           */
            uint32_t            : 1;
      __IOM uint32_t DIG_ADC_DEBUG_IN : 3;      /*!< [18..16] digital ADC 3bit debug sel000: D2A_ADC_CHSEL[0]001:
                                                     D2A_ADC_CHSEL[1]010: D2A_VALID011: D2A_ADC_RSTN100: D2A_ADCCLK101:
                                                     D2A_SAMP110: LPMOD111: ADCEN                                              */
      __IM  uint32_t DIG_ADC_DEBUG_OUT : 1;     /*!< [19..19] 1bit digital ADC debug out                                       */
            uint32_t            : 1;
      __IM  uint32_t DEBUG_DATA : 1;            /*!< [21..21] 1bit adc debug data                                              */
            uint32_t            : 2;
      __IOM uint32_t ANA_PGA_DEBUG_IN : 3;      /*!< [26..24] analog PGA 3bit debug sel000: REG_COS_P001: PGA_SIN_P010:
                                                     PGA_CS_P011: internal_op_input_vcm100: VO_VCM101: VO_1P5110:
                                                     PGA_OUTN111: PGA_OUTP                                                     */
            uint32_t            : 1;
      __IOM uint32_t DIG_PGA_DEBUG_IN : 3;      /*!< [30..28] digital PGA 3bit debug sel000: REG_CS_SEL001: PGA_SPEED[0]010:
                                                     PGA_SPEED[1]011: PGA_GAIN[0]100: PGA_GAIN[1]101: PGA_GAIN[2]110:
                                                     PGA_EN111: ISO                                                            */
      __IM  uint32_t DIG_PGA_DEBUG_OUT : 1;     /*!< [31..31] 1bit digital PGA debug out                                       */
    } bit;
  } TEST;
} ADC_Type;                                     /*!< Size = 100 (0x64)                                                         */


/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

#define FMC0_BASE                   0x50006000UL
#define FMC1_BASE                   0x50007000UL
#define GPIOA_BASE                  0x400F0000UL
#define GPIOB_BASE                  0x400F0200UL
#define GPIOC_BASE                  0x400F0400UL
#define SPI0_BASE                   0x40011000UL
#define SPI1_BASE                   0x40012000UL
#define ePWM_BASE                   0x50003000UL
#define SYSCFG_BASE                 0x50005000UL
#define DMA_BASE                    0x400F1000UL
#define eCAP_BASE                   0x50002000UL
#define TIM0_BASE                   0x40006000UL
#define TIM1_BASE                   0x40007000UL
#define TIM2_BASE                   0x40008000UL
#define WWDG_BASE                   0x40009000UL
#define IWDG_BASE                   0x40018000UL
#define LIN_BASE                    0x4000A000UL
#define CAN_BASE                    0x40017000UL
#define RCC_BASE                    0x40003000UL
#define eDIAG_BASE                  0x50004000UL
#define ADC0_BASE                   0x50000000UL
#define ADC1_BASE                   0x50001000UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define FMC0                        ((FMC_Type*)               FMC0_BASE)
#define FMC1                        ((FMC_Type*)               FMC1_BASE)
#define GPIOA                       ((GPIO_Type*)              GPIOA_BASE)
#define GPIOB                       ((GPIO_Type*)              GPIOB_BASE)
#define GPIOC                       ((GPIO_Type*)              GPIOC_BASE)
#define SPI0                        ((SPI_Type*)               SPI0_BASE)
#define SPI1                        ((SPI_Type*)               SPI1_BASE)
#define ePWM                        ((ePWM_Type*)              ePWM_BASE)
#define SYSCFG                      ((SYSCFG_Type*)            SYSCFG_BASE)
#define DMA                         ((DMA_Type*)               DMA_BASE)
#define eCAP                        ((eCAP_Type*)              eCAP_BASE)
#define TIM0                        ((TIM_Type*)               TIM0_BASE)
#define TIM1                        ((TIM_Type*)               TIM1_BASE)
#define TIM2                        ((TIM_Type*)               TIM2_BASE)
#define WWDG                        ((WWDG_Type*)              WWDG_BASE)
#define IWDG                        ((IWDG_Type*)              IWDG_BASE)
#define LIN                         ((LIN_Type*)               LIN_BASE)
#define CAN                         ((CAN_Type*)               CAN_BASE)
#define RCC                         ((RCC_Type*)               RCC_BASE)
#define eDIAG                       ((eDIAG_Type*)             eDIAG_BASE)
#define ADC0                        ((ADC_Type*)               ADC0_BASE)
#define ADC1                        ((ADC_Type*)               ADC1_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */


/* =========================================================================================================================== */
/* ================                                Pos/Mask Peripheral Section                                ================ */
/* =========================================================================================================================== */


/** @addtogroup PosMask_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                            FMC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define FMC_CR_FILTER_FF_Pos              (27UL)                    /*!< FILTER_FF (Bit 27)                                    */
#define FMC_CR_FILTER_FF_Msk              (0x8000000UL)             /*!< FILTER_FF (Bitfield-Mask: 0x01)                       */
#define FMC_CR_PreadyEn_Pos               (25UL)                    /*!< PreadyEn (Bit 25)                                     */
#define FMC_CR_PreadyEn_Msk               (0x2000000UL)             /*!< PreadyEn (Bitfield-Mask: 0x01)                        */
#define FMC_CR_DPSTB_EN_Pos               (24UL)                    /*!< DPSTB_EN (Bit 24)                                     */
#define FMC_CR_DPSTB_EN_Msk               (0x1000000UL)             /*!< DPSTB_EN (Bitfield-Mask: 0x01)                        */
#define FMC_CR_PRESCALER_CFG_Pos          (0UL)                     /*!< PRESCALER_CFG (Bit 0)                                 */
#define FMC_CR_PRESCALER_CFG_Msk          (0x7UL)                   /*!< PRESCALER_CFG (Bitfield-Mask: 0x07)                   */
/* ==========================================================  SR0  ========================================================== */
#define FMC_SR0_ECC_SYND_Pos              (8UL)                     /*!< ECC_SYND (Bit 8)                                      */
#define FMC_SR0_ECC_SYND_Msk              (0xff00UL)                /*!< ECC_SYND (Bitfield-Mask: 0xff)                        */
#define FMC_SR0_ECC_ERR_Pos               (4UL)                     /*!< ECC_ERR (Bit 4)                                       */
#define FMC_SR0_ECC_ERR_Msk               (0x30UL)                  /*!< ECC_ERR (Bitfield-Mask: 0x03)                         */
#define FMC_SR0_STAR_ERR_Pos              (0UL)                     /*!< STAR_ERR (Bit 0)                                      */
#define FMC_SR0_STAR_ERR_Msk              (0x1UL)                   /*!< STAR_ERR (Bitfield-Mask: 0x01)                        */
/* ==========================================================  SR1  ========================================================== */
#define FMC_SR1_ECC_ERR_ADDR_Pos          (0UL)                     /*!< ECC_ERR_ADDR (Bit 0)                                  */
#define FMC_SR1_ECC_ERR_ADDR_Msk          (0xffffffffUL)            /*!< ECC_ERR_ADDR (Bitfield-Mask: 0xffffffff)              */
/* ==========================================================  CMD  ========================================================== */
#define FMC_CMD_CMD_Pos                   (0UL)                     /*!< CMD (Bit 0)                                           */
#define FMC_CMD_CMD_Msk                   (0x7UL)                   /*!< CMD (Bitfield-Mask: 0x07)                             */
/* ========================================================  CMD_EXE  ======================================================== */
#define FMC_CMD_EXE_EXE_Pos               (31UL)                    /*!< EXE (Bit 31)                                          */
#define FMC_CMD_EXE_EXE_Msk               (0x80000000UL)            /*!< EXE (Bitfield-Mask: 0x01)                             */
/* =========================================================  BYTES  ========================================================= */
#define FMC_BYTES_PROG_BYTES_Pos          (0UL)                     /*!< PROG_BYTES (Bit 0)                                    */
#define FMC_BYTES_PROG_BYTES_Msk          (0xffUL)                  /*!< PROG_BYTES (Bitfield-Mask: 0xff)                      */
/* =========================================================  ADDR  ========================================================== */
#define FMC_ADDR_ADDR_Pos                 (0UL)                     /*!< ADDR (Bit 0)                                          */
#define FMC_ADDR_ADDR_Msk                 (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  DATA0  ========================================================= */
#define FMC_DATA0_DATA0_Pos               (0UL)                     /*!< DATA0 (Bit 0)                                         */
#define FMC_DATA0_DATA0_Msk               (0xffffffffUL)            /*!< DATA0 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  DATA1  ========================================================= */
#define FMC_DATA1_DATA1_Pos               (0UL)                     /*!< DATA1 (Bit 0)                                         */
#define FMC_DATA1_DATA1_Msk               (0xffffffffUL)            /*!< DATA1 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  DATA2  ========================================================= */
#define FMC_DATA2_DATA2_Pos               (0UL)                     /*!< DATA2 (Bit 0)                                         */
#define FMC_DATA2_DATA2_Msk               (0xffUL)                  /*!< DATA2 (Bitfield-Mask: 0xff)                           */
/* =========================================================  INIT  ========================================================== */
#define FMC_INIT_PROTECTED_ERR_STATE_Pos  (4UL)                     /*!< PROTECTED_ERR_STATE (Bit 4)                           */
#define FMC_INIT_PROTECTED_ERR_STATE_Msk  (0x10UL)                  /*!< PROTECTED_ERR_STATE (Bitfield-Mask: 0x01)             */
#define FMC_INIT_AHB_PROG_ERR_STATE_Pos   (3UL)                     /*!< AHB_PROG_ERR_STATE (Bit 3)                            */
#define FMC_INIT_AHB_PROG_ERR_STATE_Msk   (0x8UL)                   /*!< AHB_PROG_ERR_STATE (Bitfield-Mask: 0x01)              */
#define FMC_INIT_ERASE_STATE_Pos          (2UL)                     /*!< ERASE_STATE (Bit 2)                                   */
#define FMC_INIT_ERASE_STATE_Msk          (0x4UL)                   /*!< ERASE_STATE (Bitfield-Mask: 0x01)                     */
#define FMC_INIT_PROG_STATE_Pos           (1UL)                     /*!< PROG_STATE (Bit 1)                                    */
#define FMC_INIT_PROG_STATE_Msk           (0x2UL)                   /*!< PROG_STATE (Bitfield-Mask: 0x01)                      */
#define FMC_INIT_ECC_ERR_STATE_Pos        (0UL)                     /*!< ECC_ERR_STATE (Bit 0)                                 */
#define FMC_INIT_ECC_ERR_STATE_Msk        (0x1UL)                   /*!< ECC_ERR_STATE (Bitfield-Mask: 0x01)                   */
/* ==========================================================  IER  ========================================================== */
#define FMC_IER_PROTECTED_ERR_EN_Pos      (4UL)                     /*!< PROTECTED_ERR_EN (Bit 4)                              */
#define FMC_IER_PROTECTED_ERR_EN_Msk      (0x10UL)                  /*!< PROTECTED_ERR_EN (Bitfield-Mask: 0x01)                */
#define FMC_IER_AHB_PROG_ERR_EN_Pos       (3UL)                     /*!< AHB_PROG_ERR_EN (Bit 3)                               */
#define FMC_IER_AHB_PROG_ERR_EN_Msk       (0x8UL)                   /*!< AHB_PROG_ERR_EN (Bitfield-Mask: 0x01)                 */
#define FMC_IER_ERASE_EN_Pos              (2UL)                     /*!< ERASE_EN (Bit 2)                                      */
#define FMC_IER_ERASE_EN_Msk              (0x4UL)                   /*!< ERASE_EN (Bitfield-Mask: 0x01)                        */
#define FMC_IER_PROG_EN_Pos               (1UL)                     /*!< PROG_EN (Bit 1)                                       */
#define FMC_IER_PROG_EN_Msk               (0x2UL)                   /*!< PROG_EN (Bitfield-Mask: 0x01)                         */
#define FMC_IER_ECC_ERR_EN_Pos            (0UL)                     /*!< ECC_ERR_EN (Bit 0)                                    */
#define FMC_IER_ECC_ERR_EN_Msk            (0x1UL)                   /*!< ECC_ERR_EN (Bitfield-Mask: 0x01)                      */
/* ==========================================================  CLR  ========================================================== */
#define FMC_CLR_PROTECTED_ERR_CLR_Pos     (4UL)                     /*!< PROTECTED_ERR_CLR (Bit 4)                             */
#define FMC_CLR_PROTECTED_ERR_CLR_Msk     (0x10UL)                  /*!< PROTECTED_ERR_CLR (Bitfield-Mask: 0x01)               */
#define FMC_CLR_AHB_PROG_ERR_CLR_Pos      (3UL)                     /*!< AHB_PROG_ERR_CLR (Bit 3)                              */
#define FMC_CLR_AHB_PROG_ERR_CLR_Msk      (0x8UL)                   /*!< AHB_PROG_ERR_CLR (Bitfield-Mask: 0x01)                */
#define FMC_CLR_ERASE_CLR_Pos             (2UL)                     /*!< ERASE_CLR (Bit 2)                                     */
#define FMC_CLR_ERASE_CLR_Msk             (0x4UL)                   /*!< ERASE_CLR (Bitfield-Mask: 0x01)                       */
#define FMC_CLR_PROG_CLR_Pos              (1UL)                     /*!< PROG_CLR (Bit 1)                                      */
#define FMC_CLR_PROG_CLR_Msk              (0x2UL)                   /*!< PROG_CLR (Bitfield-Mask: 0x01)                        */
#define FMC_CLR_ECC_ERR_CLR_Pos           (0UL)                     /*!< ECC_ERR_CLR (Bit 0)                                   */
#define FMC_CLR_ECC_ERR_CLR_Msk           (0x1UL)                   /*!< ECC_ERR_CLR (Bitfield-Mask: 0x01)                     */
/* ========================================================  PARAM0  ========================================================= */
#define FMC_PARAM0_ERASE_TRCV_C_Pos       (20UL)                    /*!< ERASE_TRCV_C (Bit 20)                                 */
#define FMC_PARAM0_ERASE_TRCV_C_Msk       (0xf00000UL)              /*!< ERASE_TRCV_C (Bitfield-Mask: 0x0f)                    */
#define FMC_PARAM0_ERASE_TRCV_S_Pos       (16UL)                    /*!< ERASE_TRCV_S (Bit 16)                                 */
#define FMC_PARAM0_ERASE_TRCV_S_Msk       (0xf0000UL)               /*!< ERASE_TRCV_S (Bitfield-Mask: 0x0f)                    */
#define FMC_PARAM0_ERASE_TERASE_C_Pos     (12UL)                    /*!< ERASE_TERASE_C (Bit 12)                               */
#define FMC_PARAM0_ERASE_TERASE_C_Msk     (0xf000UL)                /*!< ERASE_TERASE_C (Bitfield-Mask: 0x0f)                  */
#define FMC_PARAM0_ERASE_TERASE_S_Pos     (8UL)                     /*!< ERASE_TERASE_S (Bit 8)                                */
#define FMC_PARAM0_ERASE_TERASE_S_Msk     (0xf00UL)                 /*!< ERASE_TERASE_S (Bitfield-Mask: 0x0f)                  */
#define FMC_PARAM0_ERASE_TNVS_Pos         (4UL)                     /*!< ERASE_TNVS (Bit 4)                                    */
#define FMC_PARAM0_ERASE_TNVS_Msk         (0xf0UL)                  /*!< ERASE_TNVS (Bitfield-Mask: 0x0f)                      */
#define FMC_PARAM0_TWUP_Pos               (0UL)                     /*!< TWUP (Bit 0)                                          */
#define FMC_PARAM0_TWUP_Msk               (0xfUL)                   /*!< TWUP (Bitfield-Mask: 0x0f)                            */
/* ========================================================  PARAM1  ========================================================= */
#define FMC_PARAM1_prog_Trcv_Pos          (16UL)                    /*!< prog_Trcv (Bit 16)                                    */
#define FMC_PARAM1_prog_Trcv_Msk          (0xf0000UL)               /*!< prog_Trcv (Bitfield-Mask: 0x0f)                       */
#define FMC_PARAM1_prog_Tprog_Pos         (10UL)                    /*!< prog_Tprog (Bit 10)                                   */
#define FMC_PARAM1_prog_Tprog_Msk         (0xfc00UL)                /*!< prog_Tprog (Bitfield-Mask: 0x3f)                      */
#define FMC_PARAM1_prog_Tpgs_Pos          (4UL)                     /*!< prog_Tpgs (Bit 4)                                     */
#define FMC_PARAM1_prog_Tpgs_Msk          (0x3f0UL)                 /*!< prog_Tpgs (Bitfield-Mask: 0x3f)                       */
#define FMC_PARAM1_prog_Tnvs_Pos          (0UL)                     /*!< prog_Tnvs (Bit 0)                                     */
#define FMC_PARAM1_prog_Tnvs_Msk          (0xfUL)                   /*!< prog_Tnvs (Bitfield-Mask: 0x0f)                       */
/* =========================================================  TRIM0  ========================================================= */
#define FMC_TRIM0_TRIM0_Pos               (0UL)                     /*!< TRIM0 (Bit 0)                                         */
#define FMC_TRIM0_TRIM0_Msk               (0xffffffffUL)            /*!< TRIM0 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  TRIM1  ========================================================= */
#define FMC_TRIM1_TRIM1_Pos               (0UL)                     /*!< TRIM1 (Bit 0)                                         */
#define FMC_TRIM1_TRIM1_Msk               (0xffffffffUL)            /*!< TRIM1 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  TRIM2  ========================================================= */
#define FMC_TRIM2_TRIM2_Pos               (0UL)                     /*!< TRIM2 (Bit 0)                                         */
#define FMC_TRIM2_TRIM2_Msk               (0xffffUL)                /*!< TRIM2 (Bitfield-Mask: 0xffff)                         */
/* =========================================================  FTST  ========================================================== */
#define FMC_FTST_TST_KEY_Pos              (16UL)                    /*!< TST_KEY (Bit 16)                                      */
#define FMC_FTST_TST_KEY_Msk              (0xffff0000UL)            /*!< TST_KEY (Bitfield-Mask: 0xffff)                       */
#define FMC_FTST_READM1_Pos               (1UL)                     /*!< READM1 (Bit 1)                                        */
#define FMC_FTST_READM1_Msk               (0x2UL)                   /*!< READM1 (Bitfield-Mask: 0x01)                          */
#define FMC_FTST_READM0_Pos               (0UL)                     /*!< READM0 (Bit 0)                                        */
#define FMC_FTST_READM0_Msk               (0x1UL)                   /*!< READM0 (Bitfield-Mask: 0x01)                          */
/* =======================================================  TRIM_KEY  ======================================================== */
/* =======================================================  PARAM_KEY  ======================================================= */
#define FMC_PARAM_KEY_PARAM_KEY_Pos       (0UL)                     /*!< PARAM_KEY (Bit 0)                                     */
#define FMC_PARAM_KEY_PARAM_KEY_Msk       (0xffffffffUL)            /*!< PARAM_KEY (Bitfield-Mask: 0xffffffff)                 */
/* ========================================================  ECC_INL  ======================================================== */
#define FMC_ECC_INL_ECC_INL_Pos           (0UL)                     /*!< ECC_INL (Bit 0)                                       */
#define FMC_ECC_INL_ECC_INL_Msk           (0xffffffffUL)            /*!< ECC_INL (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  ECC_INM  ======================================================== */
#define FMC_ECC_INM_ECC_INM_Pos           (0UL)                     /*!< ECC_INM (Bit 0)                                       */
#define FMC_ECC_INM_ECC_INM_Msk           (0xffffffffUL)            /*!< ECC_INM (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  ECC_INH  ======================================================== */
#define FMC_ECC_INH_ECC_INH_Pos           (0UL)                     /*!< ECC_INH (Bit 0)                                       */
#define FMC_ECC_INH_ECC_INH_Msk           (0xffUL)                  /*!< ECC_INH (Bitfield-Mask: 0xff)                         */


/* =========================================================================================================================== */
/* ================                                           GPIO                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  MODER  ========================================================= */
#define GPIO_MODER_MODE_Pos               (0UL)                     /*!< MODE (Bit 0)                                          */
#define GPIO_MODER_MODE_Msk               (0x3UL)                   /*!< MODE (Bitfield-Mask: 0x03)                            */
/* ========================================================  OTYPER  ========================================================= */
#define GPIO_OTYPER_OT_Pos                (0UL)                     /*!< OT (Bit 0)                                            */
#define GPIO_OTYPER_OT_Msk                (0x1UL)                   /*!< OT (Bitfield-Mask: 0x01)                              */
/* ==========================================================  STR  ========================================================== */
#define GPIO_STR_STR_Pos                  (0UL)                     /*!< STR (Bit 0)                                           */
#define GPIO_STR_STR_Msk                  (0x1UL)                   /*!< STR (Bitfield-Mask: 0x01)                             */
/* =========================================================  SLEWR  ========================================================= */
#define GPIO_SLEWR_RATE_Pos               (0UL)                     /*!< RATE (Bit 0)                                          */
#define GPIO_SLEWR_RATE_Msk               (0x1UL)                   /*!< RATE (Bitfield-Mask: 0x01)                            */
/* =========================================================  PUPDR  ========================================================= */
#define GPIO_PUPDR_PUPD_Pos               (0UL)                     /*!< PUPD (Bit 0)                                          */
#define GPIO_PUPDR_PUPD_Msk               (0x3UL)                   /*!< PUPD (Bitfield-Mask: 0x03)                            */
/* ==========================================================  IDR  ========================================================== */
#define GPIO_IDR_ID_Pos                   (0UL)                     /*!< ID (Bit 0)                                            */
#define GPIO_IDR_ID_Msk                   (0x1UL)                   /*!< ID (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ODR  ========================================================== */
#define GPIO_ODR_OD_Pos                   (0UL)                     /*!< OD (Bit 0)                                            */
#define GPIO_ODR_OD_Msk                   (0x1UL)                   /*!< OD (Bitfield-Mask: 0x01)                              */
/* =========================================================  AFLR  ========================================================== */
#define GPIO_AFLR_AFSEL_Pos               (0UL)                     /*!< AFSEL (Bit 0)                                         */
#define GPIO_AFLR_AFSEL_Msk               (0xfUL)                   /*!< AFSEL (Bitfield-Mask: 0x0f)                           */
/* =========================================================  AFHR  ========================================================== */
#define GPIO_AFHR_AFSEL_Pos               (0UL)                     /*!< AFSEL (Bit 0)                                         */
#define GPIO_AFHR_AFSEL_Msk               (0xfUL)                   /*!< AFSEL (Bitfield-Mask: 0x0f)                           */
/* ========================================================  EDGIER  ========================================================= */
#define GPIO_EDGIER_EDGIE_Pos             (0UL)                     /*!< EDGIE (Bit 0)                                         */
#define GPIO_EDGIER_EDGIE_Msk             (0x3UL)                   /*!< EDGIE (Bitfield-Mask: 0x03)                           */
/* ========================================================  EDGISR  ========================================================= */
#define GPIO_EDGISR_EDGISR_Pos            (0UL)                     /*!< EDGISR (Bit 0)                                        */
#define GPIO_EDGISR_EDGISR_Msk            (0x3UL)                   /*!< EDGISR (Bitfield-Mask: 0x03)                          */
/* ========================================================  EDGICLR  ======================================================== */
#define GPIO_EDGICLR_EDGICLR_Pos          (0UL)                     /*!< EDGICLR (Bit 0)                                       */
#define GPIO_EDGICLR_EDGICLR_Msk          (0x3UL)                   /*!< EDGICLR (Bitfield-Mask: 0x03)                         */
/* ========================================================  LEVIER  ========================================================= */
#define GPIO_LEVIER_LEVIE_Pos             (0UL)                     /*!< LEVIE (Bit 0)                                         */
#define GPIO_LEVIER_LEVIE_Msk             (0x3UL)                   /*!< LEVIE (Bitfield-Mask: 0x03)                           */
/* ========================================================  LEVISR  ========================================================= */
#define GPIO_LEVISR_LEVISR_Pos            (0UL)                     /*!< LEVISR (Bit 0)                                        */
#define GPIO_LEVISR_LEVISR_Msk            (0x3UL)                   /*!< LEVISR (Bitfield-Mask: 0x03)                          */
/* ========================================================  LEVICLR  ======================================================== */
#define GPIO_LEVICLR_LEVICLR_Pos          (0UL)                     /*!< LEVICLR (Bit 0)                                       */
#define GPIO_LEVICLR_LEVICLR_Msk          (0x3UL)                   /*!< LEVICLR (Bitfield-Mask: 0x03)                         */


/* =========================================================================================================================== */
/* ================                                            SPI                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  CTRLR0  ========================================================= */
#define SPI_CTRLR0_SSTE_Pos               (24UL)                    /*!< SSTE (Bit 24)                                         */
#define SPI_CTRLR0_SSTE_Msk               (0x1000000UL)             /*!< SSTE (Bitfield-Mask: 0x01)                            */
#define SPI_CTRLR0_SPI_FRF_Pos            (21UL)                    /*!< SPI_FRF (Bit 21)                                      */
#define SPI_CTRLR0_SPI_FRF_Msk            (0x600000UL)              /*!< SPI_FRF (Bitfield-Mask: 0x03)                         */
#define SPI_CTRLR0_DFS_32_Pos             (16UL)                    /*!< DFS_32 (Bit 16)                                       */
#define SPI_CTRLR0_DFS_32_Msk             (0x1f0000UL)              /*!< DFS_32 (Bitfield-Mask: 0x1f)                          */
#define SPI_CTRLR0_CFS_Pos                (12UL)                    /*!< CFS (Bit 12)                                          */
#define SPI_CTRLR0_CFS_Msk                (0xf000UL)                /*!< CFS (Bitfield-Mask: 0x0f)                             */
#define SPI_CTRLR0_SRL_Pos                (11UL)                    /*!< SRL (Bit 11)                                          */
#define SPI_CTRLR0_SRL_Msk                (0x800UL)                 /*!< SRL (Bitfield-Mask: 0x01)                             */
#define SPI_CTRLR0_TMOD_Pos               (8UL)                     /*!< TMOD (Bit 8)                                          */
#define SPI_CTRLR0_TMOD_Msk               (0x300UL)                 /*!< TMOD (Bitfield-Mask: 0x03)                            */
#define SPI_CTRLR0_SCPOL_Pos              (7UL)                     /*!< SCPOL (Bit 7)                                         */
#define SPI_CTRLR0_SCPOL_Msk              (0x80UL)                  /*!< SCPOL (Bitfield-Mask: 0x01)                           */
#define SPI_CTRLR0_SCPH_Pos               (6UL)                     /*!< SCPH (Bit 6)                                          */
#define SPI_CTRLR0_SCPH_Msk               (0x40UL)                  /*!< SCPH (Bitfield-Mask: 0x01)                            */
#define SPI_CTRLR0_FRF_Pos                (4UL)                     /*!< FRF (Bit 4)                                           */
#define SPI_CTRLR0_FRF_Msk                (0x30UL)                  /*!< FRF (Bitfield-Mask: 0x03)                             */
#define SPI_CTRLR0_DFS_Pos                (0UL)                     /*!< DFS (Bit 0)                                           */
#define SPI_CTRLR0_DFS_Msk                (0xfUL)                   /*!< DFS (Bitfield-Mask: 0x0f)                             */
/* ========================================================  CTRLR1  ========================================================= */
#define SPI_CTRLR1_NDF_Pos                (0UL)                     /*!< NDF (Bit 0)                                           */
#define SPI_CTRLR1_NDF_Msk                (0xffffUL)                /*!< NDF (Bitfield-Mask: 0xffff)                           */
/* ========================================================  SSIENR  ========================================================= */
#define SPI_SSIENR_SSI_EN_Pos             (0UL)                     /*!< SSI_EN (Bit 0)                                        */
#define SPI_SSIENR_SSI_EN_Msk             (0x1UL)                   /*!< SSI_EN (Bitfield-Mask: 0x01)                          */
/* =========================================================  MWCR  ========================================================== */
#define SPI_MWCR_MHS_Pos                  (2UL)                     /*!< MHS (Bit 2)                                           */
#define SPI_MWCR_MHS_Msk                  (0x4UL)                   /*!< MHS (Bitfield-Mask: 0x01)                             */
#define SPI_MWCR_MDD_Pos                  (1UL)                     /*!< MDD (Bit 1)                                           */
#define SPI_MWCR_MDD_Msk                  (0x2UL)                   /*!< MDD (Bitfield-Mask: 0x01)                             */
#define SPI_MWCR_MWMOD_Pos                (0UL)                     /*!< MWMOD (Bit 0)                                         */
#define SPI_MWCR_MWMOD_Msk                (0x1UL)                   /*!< MWMOD (Bitfield-Mask: 0x01)                           */
/* ==========================================================  SER  ========================================================== */
#define SPI_SER_SER_Pos                   (0UL)                     /*!< SER (Bit 0)                                           */
#define SPI_SER_SER_Msk                   (0x1UL)                   /*!< SER (Bitfield-Mask: 0x01)                             */
/* =========================================================  BAUDR  ========================================================= */
#define SPI_BAUDR_SCKDV_Pos               (0UL)                     /*!< SCKDV (Bit 0)                                         */
#define SPI_BAUDR_SCKDV_Msk               (0xffffUL)                /*!< SCKDV (Bitfield-Mask: 0xffff)                         */
/* ========================================================  TXFTLR  ========================================================= */
#define SPI_TXFTLR_TFT_Pos                (0UL)                     /*!< TFT (Bit 0)                                           */
#define SPI_TXFTLR_TFT_Msk                (0x7UL)                   /*!< TFT (Bitfield-Mask: 0x07)                             */
/* ========================================================  RXFTLR  ========================================================= */
#define SPI_RXFTLR_RFT_Pos                (0UL)                     /*!< RFT (Bit 0)                                           */
#define SPI_RXFTLR_RFT_Msk                (0x7UL)                   /*!< RFT (Bitfield-Mask: 0x07)                             */
/* =========================================================  TXFLR  ========================================================= */
#define SPI_TXFLR_TXTFL_Pos               (0UL)                     /*!< TXTFL (Bit 0)                                         */
#define SPI_TXFLR_TXTFL_Msk               (0xfUL)                   /*!< TXTFL (Bitfield-Mask: 0x0f)                           */
/* =========================================================  RXFLR  ========================================================= */
#define SPI_RXFLR_RXTFL_Pos               (0UL)                     /*!< RXTFL (Bit 0)                                         */
#define SPI_RXFLR_RXTFL_Msk               (0xfUL)                   /*!< RXTFL (Bitfield-Mask: 0x0f)                           */
/* ==========================================================  SR  =========================================================== */
#define SPI_SR_DCOL_Pos                   (6UL)                     /*!< DCOL (Bit 6)                                          */
#define SPI_SR_DCOL_Msk                   (0x40UL)                  /*!< DCOL (Bitfield-Mask: 0x01)                            */
#define SPI_SR_RFF_Pos                    (4UL)                     /*!< RFF (Bit 4)                                           */
#define SPI_SR_RFF_Msk                    (0x10UL)                  /*!< RFF (Bitfield-Mask: 0x01)                             */
#define SPI_SR_RFNE_Pos                   (3UL)                     /*!< RFNE (Bit 3)                                          */
#define SPI_SR_RFNE_Msk                   (0x8UL)                   /*!< RFNE (Bitfield-Mask: 0x01)                            */
#define SPI_SR_TFE_Pos                    (2UL)                     /*!< TFE (Bit 2)                                           */
#define SPI_SR_TFE_Msk                    (0x4UL)                   /*!< TFE (Bitfield-Mask: 0x01)                             */
#define SPI_SR_TFNF_Pos                   (1UL)                     /*!< TFNF (Bit 1)                                          */
#define SPI_SR_TFNF_Msk                   (0x2UL)                   /*!< TFNF (Bitfield-Mask: 0x01)                            */
#define SPI_SR_BUSY_Pos                   (0UL)                     /*!< BUSY (Bit 0)                                          */
#define SPI_SR_BUSY_Msk                   (0x1UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
/* ==========================================================  IMR  ========================================================== */
#define SPI_IMR_MSTIM_Pos                 (5UL)                     /*!< MSTIM (Bit 5)                                         */
#define SPI_IMR_MSTIM_Msk                 (0x20UL)                  /*!< MSTIM (Bitfield-Mask: 0x01)                           */
#define SPI_IMR_RXFIM_Pos                 (4UL)                     /*!< RXFIM (Bit 4)                                         */
#define SPI_IMR_RXFIM_Msk                 (0x10UL)                  /*!< RXFIM (Bitfield-Mask: 0x01)                           */
#define SPI_IMR_RXOIM_Pos                 (3UL)                     /*!< RXOIM (Bit 3)                                         */
#define SPI_IMR_RXOIM_Msk                 (0x8UL)                   /*!< RXOIM (Bitfield-Mask: 0x01)                           */
#define SPI_IMR_RXUIM_Pos                 (2UL)                     /*!< RXUIM (Bit 2)                                         */
#define SPI_IMR_RXUIM_Msk                 (0x4UL)                   /*!< RXUIM (Bitfield-Mask: 0x01)                           */
#define SPI_IMR_TXOIM_Pos                 (1UL)                     /*!< TXOIM (Bit 1)                                         */
#define SPI_IMR_TXOIM_Msk                 (0x2UL)                   /*!< TXOIM (Bitfield-Mask: 0x01)                           */
#define SPI_IMR_TXEIM_Pos                 (0UL)                     /*!< TXEIM (Bit 0)                                         */
#define SPI_IMR_TXEIM_Msk                 (0x1UL)                   /*!< TXEIM (Bitfield-Mask: 0x01)                           */
/* ==========================================================  ISR  ========================================================== */
#define SPI_ISR_MSTIS_Pos                 (5UL)                     /*!< MSTIS (Bit 5)                                         */
#define SPI_ISR_MSTIS_Msk                 (0x20UL)                  /*!< MSTIS (Bitfield-Mask: 0x01)                           */
#define SPI_ISR_RXFIS_Pos                 (4UL)                     /*!< RXFIS (Bit 4)                                         */
#define SPI_ISR_RXFIS_Msk                 (0x10UL)                  /*!< RXFIS (Bitfield-Mask: 0x01)                           */
#define SPI_ISR_RXOIS_Pos                 (3UL)                     /*!< RXOIS (Bit 3)                                         */
#define SPI_ISR_RXOIS_Msk                 (0x8UL)                   /*!< RXOIS (Bitfield-Mask: 0x01)                           */
#define SPI_ISR_RXUIS_Pos                 (2UL)                     /*!< RXUIS (Bit 2)                                         */
#define SPI_ISR_RXUIS_Msk                 (0x4UL)                   /*!< RXUIS (Bitfield-Mask: 0x01)                           */
#define SPI_ISR_TXOIS_Pos                 (1UL)                     /*!< TXOIS (Bit 1)                                         */
#define SPI_ISR_TXOIS_Msk                 (0x2UL)                   /*!< TXOIS (Bitfield-Mask: 0x01)                           */
#define SPI_ISR_TXEIS_Pos                 (0UL)                     /*!< TXEIS (Bit 0)                                         */
#define SPI_ISR_TXEIS_Msk                 (0x1UL)                   /*!< TXEIS (Bitfield-Mask: 0x01)                           */
/* =========================================================  RISR  ========================================================== */
#define SPI_RISR_MSTIR_Pos                (5UL)                     /*!< MSTIR (Bit 5)                                         */
#define SPI_RISR_MSTIR_Msk                (0x20UL)                  /*!< MSTIR (Bitfield-Mask: 0x01)                           */
#define SPI_RISR_RXFIR_Pos                (4UL)                     /*!< RXFIR (Bit 4)                                         */
#define SPI_RISR_RXFIR_Msk                (0x10UL)                  /*!< RXFIR (Bitfield-Mask: 0x01)                           */
#define SPI_RISR_RXOIR_Pos                (3UL)                     /*!< RXOIR (Bit 3)                                         */
#define SPI_RISR_RXOIR_Msk                (0x8UL)                   /*!< RXOIR (Bitfield-Mask: 0x01)                           */
#define SPI_RISR_RXUIR_Pos                (2UL)                     /*!< RXUIR (Bit 2)                                         */
#define SPI_RISR_RXUIR_Msk                (0x4UL)                   /*!< RXUIR (Bitfield-Mask: 0x01)                           */
#define SPI_RISR_TXOIR_Pos                (1UL)                     /*!< TXOIR (Bit 1)                                         */
#define SPI_RISR_TXOIR_Msk                (0x2UL)                   /*!< TXOIR (Bitfield-Mask: 0x01)                           */
#define SPI_RISR_TXEIR_Pos                (0UL)                     /*!< TXEIR (Bit 0)                                         */
#define SPI_RISR_TXEIR_Msk                (0x1UL)                   /*!< TXEIR (Bitfield-Mask: 0x01)                           */
/* ========================================================  TXOICR  ========================================================= */
#define SPI_TXOICR_TXOICR_Pos             (0UL)                     /*!< TXOICR (Bit 0)                                        */
#define SPI_TXOICR_TXOICR_Msk             (0x1UL)                   /*!< TXOICR (Bitfield-Mask: 0x01)                          */
/* ========================================================  RXOICR  ========================================================= */
#define SPI_RXOICR_RXOICR_Pos             (0UL)                     /*!< RXOICR (Bit 0)                                        */
#define SPI_RXOICR_RXOICR_Msk             (0x1UL)                   /*!< RXOICR (Bitfield-Mask: 0x01)                          */
/* ========================================================  RXUICR  ========================================================= */
#define SPI_RXUICR_RXUICR_Pos             (0UL)                     /*!< RXUICR (Bit 0)                                        */
#define SPI_RXUICR_RXUICR_Msk             (0x1UL)                   /*!< RXUICR (Bitfield-Mask: 0x01)                          */
/* ========================================================  MSTICR  ========================================================= */
#define SPI_MSTICR_MSTICR_Pos             (0UL)                     /*!< MSTICR (Bit 0)                                        */
#define SPI_MSTICR_MSTICR_Msk             (0x1UL)                   /*!< MSTICR (Bitfield-Mask: 0x01)                          */
/* ==========================================================  ICR  ========================================================== */
#define SPI_ICR_ICR_Pos                   (0UL)                     /*!< ICR (Bit 0)                                           */
#define SPI_ICR_ICR_Msk                   (0x1UL)                   /*!< ICR (Bitfield-Mask: 0x01)                             */
/* =========================================================  DMACR  ========================================================= */
#define SPI_DMACR_TDMAE_Pos               (1UL)                     /*!< TDMAE (Bit 1)                                         */
#define SPI_DMACR_TDMAE_Msk               (0x2UL)                   /*!< TDMAE (Bitfield-Mask: 0x01)                           */
#define SPI_DMACR_RDMAE_Pos               (0UL)                     /*!< RDMAE (Bit 0)                                         */
#define SPI_DMACR_RDMAE_Msk               (0x1UL)                   /*!< RDMAE (Bitfield-Mask: 0x01)                           */
/* ========================================================  DMATDLR  ======================================================== */
#define SPI_DMATDLR_DMATDL_Pos            (0UL)                     /*!< DMATDL (Bit 0)                                        */
#define SPI_DMATDLR_DMATDL_Msk            (0x7UL)                   /*!< DMATDL (Bitfield-Mask: 0x07)                          */
/* ========================================================  DMARDLR  ======================================================== */
#define SPI_DMARDLR_DMARDLR_Pos           (0UL)                     /*!< DMARDLR (Bit 0)                                       */
#define SPI_DMARDLR_DMARDLR_Msk           (0x7UL)                   /*!< DMARDLR (Bitfield-Mask: 0x07)                         */
/* ==========================================================  IDR  ========================================================== */
#define SPI_IDR_IDCODE_Pos                (0UL)                     /*!< IDCODE (Bit 0)                                        */
#define SPI_IDR_IDCODE_Msk                (0xffffffffUL)            /*!< IDCODE (Bitfield-Mask: 0xffffffff)                    */
/* ====================================================  SSI_VERSION_ID  ===================================================== */
#define SPI_SSI_VERSION_ID_SSI_COMP_VERSION_Pos (0UL)               /*!< SSI_COMP_VERSION (Bit 0)                              */
#define SPI_SSI_VERSION_ID_SSI_COMP_VERSION_Msk (0xffffffffUL)      /*!< SSI_COMP_VERSION (Bitfield-Mask: 0xffffffff)          */
/* ==========================================================  DR  =========================================================== */
/* =====================================================  RX_SAMPLE_DLY  ===================================================== */
#define SPI_RX_SAMPLE_DLY_RSD_Pos         (0UL)                     /*!< RSD (Bit 0)                                           */
#define SPI_RX_SAMPLE_DLY_RSD_Msk         (0xffUL)                  /*!< RSD (Bitfield-Mask: 0xff)                             */
/* ====================================================  TXD_DRIVE_EDGE  ===================================================== */
#define SPI_TXD_DRIVE_EDGE_TDE_Pos        (0UL)                     /*!< TDE (Bit 0)                                           */
#define SPI_TXD_DRIVE_EDGE_TDE_Msk        (0xffUL)                  /*!< TDE (Bitfield-Mask: 0xff)                             */


/* =========================================================================================================================== */
/* ================                                           ePWM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
#define ePWM_CR1_CMP5TRGCF_Pos            (20UL)                    /*!< CMP5TRGCF (Bit 20)                                    */
#define ePWM_CR1_CMP5TRGCF_Msk            (0x300000UL)              /*!< CMP5TRGCF (Bitfield-Mask: 0x03)                       */
#define ePWM_CR1_CMP4TRGCF_Pos            (18UL)                    /*!< CMP4TRGCF (Bit 18)                                    */
#define ePWM_CR1_CMP4TRGCF_Msk            (0xc0000UL)               /*!< CMP4TRGCF (Bitfield-Mask: 0x03)                       */
#define ePWM_CR1_CMP3TRGCF_Pos            (16UL)                    /*!< CMP3TRGCF (Bit 16)                                    */
#define ePWM_CR1_CMP3TRGCF_Msk            (0x30000UL)               /*!< CMP3TRGCF (Bitfield-Mask: 0x03)                       */
#define ePWM_CR1_CMP2TRGCF_Pos            (14UL)                    /*!< CMP2TRGCF (Bit 14)                                    */
#define ePWM_CR1_CMP2TRGCF_Msk            (0xc000UL)                /*!< CMP2TRGCF (Bitfield-Mask: 0x03)                       */
#define ePWM_CR1_CMP1TRGCF_Pos            (12UL)                    /*!< CMP1TRGCF (Bit 12)                                    */
#define ePWM_CR1_CMP1TRGCF_Msk            (0x3000UL)                /*!< CMP1TRGCF (Bitfield-Mask: 0x03)                       */
#define ePWM_CR1_CMP0TRGCF_Pos            (10UL)                    /*!< CMP0TRGCF (Bit 10)                                    */
#define ePWM_CR1_CMP0TRGCF_Msk            (0xc00UL)                 /*!< CMP0TRGCF (Bitfield-Mask: 0x03)                       */
#define ePWM_CR1_CKD_Pos                  (8UL)                     /*!< CKD (Bit 8)                                           */
#define ePWM_CR1_CKD_Msk                  (0x300UL)                 /*!< CKD (Bitfield-Mask: 0x03)                             */
#define ePWM_CR1_ARPE_Pos                 (7UL)                     /*!< ARPE (Bit 7)                                          */
#define ePWM_CR1_ARPE_Msk                 (0x80UL)                  /*!< ARPE (Bitfield-Mask: 0x01)                            */
#define ePWM_CR1_CMS_Pos                  (5UL)                     /*!< CMS (Bit 5)                                           */
#define ePWM_CR1_CMS_Msk                  (0x60UL)                  /*!< CMS (Bitfield-Mask: 0x03)                             */
#define ePWM_CR1_DIR_Pos                  (4UL)                     /*!< DIR (Bit 4)                                           */
#define ePWM_CR1_DIR_Msk                  (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define ePWM_CR1_OPM_Pos                  (3UL)                     /*!< OPM (Bit 3)                                           */
#define ePWM_CR1_OPM_Msk                  (0x8UL)                   /*!< OPM (Bitfield-Mask: 0x01)                             */
#define ePWM_CR1_URS_Pos                  (2UL)                     /*!< URS (Bit 2)                                           */
#define ePWM_CR1_URS_Msk                  (0x4UL)                   /*!< URS (Bitfield-Mask: 0x01)                             */
#define ePWM_CR1_UDIS_Pos                 (1UL)                     /*!< UDIS (Bit 1)                                          */
#define ePWM_CR1_UDIS_Msk                 (0x2UL)                   /*!< UDIS (Bitfield-Mask: 0x01)                            */
#define ePWM_CR1_CEN_Pos                  (0UL)                     /*!< CEN (Bit 0)                                           */
#define ePWM_CR1_CEN_Msk                  (0x1UL)                   /*!< CEN (Bitfield-Mask: 0x01)                             */
/* ==========================================================  CR2  ========================================================== */
#define ePWM_CR2_OIS4_Pos                 (14UL)                    /*!< OIS4 (Bit 14)                                         */
#define ePWM_CR2_OIS4_Msk                 (0x4000UL)                /*!< OIS4 (Bitfield-Mask: 0x01)                            */
#define ePWM_CR2_OIS3N_Pos                (13UL)                    /*!< OIS3N (Bit 13)                                        */
#define ePWM_CR2_OIS3N_Msk                (0x2000UL)                /*!< OIS3N (Bitfield-Mask: 0x01)                           */
#define ePWM_CR2_OIS3_Pos                 (12UL)                    /*!< OIS3 (Bit 12)                                         */
#define ePWM_CR2_OIS3_Msk                 (0x1000UL)                /*!< OIS3 (Bitfield-Mask: 0x01)                            */
#define ePWM_CR2_OIS2N_Pos                (11UL)                    /*!< OIS2N (Bit 11)                                        */
#define ePWM_CR2_OIS2N_Msk                (0x800UL)                 /*!< OIS2N (Bitfield-Mask: 0x01)                           */
#define ePWM_CR2_OIS2_Pos                 (10UL)                    /*!< OIS2 (Bit 10)                                         */
#define ePWM_CR2_OIS2_Msk                 (0x400UL)                 /*!< OIS2 (Bitfield-Mask: 0x01)                            */
#define ePWM_CR2_OIS1N_Pos                (9UL)                     /*!< OIS1N (Bit 9)                                         */
#define ePWM_CR2_OIS1N_Msk                (0x200UL)                 /*!< OIS1N (Bitfield-Mask: 0x01)                           */
#define ePWM_CR2_OIS1_Pos                 (8UL)                     /*!< OIS1 (Bit 8)                                          */
#define ePWM_CR2_OIS1_Msk                 (0x100UL)                 /*!< OIS1 (Bitfield-Mask: 0x01)                            */
#define ePWM_CR2_TI1S_Pos                 (7UL)                     /*!< TI1S (Bit 7)                                          */
#define ePWM_CR2_TI1S_Msk                 (0x80UL)                  /*!< TI1S (Bitfield-Mask: 0x01)                            */
#define ePWM_CR2_MMS_Pos                  (4UL)                     /*!< MMS (Bit 4)                                           */
#define ePWM_CR2_MMS_Msk                  (0x70UL)                  /*!< MMS (Bitfield-Mask: 0x07)                             */
#define ePWM_CR2_CCDS_Pos                 (3UL)                     /*!< CCDS (Bit 3)                                          */
#define ePWM_CR2_CCDS_Msk                 (0x8UL)                   /*!< CCDS (Bitfield-Mask: 0x01)                            */
#define ePWM_CR2_CCUS_Pos                 (2UL)                     /*!< CCUS (Bit 2)                                          */
#define ePWM_CR2_CCUS_Msk                 (0x4UL)                   /*!< CCUS (Bitfield-Mask: 0x01)                            */
#define ePWM_CR2_CCPC_Pos                 (0UL)                     /*!< CCPC (Bit 0)                                          */
#define ePWM_CR2_CCPC_Msk                 (0x1UL)                   /*!< CCPC (Bitfield-Mask: 0x01)                            */
/* =========================================================  SMCR  ========================================================== */
#define ePWM_SMCR_ETP_Pos                 (15UL)                    /*!< ETP (Bit 15)                                          */
#define ePWM_SMCR_ETP_Msk                 (0x8000UL)                /*!< ETP (Bitfield-Mask: 0x01)                             */
#define ePWM_SMCR_ECE_Pos                 (14UL)                    /*!< ECE (Bit 14)                                          */
#define ePWM_SMCR_ECE_Msk                 (0x4000UL)                /*!< ECE (Bitfield-Mask: 0x01)                             */
#define ePWM_SMCR_ETPS_Pos                (12UL)                    /*!< ETPS (Bit 12)                                         */
#define ePWM_SMCR_ETPS_Msk                (0x3000UL)                /*!< ETPS (Bitfield-Mask: 0x03)                            */
#define ePWM_SMCR_ETF_Pos                 (8UL)                     /*!< ETF (Bit 8)                                           */
#define ePWM_SMCR_ETF_Msk                 (0xf00UL)                 /*!< ETF (Bitfield-Mask: 0x0f)                             */
#define ePWM_SMCR_MSM_Pos                 (7UL)                     /*!< MSM (Bit 7)                                           */
#define ePWM_SMCR_MSM_Msk                 (0x80UL)                  /*!< MSM (Bitfield-Mask: 0x01)                             */
#define ePWM_SMCR_TS_Pos                  (4UL)                     /*!< TS (Bit 4)                                            */
#define ePWM_SMCR_TS_Msk                  (0x70UL)                  /*!< TS (Bitfield-Mask: 0x07)                              */
#define ePWM_SMCR_SMS_Pos                 (0UL)                     /*!< SMS (Bit 0)                                           */
#define ePWM_SMCR_SMS_Msk                 (0x7UL)                   /*!< SMS (Bitfield-Mask: 0x07)                             */
/* =========================================================  DIER  ========================================================== */
#define ePWM_DIER_TDE_Pos                 (14UL)                    /*!< TDE (Bit 14)                                          */
#define ePWM_DIER_TDE_Msk                 (0x4000UL)                /*!< TDE (Bitfield-Mask: 0x01)                             */
#define ePWM_DIER_COMDE_Pos               (13UL)                    /*!< COMDE (Bit 13)                                        */
#define ePWM_DIER_COMDE_Msk               (0x2000UL)                /*!< COMDE (Bitfield-Mask: 0x01)                           */
#define ePWM_DIER_CC4DE_Pos               (12UL)                    /*!< CC4DE (Bit 12)                                        */
#define ePWM_DIER_CC4DE_Msk               (0x1000UL)                /*!< CC4DE (Bitfield-Mask: 0x01)                           */
#define ePWM_DIER_CC3DE_Pos               (11UL)                    /*!< CC3DE (Bit 11)                                        */
#define ePWM_DIER_CC3DE_Msk               (0x800UL)                 /*!< CC3DE (Bitfield-Mask: 0x01)                           */
#define ePWM_DIER_CC2DE_Pos               (10UL)                    /*!< CC2DE (Bit 10)                                        */
#define ePWM_DIER_CC2DE_Msk               (0x400UL)                 /*!< CC2DE (Bitfield-Mask: 0x01)                           */
#define ePWM_DIER_CC1DE_Pos               (9UL)                     /*!< CC1DE (Bit 9)                                         */
#define ePWM_DIER_CC1DE_Msk               (0x200UL)                 /*!< CC1DE (Bitfield-Mask: 0x01)                           */
#define ePWM_DIER_UDE_Pos                 (8UL)                     /*!< UDE (Bit 8)                                           */
#define ePWM_DIER_UDE_Msk                 (0x100UL)                 /*!< UDE (Bitfield-Mask: 0x01)                             */
#define ePWM_DIER_TIE_Pos                 (6UL)                     /*!< TIE (Bit 6)                                           */
#define ePWM_DIER_TIE_Msk                 (0x40UL)                  /*!< TIE (Bitfield-Mask: 0x01)                             */
#define ePWM_DIER_CC4IE_Pos               (4UL)                     /*!< CC4IE (Bit 4)                                         */
#define ePWM_DIER_CC4IE_Msk               (0x10UL)                  /*!< CC4IE (Bitfield-Mask: 0x01)                           */
#define ePWM_DIER_CC3IE_Pos               (3UL)                     /*!< CC3IE (Bit 3)                                         */
#define ePWM_DIER_CC3IE_Msk               (0x8UL)                   /*!< CC3IE (Bitfield-Mask: 0x01)                           */
#define ePWM_DIER_CC2IE_Pos               (2UL)                     /*!< CC2IE (Bit 2)                                         */
#define ePWM_DIER_CC2IE_Msk               (0x4UL)                   /*!< CC2IE (Bitfield-Mask: 0x01)                           */
#define ePWM_DIER_CC1IE_Pos               (1UL)                     /*!< CC1IE (Bit 1)                                         */
#define ePWM_DIER_CC1IE_Msk               (0x2UL)                   /*!< CC1IE (Bitfield-Mask: 0x01)                           */
#define ePWM_DIER_UIE_Pos                 (0UL)                     /*!< UIE (Bit 0)                                           */
#define ePWM_DIER_UIE_Msk                 (0x1UL)                   /*!< UIE (Bitfield-Mask: 0x01)                             */
#define ePWM_DIER_BIE_Pos                 (7UL)                     /*!< BIE (Bit 7)                                           */
#define ePWM_DIER_BIE_Msk                 (0x80UL)                  /*!< BIE (Bitfield-Mask: 0x01)                             */
#define ePWM_DIER_COMIE_Pos               (5UL)                     /*!< COMIE (Bit 5)                                         */
#define ePWM_DIER_COMIE_Msk               (0x20UL)                  /*!< COMIE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  SR  =========================================================== */
#define ePWM_SR_CC4OF_Pos                 (12UL)                    /*!< CC4OF (Bit 12)                                        */
#define ePWM_SR_CC4OF_Msk                 (0x1000UL)                /*!< CC4OF (Bitfield-Mask: 0x01)                           */
#define ePWM_SR_CC3OF_Pos                 (11UL)                    /*!< CC3OF (Bit 11)                                        */
#define ePWM_SR_CC3OF_Msk                 (0x800UL)                 /*!< CC3OF (Bitfield-Mask: 0x01)                           */
#define ePWM_SR_CC2OF_Pos                 (10UL)                    /*!< CC2OF (Bit 10)                                        */
#define ePWM_SR_CC2OF_Msk                 (0x400UL)                 /*!< CC2OF (Bitfield-Mask: 0x01)                           */
#define ePWM_SR_CC1OF_Pos                 (9UL)                     /*!< CC1OF (Bit 9)                                         */
#define ePWM_SR_CC1OF_Msk                 (0x200UL)                 /*!< CC1OF (Bitfield-Mask: 0x01)                           */
#define ePWM_SR_BIF_Pos                   (7UL)                     /*!< BIF (Bit 7)                                           */
#define ePWM_SR_BIF_Msk                   (0x80UL)                  /*!< BIF (Bitfield-Mask: 0x01)                             */
#define ePWM_SR_TIF_Pos                   (6UL)                     /*!< TIF (Bit 6)                                           */
#define ePWM_SR_TIF_Msk                   (0x40UL)                  /*!< TIF (Bitfield-Mask: 0x01)                             */
#define ePWM_SR_COMIF_Pos                 (5UL)                     /*!< COMIF (Bit 5)                                         */
#define ePWM_SR_COMIF_Msk                 (0x20UL)                  /*!< COMIF (Bitfield-Mask: 0x01)                           */
#define ePWM_SR_CC4IF_Pos                 (4UL)                     /*!< CC4IF (Bit 4)                                         */
#define ePWM_SR_CC4IF_Msk                 (0x10UL)                  /*!< CC4IF (Bitfield-Mask: 0x01)                           */
#define ePWM_SR_CC3IF_Pos                 (3UL)                     /*!< CC3IF (Bit 3)                                         */
#define ePWM_SR_CC3IF_Msk                 (0x8UL)                   /*!< CC3IF (Bitfield-Mask: 0x01)                           */
#define ePWM_SR_CC2IF_Pos                 (2UL)                     /*!< CC2IF (Bit 2)                                         */
#define ePWM_SR_CC2IF_Msk                 (0x4UL)                   /*!< CC2IF (Bitfield-Mask: 0x01)                           */
#define ePWM_SR_CC1IF_Pos                 (1UL)                     /*!< CC1IF (Bit 1)                                         */
#define ePWM_SR_CC1IF_Msk                 (0x2UL)                   /*!< CC1IF (Bitfield-Mask: 0x01)                           */
#define ePWM_SR_UIF_Pos                   (0UL)                     /*!< UIF (Bit 0)                                           */
#define ePWM_SR_UIF_Msk                   (0x1UL)                   /*!< UIF (Bitfield-Mask: 0x01)                             */
/* ==========================================================  EGR  ========================================================== */
#define ePWM_EGR_BG_Pos                   (7UL)                     /*!< BG (Bit 7)                                            */
#define ePWM_EGR_BG_Msk                   (0x80UL)                  /*!< BG (Bitfield-Mask: 0x01)                              */
#define ePWM_EGR_TG_Pos                   (6UL)                     /*!< TG (Bit 6)                                            */
#define ePWM_EGR_TG_Msk                   (0x40UL)                  /*!< TG (Bitfield-Mask: 0x01)                              */
#define ePWM_EGR_COMG_Pos                 (5UL)                     /*!< COMG (Bit 5)                                          */
#define ePWM_EGR_COMG_Msk                 (0x20UL)                  /*!< COMG (Bitfield-Mask: 0x01)                            */
#define ePWM_EGR_CC4G_Pos                 (4UL)                     /*!< CC4G (Bit 4)                                          */
#define ePWM_EGR_CC4G_Msk                 (0x10UL)                  /*!< CC4G (Bitfield-Mask: 0x01)                            */
#define ePWM_EGR_CC3G_Pos                 (3UL)                     /*!< CC3G (Bit 3)                                          */
#define ePWM_EGR_CC3G_Msk                 (0x8UL)                   /*!< CC3G (Bitfield-Mask: 0x01)                            */
#define ePWM_EGR_CC2G_Pos                 (2UL)                     /*!< CC2G (Bit 2)                                          */
#define ePWM_EGR_CC2G_Msk                 (0x4UL)                   /*!< CC2G (Bitfield-Mask: 0x01)                            */
#define ePWM_EGR_CC1G_Pos                 (1UL)                     /*!< CC1G (Bit 1)                                          */
#define ePWM_EGR_CC1G_Msk                 (0x2UL)                   /*!< CC1G (Bitfield-Mask: 0x01)                            */
#define ePWM_EGR_UG_Pos                   (0UL)                     /*!< UG (Bit 0)                                            */
#define ePWM_EGR_UG_Msk                   (0x1UL)                   /*!< UG (Bitfield-Mask: 0x01)                              */
/* =========================================================  CCMR1  ========================================================= */
#define ePWM_CCMR1_OC2CE_Pos              (15UL)                    /*!< OC2CE (Bit 15)                                        */
#define ePWM_CCMR1_OC2CE_Msk              (0x8000UL)                /*!< OC2CE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCMR1_OC2M_Pos               (12UL)                    /*!< OC2M (Bit 12)                                         */
#define ePWM_CCMR1_OC2M_Msk               (0x7000UL)                /*!< OC2M (Bitfield-Mask: 0x07)                            */
#define ePWM_CCMR1_OC2PE_Pos              (11UL)                    /*!< OC2PE (Bit 11)                                        */
#define ePWM_CCMR1_OC2PE_Msk              (0x800UL)                 /*!< OC2PE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCMR1_OC2FE_Pos              (10UL)                    /*!< OC2FE (Bit 10)                                        */
#define ePWM_CCMR1_OC2FE_Msk              (0x400UL)                 /*!< OC2FE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCMR1_CC2S_Pos               (8UL)                     /*!< CC2S (Bit 8)                                          */
#define ePWM_CCMR1_CC2S_Msk               (0x300UL)                 /*!< CC2S (Bitfield-Mask: 0x03)                            */
#define ePWM_CCMR1_OC1CE_Pos              (7UL)                     /*!< OC1CE (Bit 7)                                         */
#define ePWM_CCMR1_OC1CE_Msk              (0x80UL)                  /*!< OC1CE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCMR1_OC1M_Pos               (4UL)                     /*!< OC1M (Bit 4)                                          */
#define ePWM_CCMR1_OC1M_Msk               (0x70UL)                  /*!< OC1M (Bitfield-Mask: 0x07)                            */
#define ePWM_CCMR1_OC1PE_Pos              (3UL)                     /*!< OC1PE (Bit 3)                                         */
#define ePWM_CCMR1_OC1PE_Msk              (0x8UL)                   /*!< OC1PE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCMR1_OC1FE_Pos              (2UL)                     /*!< OC1FE (Bit 2)                                         */
#define ePWM_CCMR1_OC1FE_Msk              (0x4UL)                   /*!< OC1FE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCMR1_CC1S_Pos               (0UL)                     /*!< CC1S (Bit 0)                                          */
#define ePWM_CCMR1_CC1S_Msk               (0x3UL)                   /*!< CC1S (Bitfield-Mask: 0x03)                            */
/* =========================================================  CCMR2  ========================================================= */
#define ePWM_CCMR2_OC4CE_Pos              (15UL)                    /*!< OC4CE (Bit 15)                                        */
#define ePWM_CCMR2_OC4CE_Msk              (0x8000UL)                /*!< OC4CE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCMR2_OC4M_Pos               (12UL)                    /*!< OC4M (Bit 12)                                         */
#define ePWM_CCMR2_OC4M_Msk               (0x7000UL)                /*!< OC4M (Bitfield-Mask: 0x07)                            */
#define ePWM_CCMR2_OC4PE_Pos              (11UL)                    /*!< OC4PE (Bit 11)                                        */
#define ePWM_CCMR2_OC4PE_Msk              (0x800UL)                 /*!< OC4PE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCMR2_OC4FE_Pos              (10UL)                    /*!< OC4FE (Bit 10)                                        */
#define ePWM_CCMR2_OC4FE_Msk              (0x400UL)                 /*!< OC4FE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCMR2_CC4S_Pos               (8UL)                     /*!< CC4S (Bit 8)                                          */
#define ePWM_CCMR2_CC4S_Msk               (0x300UL)                 /*!< CC4S (Bitfield-Mask: 0x03)                            */
#define ePWM_CCMR2_OC3CE_Pos              (7UL)                     /*!< OC3CE (Bit 7)                                         */
#define ePWM_CCMR2_OC3CE_Msk              (0x80UL)                  /*!< OC3CE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCMR2_OC3M_Pos               (4UL)                     /*!< OC3M (Bit 4)                                          */
#define ePWM_CCMR2_OC3M_Msk               (0x70UL)                  /*!< OC3M (Bitfield-Mask: 0x07)                            */
#define ePWM_CCMR2_OC3PE_Pos              (3UL)                     /*!< OC3PE (Bit 3)                                         */
#define ePWM_CCMR2_OC3PE_Msk              (0x8UL)                   /*!< OC3PE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCMR2_OC3FE_Pos              (2UL)                     /*!< OC3FE (Bit 2)                                         */
#define ePWM_CCMR2_OC3FE_Msk              (0x4UL)                   /*!< OC3FE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCMR2_CC3S_Pos               (0UL)                     /*!< CC3S (Bit 0)                                          */
#define ePWM_CCMR2_CC3S_Msk               (0x3UL)                   /*!< CC3S (Bitfield-Mask: 0x03)                            */
/* =========================================================  CCER  ========================================================== */
#define ePWM_CCER_CC4P_Pos                (13UL)                    /*!< CC4P (Bit 13)                                         */
#define ePWM_CCER_CC4P_Msk                (0x2000UL)                /*!< CC4P (Bitfield-Mask: 0x01)                            */
#define ePWM_CCER_CC4E_Pos                (12UL)                    /*!< CC4E (Bit 12)                                         */
#define ePWM_CCER_CC4E_Msk                (0x1000UL)                /*!< CC4E (Bitfield-Mask: 0x01)                            */
#define ePWM_CCER_CC3NP_Pos               (11UL)                    /*!< CC3NP (Bit 11)                                        */
#define ePWM_CCER_CC3NP_Msk               (0x800UL)                 /*!< CC3NP (Bitfield-Mask: 0x01)                           */
#define ePWM_CCER_CC3NE_Pos               (10UL)                    /*!< CC3NE (Bit 10)                                        */
#define ePWM_CCER_CC3NE_Msk               (0x400UL)                 /*!< CC3NE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCER_CC3P_Pos                (9UL)                     /*!< CC3P (Bit 9)                                          */
#define ePWM_CCER_CC3P_Msk                (0x200UL)                 /*!< CC3P (Bitfield-Mask: 0x01)                            */
#define ePWM_CCER_CC3E_Pos                (8UL)                     /*!< CC3E (Bit 8)                                          */
#define ePWM_CCER_CC3E_Msk                (0x100UL)                 /*!< CC3E (Bitfield-Mask: 0x01)                            */
#define ePWM_CCER_CC2NP_Pos               (7UL)                     /*!< CC2NP (Bit 7)                                         */
#define ePWM_CCER_CC2NP_Msk               (0x80UL)                  /*!< CC2NP (Bitfield-Mask: 0x01)                           */
#define ePWM_CCER_CC2NE_Pos               (6UL)                     /*!< CC2NE (Bit 6)                                         */
#define ePWM_CCER_CC2NE_Msk               (0x40UL)                  /*!< CC2NE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCER_CC2P_Pos                (5UL)                     /*!< CC2P (Bit 5)                                          */
#define ePWM_CCER_CC2P_Msk                (0x20UL)                  /*!< CC2P (Bitfield-Mask: 0x01)                            */
#define ePWM_CCER_CC2E_Pos                (4UL)                     /*!< CC2E (Bit 4)                                          */
#define ePWM_CCER_CC2E_Msk                (0x10UL)                  /*!< CC2E (Bitfield-Mask: 0x01)                            */
#define ePWM_CCER_CC1NP_Pos               (3UL)                     /*!< CC1NP (Bit 3)                                         */
#define ePWM_CCER_CC1NP_Msk               (0x8UL)                   /*!< CC1NP (Bitfield-Mask: 0x01)                           */
#define ePWM_CCER_CC1NE_Pos               (2UL)                     /*!< CC1NE (Bit 2)                                         */
#define ePWM_CCER_CC1NE_Msk               (0x4UL)                   /*!< CC1NE (Bitfield-Mask: 0x01)                           */
#define ePWM_CCER_CC1P_Pos                (1UL)                     /*!< CC1P (Bit 1)                                          */
#define ePWM_CCER_CC1P_Msk                (0x2UL)                   /*!< CC1P (Bitfield-Mask: 0x01)                            */
#define ePWM_CCER_CC1E_Pos                (0UL)                     /*!< CC1E (Bit 0)                                          */
#define ePWM_CCER_CC1E_Msk                (0x1UL)                   /*!< CC1E (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CNT  ========================================================== */
#define ePWM_CNT_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define ePWM_CNT_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  PSC  ========================================================== */
#define ePWM_PSC_PSC_Pos                  (0UL)                     /*!< PSC (Bit 0)                                           */
#define ePWM_PSC_PSC_Msk                  (0xffffUL)                /*!< PSC (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  ARR  ========================================================== */
#define ePWM_ARR_ARR_Pos                  (0UL)                     /*!< ARR (Bit 0)                                           */
#define ePWM_ARR_ARR_Msk                  (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CCR1  ========================================================== */
#define ePWM_CCR1_CCR1_Pos                (0UL)                     /*!< CCR1 (Bit 0)                                          */
#define ePWM_CCR1_CCR1_Msk                (0xffffUL)                /*!< CCR1 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR2  ========================================================== */
#define ePWM_CCR2_CCR2_Pos                (0UL)                     /*!< CCR2 (Bit 0)                                          */
#define ePWM_CCR2_CCR2_Msk                (0xffffUL)                /*!< CCR2 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR3  ========================================================== */
#define ePWM_CCR3_CCR3_Pos                (0UL)                     /*!< CCR3 (Bit 0)                                          */
#define ePWM_CCR3_CCR3_Msk                (0xffffUL)                /*!< CCR3 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR4  ========================================================== */
#define ePWM_CCR4_CCR4_Pos                (0UL)                     /*!< CCR4 (Bit 0)                                          */
#define ePWM_CCR4_CCR4_Msk                (0xffffUL)                /*!< CCR4 (Bitfield-Mask: 0xffff)                          */
/* ==========================================================  DCR  ========================================================== */
#define ePWM_DCR_DBL_Pos                  (8UL)                     /*!< DBL (Bit 8)                                           */
#define ePWM_DCR_DBL_Msk                  (0x1f00UL)                /*!< DBL (Bitfield-Mask: 0x1f)                             */
#define ePWM_DCR_DBA_Pos                  (0UL)                     /*!< DBA (Bit 0)                                           */
#define ePWM_DCR_DBA_Msk                  (0x1fUL)                  /*!< DBA (Bitfield-Mask: 0x1f)                             */
/* =========================================================  DMAR  ========================================================== */
#define ePWM_DMAR_DMAB_Pos                (0UL)                     /*!< DMAB (Bit 0)                                          */
#define ePWM_DMAR_DMAB_Msk                (0xffffUL)                /*!< DMAB (Bitfield-Mask: 0xffff)                          */
/* ==========================================================  RCR  ========================================================== */
#define ePWM_RCR_REP_CMP5_Pos             (24UL)                    /*!< REP_CMP5 (Bit 24)                                     */
#define ePWM_RCR_REP_CMP5_Msk             (0xff000000UL)            /*!< REP_CMP5 (Bitfield-Mask: 0xff)                        */
#define ePWM_RCR_REP_CMP4_Pos             (16UL)                    /*!< REP_CMP4 (Bit 16)                                     */
#define ePWM_RCR_REP_CMP4_Msk             (0xff0000UL)              /*!< REP_CMP4 (Bitfield-Mask: 0xff)                        */
#define ePWM_RCR_REP_CMP03_Pos            (8UL)                     /*!< REP_CMP03 (Bit 8)                                     */
#define ePWM_RCR_REP_CMP03_Msk            (0xff00UL)                /*!< REP_CMP03 (Bitfield-Mask: 0xff)                       */
#define ePWM_RCR_REP_Pos                  (0UL)                     /*!< REP (Bit 0)                                           */
#define ePWM_RCR_REP_Msk                  (0xffUL)                  /*!< REP (Bitfield-Mask: 0xff)                             */
/* =========================================================  BDTR  ========================================================== */
#define ePWM_BDTR_MOE_Pos                 (15UL)                    /*!< MOE (Bit 15)                                          */
#define ePWM_BDTR_MOE_Msk                 (0x8000UL)                /*!< MOE (Bitfield-Mask: 0x01)                             */
#define ePWM_BDTR_AOE_Pos                 (14UL)                    /*!< AOE (Bit 14)                                          */
#define ePWM_BDTR_AOE_Msk                 (0x4000UL)                /*!< AOE (Bitfield-Mask: 0x01)                             */
#define ePWM_BDTR_BKP_Pos                 (13UL)                    /*!< BKP (Bit 13)                                          */
#define ePWM_BDTR_BKP_Msk                 (0x2000UL)                /*!< BKP (Bitfield-Mask: 0x01)                             */
#define ePWM_BDTR_BKE_Pos                 (12UL)                    /*!< BKE (Bit 12)                                          */
#define ePWM_BDTR_BKE_Msk                 (0x1000UL)                /*!< BKE (Bitfield-Mask: 0x01)                             */
#define ePWM_BDTR_OSSR_Pos                (11UL)                    /*!< OSSR (Bit 11)                                         */
#define ePWM_BDTR_OSSR_Msk                (0x800UL)                 /*!< OSSR (Bitfield-Mask: 0x01)                            */
#define ePWM_BDTR_OSSI_Pos                (10UL)                    /*!< OSSI (Bit 10)                                         */
#define ePWM_BDTR_OSSI_Msk                (0x400UL)                 /*!< OSSI (Bitfield-Mask: 0x01)                            */
#define ePWM_BDTR_LOCK_Pos                (8UL)                     /*!< LOCK (Bit 8)                                          */
#define ePWM_BDTR_LOCK_Msk                (0x300UL)                 /*!< LOCK (Bitfield-Mask: 0x03)                            */
#define ePWM_BDTR_DTG_Pos                 (0UL)                     /*!< DTG (Bit 0)                                           */
#define ePWM_BDTR_DTG_Msk                 (0xffUL)                  /*!< DTG (Bitfield-Mask: 0xff)                             */
/* =========================================================  CMP01  ========================================================= */
#define ePWM_CMP01_CMP1_Pos               (16UL)                    /*!< CMP1 (Bit 16)                                         */
#define ePWM_CMP01_CMP1_Msk               (0xffff0000UL)            /*!< CMP1 (Bitfield-Mask: 0xffff)                          */
#define ePWM_CMP01_CMP0_Pos               (0UL)                     /*!< CMP0 (Bit 0)                                          */
#define ePWM_CMP01_CMP0_Msk               (0xffffUL)                /*!< CMP0 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CMP23  ========================================================= */
#define ePWM_CMP23_CMP3_Pos               (16UL)                    /*!< CMP3 (Bit 16)                                         */
#define ePWM_CMP23_CMP3_Msk               (0xffff0000UL)            /*!< CMP3 (Bitfield-Mask: 0xffff)                          */
#define ePWM_CMP23_CMP2_Pos               (0UL)                     /*!< CMP2 (Bit 0)                                          */
#define ePWM_CMP23_CMP2_Msk               (0xffffUL)                /*!< CMP2 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CMP45  ========================================================= */
#define ePWM_CMP45_CMP5_Pos               (16UL)                    /*!< CMP5 (Bit 16)                                         */
#define ePWM_CMP45_CMP5_Msk               (0xffff0000UL)            /*!< CMP5 (Bitfield-Mask: 0xffff)                          */
#define ePWM_CMP45_CMP4_Pos               (0UL)                     /*!< CMP4 (Bit 0)                                          */
#define ePWM_CMP45_CMP4_Msk               (0xffffUL)                /*!< CMP4 (Bitfield-Mask: 0xffff)                          */


/* =========================================================================================================================== */
/* ================                                          SYSCFG                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  CHIPID  ========================================================= */
#define SYSCFG_CHIPID_CHIPID_Pos          (0UL)                     /*!< CHIPID (Bit 0)                                        */
#define SYSCFG_CHIPID_CHIPID_Msk          (0xffffffffUL)            /*!< CHIPID (Bitfield-Mask: 0xffffffff)                    */
/* ==========================================================  RDP  ========================================================== */
#define SYSCFG_RDP_RDP_Pos                (0UL)                     /*!< RDP (Bit 0)                                           */
#define SYSCFG_RDP_RDP_Msk                (0x1UL)                   /*!< RDP (Bitfield-Mask: 0x01)                             */
/* ========================================================  RAM0IER  ======================================================== */
#define SYSCFG_RAM0IER_EN_Pos             (0UL)                     /*!< EN (Bit 0)                                            */
#define SYSCFG_RAM0IER_EN_Msk             (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ========================================================  RAM0ISR  ======================================================== */
#define SYSCFG_RAM0ISR_ERR_Pos            (0UL)                     /*!< ERR (Bit 0)                                           */
#define SYSCFG_RAM0ISR_ERR_Msk            (0x3UL)                   /*!< ERR (Bitfield-Mask: 0x03)                             */
/* =======================================================  RAM0ICLR  ======================================================== */
#define SYSCFG_RAM0ICLR_ERRCLR_Pos        (0UL)                     /*!< ERRCLR (Bit 0)                                        */
#define SYSCFG_RAM0ICLR_ERRCLR_Msk        (0x1UL)                   /*!< ERRCLR (Bitfield-Mask: 0x01)                          */
/* =======================================================  RAM0SYND  ======================================================== */
#define SYSCFG_RAM0SYND_SYND_Pos          (0UL)                     /*!< SYND (Bit 0)                                          */
#define SYSCFG_RAM0SYND_SYND_Msk          (0x7fUL)                  /*!< SYND (Bitfield-Mask: 0x7f)                            */
/* =======================================================  RAM0INJL  ======================================================== */
#define SYSCFG_RAM0INJL_INJL_Pos          (0UL)                     /*!< INJL (Bit 0)                                          */
#define SYSCFG_RAM0INJL_INJL_Msk          (0xffffffffUL)            /*!< INJL (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  RAM0INJH  ======================================================== */
#define SYSCFG_RAM0INJH_INJH_Pos          (0UL)                     /*!< INJH (Bit 0)                                          */
#define SYSCFG_RAM0INJH_INJH_Msk          (0x7fUL)                  /*!< INJH (Bitfield-Mask: 0x7f)                            */
/* ========================================================  RAM1IER  ======================================================== */
#define SYSCFG_RAM1IER_EN_Pos             (0UL)                     /*!< EN (Bit 0)                                            */
#define SYSCFG_RAM1IER_EN_Msk             (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ========================================================  RAM1ISR  ======================================================== */
#define SYSCFG_RAM1ISR_ERR_Pos            (0UL)                     /*!< ERR (Bit 0)                                           */
#define SYSCFG_RAM1ISR_ERR_Msk            (0x3UL)                   /*!< ERR (Bitfield-Mask: 0x03)                             */
/* =======================================================  RAM1ICLR  ======================================================== */
#define SYSCFG_RAM1ICLR_ERRCLR_Pos        (0UL)                     /*!< ERRCLR (Bit 0)                                        */
#define SYSCFG_RAM1ICLR_ERRCLR_Msk        (0x1UL)                   /*!< ERRCLR (Bitfield-Mask: 0x01)                          */
/* =======================================================  RAM1SYND  ======================================================== */
#define SYSCFG_RAM1SYND_SYND_Pos          (0UL)                     /*!< SYND (Bit 0)                                          */
#define SYSCFG_RAM1SYND_SYND_Msk          (0x7fUL)                  /*!< SYND (Bitfield-Mask: 0x7f)                            */
/* =======================================================  RAM1INJL  ======================================================== */
#define SYSCFG_RAM1INJL_INJL_Pos          (0UL)                     /*!< INJL (Bit 0)                                          */
#define SYSCFG_RAM1INJL_INJL_Msk          (0xffffffffUL)            /*!< INJL (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  RAM1INJH  ======================================================== */
#define SYSCFG_RAM1INJH_INJH_Pos          (0UL)                     /*!< INJH (Bit 0)                                          */
#define SYSCFG_RAM1INJH_INJH_Msk          (0x7fUL)                  /*!< INJH (Bitfield-Mask: 0x7f)                            */
/* ========================================================  ADC0TRG  ======================================================== */
#define SYSCFG_ADC0TRG_ePWM_CMP0_Pos      (0UL)                     /*!< ePWM_CMP0 (Bit 0)                                     */
#define SYSCFG_ADC0TRG_ePWM_CMP0_Msk      (0x1UL)                   /*!< ePWM_CMP0 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC0TRG_ePWM_CMP1_Pos      (1UL)                     /*!< ePWM_CMP1 (Bit 1)                                     */
#define SYSCFG_ADC0TRG_ePWM_CMP1_Msk      (0x2UL)                   /*!< ePWM_CMP1 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC0TRG_ePWM_CMP2_Pos      (2UL)                     /*!< ePWM_CMP2 (Bit 2)                                     */
#define SYSCFG_ADC0TRG_ePWM_CMP2_Msk      (0x4UL)                   /*!< ePWM_CMP2 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC0TRG_ePWM_CMP3_Pos      (3UL)                     /*!< ePWM_CMP3 (Bit 3)                                     */
#define SYSCFG_ADC0TRG_ePWM_CMP3_Msk      (0x8UL)                   /*!< ePWM_CMP3 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC0TRG_ePWM_CMP4_Pos      (4UL)                     /*!< ePWM_CMP4 (Bit 4)                                     */
#define SYSCFG_ADC0TRG_ePWM_CMP4_Msk      (0x10UL)                  /*!< ePWM_CMP4 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC0TRG_ePWM_CMP5_Pos      (5UL)                     /*!< ePWM_CMP5 (Bit 5)                                     */
#define SYSCFG_ADC0TRG_ePWM_CMP5_Msk      (0x20UL)                  /*!< ePWM_CMP5 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC0TRG_ePWM_TRGO_Pos      (6UL)                     /*!< ePWM_TRGO (Bit 6)                                     */
#define SYSCFG_ADC0TRG_ePWM_TRGO_Msk      (0x40UL)                  /*!< ePWM_TRGO (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC0TRG_ePWM_OC0_Pos       (7UL)                     /*!< ePWM_OC0 (Bit 7)                                      */
#define SYSCFG_ADC0TRG_ePWM_OC0_Msk       (0x80UL)                  /*!< ePWM_OC0 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_ADC0TRG_ePWM_OC1_Pos       (8UL)                     /*!< ePWM_OC1 (Bit 8)                                      */
#define SYSCFG_ADC0TRG_ePWM_OC1_Msk       (0x100UL)                 /*!< ePWM_OC1 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_ADC0TRG_ePWM_OC2_Pos       (9UL)                     /*!< ePWM_OC2 (Bit 9)                                      */
#define SYSCFG_ADC0TRG_ePWM_OC2_Msk       (0x200UL)                 /*!< ePWM_OC2 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_ADC0TRG_ePWM_OC3_Pos       (10UL)                    /*!< ePWM_OC3 (Bit 10)                                     */
#define SYSCFG_ADC0TRG_ePWM_OC3_Msk       (0x400UL)                 /*!< ePWM_OC3 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_ADC0TRG_TIM0_UP_Pos        (11UL)                    /*!< TIM0_UP (Bit 11)                                      */
#define SYSCFG_ADC0TRG_TIM0_UP_Msk        (0x800UL)                 /*!< TIM0_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_ADC0TRG_TIM1_UP_Pos        (12UL)                    /*!< TIM1_UP (Bit 12)                                      */
#define SYSCFG_ADC0TRG_TIM1_UP_Msk        (0x1000UL)                /*!< TIM1_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_ADC0TRG_TIM2_UP_Pos        (13UL)                    /*!< TIM2_UP (Bit 13)                                      */
#define SYSCFG_ADC0TRG_TIM2_UP_Msk        (0x2000UL)                /*!< TIM2_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_ADC0TRG_eDIAG_CMP_Pos      (14UL)                    /*!< eDIAG_CMP (Bit 14)                                    */
#define SYSCFG_ADC0TRG_eDIAG_CMP_Msk      (0x4000UL)                /*!< eDIAG_CMP (Bitfield-Mask: 0x01)                       */
/* ========================================================  ADC1TRG  ======================================================== */
#define SYSCFG_ADC1TRG_ePWM_CMP0_Pos      (0UL)                     /*!< ePWM_CMP0 (Bit 0)                                     */
#define SYSCFG_ADC1TRG_ePWM_CMP0_Msk      (0x1UL)                   /*!< ePWM_CMP0 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC1TRG_ePWM_CMP1_Pos      (1UL)                     /*!< ePWM_CMP1 (Bit 1)                                     */
#define SYSCFG_ADC1TRG_ePWM_CMP1_Msk      (0x2UL)                   /*!< ePWM_CMP1 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC1TRG_ePWM_CMP2_Pos      (2UL)                     /*!< ePWM_CMP2 (Bit 2)                                     */
#define SYSCFG_ADC1TRG_ePWM_CMP2_Msk      (0x4UL)                   /*!< ePWM_CMP2 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC1TRG_ePWM_CMP3_Pos      (3UL)                     /*!< ePWM_CMP3 (Bit 3)                                     */
#define SYSCFG_ADC1TRG_ePWM_CMP3_Msk      (0x8UL)                   /*!< ePWM_CMP3 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC1TRG_ePWM_CMP4_Pos      (4UL)                     /*!< ePWM_CMP4 (Bit 4)                                     */
#define SYSCFG_ADC1TRG_ePWM_CMP4_Msk      (0x10UL)                  /*!< ePWM_CMP4 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC1TRG_ePWM_CMP5_Pos      (5UL)                     /*!< ePWM_CMP5 (Bit 5)                                     */
#define SYSCFG_ADC1TRG_ePWM_CMP5_Msk      (0x20UL)                  /*!< ePWM_CMP5 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC1TRG_ePWM_TRGO_Pos      (6UL)                     /*!< ePWM_TRGO (Bit 6)                                     */
#define SYSCFG_ADC1TRG_ePWM_TRGO_Msk      (0x40UL)                  /*!< ePWM_TRGO (Bitfield-Mask: 0x01)                       */
#define SYSCFG_ADC1TRG_ePWM_OC0_Pos       (7UL)                     /*!< ePWM_OC0 (Bit 7)                                      */
#define SYSCFG_ADC1TRG_ePWM_OC0_Msk       (0x80UL)                  /*!< ePWM_OC0 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_ADC1TRG_ePWM_OC1_Pos       (8UL)                     /*!< ePWM_OC1 (Bit 8)                                      */
#define SYSCFG_ADC1TRG_ePWM_OC1_Msk       (0x100UL)                 /*!< ePWM_OC1 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_ADC1TRG_ePWM_OC2_Pos       (9UL)                     /*!< ePWM_OC2 (Bit 9)                                      */
#define SYSCFG_ADC1TRG_ePWM_OC2_Msk       (0x200UL)                 /*!< ePWM_OC2 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_ADC1TRG_ePWM_OC3_Pos       (10UL)                    /*!< ePWM_OC3 (Bit 10)                                     */
#define SYSCFG_ADC1TRG_ePWM_OC3_Msk       (0x400UL)                 /*!< ePWM_OC3 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_ADC1TRG_TIM0_UP_Pos        (11UL)                    /*!< TIM0_UP (Bit 11)                                      */
#define SYSCFG_ADC1TRG_TIM0_UP_Msk        (0x800UL)                 /*!< TIM0_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_ADC1TRG_TIM1_UP_Pos        (12UL)                    /*!< TIM1_UP (Bit 12)                                      */
#define SYSCFG_ADC1TRG_TIM1_UP_Msk        (0x1000UL)                /*!< TIM1_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_ADC1TRG_TIM2_UP_Pos        (13UL)                    /*!< TIM2_UP (Bit 13)                                      */
#define SYSCFG_ADC1TRG_TIM2_UP_Msk        (0x2000UL)                /*!< TIM2_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_ADC1TRG_eDIAG_CMP_Pos      (14UL)                    /*!< eDIAG_CMP (Bit 14)                                    */
#define SYSCFG_ADC1TRG_eDIAG_CMP_Msk      (0x4000UL)                /*!< eDIAG_CMP (Bitfield-Mask: 0x01)                       */
/* ========================================================  TIM0TRG  ======================================================== */
#define SYSCFG_TIM0TRG_ePWM_CMP0_Pos      (0UL)                     /*!< ePWM_CMP0 (Bit 0)                                     */
#define SYSCFG_TIM0TRG_ePWM_CMP0_Msk      (0x1UL)                   /*!< ePWM_CMP0 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM0TRG_ePWM_CMP1_Pos      (1UL)                     /*!< ePWM_CMP1 (Bit 1)                                     */
#define SYSCFG_TIM0TRG_ePWM_CMP1_Msk      (0x2UL)                   /*!< ePWM_CMP1 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM0TRG_ePWM_CMP2_Pos      (2UL)                     /*!< ePWM_CMP2 (Bit 2)                                     */
#define SYSCFG_TIM0TRG_ePWM_CMP2_Msk      (0x4UL)                   /*!< ePWM_CMP2 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM0TRG_ePWM_CMP3_Pos      (3UL)                     /*!< ePWM_CMP3 (Bit 3)                                     */
#define SYSCFG_TIM0TRG_ePWM_CMP3_Msk      (0x8UL)                   /*!< ePWM_CMP3 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM0TRG_ePWM_CMP4_Pos      (4UL)                     /*!< ePWM_CMP4 (Bit 4)                                     */
#define SYSCFG_TIM0TRG_ePWM_CMP4_Msk      (0x10UL)                  /*!< ePWM_CMP4 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM0TRG_ePWM_CMP5_Pos      (5UL)                     /*!< ePWM_CMP5 (Bit 5)                                     */
#define SYSCFG_TIM0TRG_ePWM_CMP5_Msk      (0x20UL)                  /*!< ePWM_CMP5 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM0TRG_ePWM_TRGO_Pos      (6UL)                     /*!< ePWM_TRGO (Bit 6)                                     */
#define SYSCFG_TIM0TRG_ePWM_TRGO_Msk      (0x40UL)                  /*!< ePWM_TRGO (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM0TRG_ePWM_OC0_Pos       (7UL)                     /*!< ePWM_OC0 (Bit 7)                                      */
#define SYSCFG_TIM0TRG_ePWM_OC0_Msk       (0x80UL)                  /*!< ePWM_OC0 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TIM0TRG_ePWM_OC1_Pos       (8UL)                     /*!< ePWM_OC1 (Bit 8)                                      */
#define SYSCFG_TIM0TRG_ePWM_OC1_Msk       (0x100UL)                 /*!< ePWM_OC1 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TIM0TRG_ePWM_OC2_Pos       (9UL)                     /*!< ePWM_OC2 (Bit 9)                                      */
#define SYSCFG_TIM0TRG_ePWM_OC2_Msk       (0x200UL)                 /*!< ePWM_OC2 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TIM0TRG_ePWM_OC3_Pos       (10UL)                    /*!< ePWM_OC3 (Bit 10)                                     */
#define SYSCFG_TIM0TRG_ePWM_OC3_Msk       (0x400UL)                 /*!< ePWM_OC3 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TIM0TRG_TIM0_UP_Pos        (11UL)                    /*!< TIM0_UP (Bit 11)                                      */
#define SYSCFG_TIM0TRG_TIM0_UP_Msk        (0x800UL)                 /*!< TIM0_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TIM0TRG_TIM1_UP_Pos        (12UL)                    /*!< TIM1_UP (Bit 12)                                      */
#define SYSCFG_TIM0TRG_TIM1_UP_Msk        (0x1000UL)                /*!< TIM1_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TIM0TRG_TIM2_UP_Pos        (13UL)                    /*!< TIM2_UP (Bit 13)                                      */
#define SYSCFG_TIM0TRG_TIM2_UP_Msk        (0x2000UL)                /*!< TIM2_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TIM0TRG_eDIAG_CMP_Pos      (14UL)                    /*!< eDIAG_CMP (Bit 14)                                    */
#define SYSCFG_TIM0TRG_eDIAG_CMP_Msk      (0x4000UL)                /*!< eDIAG_CMP (Bitfield-Mask: 0x01)                       */
/* ========================================================  TIM1TRG  ======================================================== */
#define SYSCFG_TIM1TRG_ePWM_CMP0_Pos      (0UL)                     /*!< ePWM_CMP0 (Bit 0)                                     */
#define SYSCFG_TIM1TRG_ePWM_CMP0_Msk      (0x1UL)                   /*!< ePWM_CMP0 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM1TRG_ePWM_CMP1_Pos      (1UL)                     /*!< ePWM_CMP1 (Bit 1)                                     */
#define SYSCFG_TIM1TRG_ePWM_CMP1_Msk      (0x2UL)                   /*!< ePWM_CMP1 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM1TRG_ePWM_CMP2_Pos      (2UL)                     /*!< ePWM_CMP2 (Bit 2)                                     */
#define SYSCFG_TIM1TRG_ePWM_CMP2_Msk      (0x4UL)                   /*!< ePWM_CMP2 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM1TRG_ePWM_CMP3_Pos      (3UL)                     /*!< ePWM_CMP3 (Bit 3)                                     */
#define SYSCFG_TIM1TRG_ePWM_CMP3_Msk      (0x8UL)                   /*!< ePWM_CMP3 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM1TRG_ePWM_CMP4_Pos      (4UL)                     /*!< ePWM_CMP4 (Bit 4)                                     */
#define SYSCFG_TIM1TRG_ePWM_CMP4_Msk      (0x10UL)                  /*!< ePWM_CMP4 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM1TRG_ePWM_CMP5_Pos      (5UL)                     /*!< ePWM_CMP5 (Bit 5)                                     */
#define SYSCFG_TIM1TRG_ePWM_CMP5_Msk      (0x20UL)                  /*!< ePWM_CMP5 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM1TRG_ePWM_TRGO_Pos      (6UL)                     /*!< ePWM_TRGO (Bit 6)                                     */
#define SYSCFG_TIM1TRG_ePWM_TRGO_Msk      (0x40UL)                  /*!< ePWM_TRGO (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM1TRG_ePWM_OC0_Pos       (7UL)                     /*!< ePWM_OC0 (Bit 7)                                      */
#define SYSCFG_TIM1TRG_ePWM_OC0_Msk       (0x80UL)                  /*!< ePWM_OC0 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TIM1TRG_ePWM_OC1_Pos       (8UL)                     /*!< ePWM_OC1 (Bit 8)                                      */
#define SYSCFG_TIM1TRG_ePWM_OC1_Msk       (0x100UL)                 /*!< ePWM_OC1 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TIM1TRG_ePWM_OC2_Pos       (9UL)                     /*!< ePWM_OC2 (Bit 9)                                      */
#define SYSCFG_TIM1TRG_ePWM_OC2_Msk       (0x200UL)                 /*!< ePWM_OC2 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TIM1TRG_ePWM_OC3_Pos       (10UL)                    /*!< ePWM_OC3 (Bit 10)                                     */
#define SYSCFG_TIM1TRG_ePWM_OC3_Msk       (0x400UL)                 /*!< ePWM_OC3 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TIM1TRG_TIM0_UP_Pos        (11UL)                    /*!< TIM0_UP (Bit 11)                                      */
#define SYSCFG_TIM1TRG_TIM0_UP_Msk        (0x800UL)                 /*!< TIM0_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TIM1TRG_TIM1_UP_Pos        (12UL)                    /*!< TIM1_UP (Bit 12)                                      */
#define SYSCFG_TIM1TRG_TIM1_UP_Msk        (0x1000UL)                /*!< TIM1_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TIM1TRG_TIM2_UP_Pos        (13UL)                    /*!< TIM2_UP (Bit 13)                                      */
#define SYSCFG_TIM1TRG_TIM2_UP_Msk        (0x2000UL)                /*!< TIM2_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TIM1TRG_eDIAG_CMP_Pos      (14UL)                    /*!< eDIAG_CMP (Bit 14)                                    */
#define SYSCFG_TIM1TRG_eDIAG_CMP_Msk      (0x4000UL)                /*!< eDIAG_CMP (Bitfield-Mask: 0x01)                       */
/* ========================================================  TIM2TRG  ======================================================== */
#define SYSCFG_TIM2TRG_ePWM_CMP0_Pos      (0UL)                     /*!< ePWM_CMP0 (Bit 0)                                     */
#define SYSCFG_TIM2TRG_ePWM_CMP0_Msk      (0x1UL)                   /*!< ePWM_CMP0 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM2TRG_ePWM_CMP1_Pos      (1UL)                     /*!< ePWM_CMP1 (Bit 1)                                     */
#define SYSCFG_TIM2TRG_ePWM_CMP1_Msk      (0x2UL)                   /*!< ePWM_CMP1 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM2TRG_ePWM_CMP2_Pos      (2UL)                     /*!< ePWM_CMP2 (Bit 2)                                     */
#define SYSCFG_TIM2TRG_ePWM_CMP2_Msk      (0x4UL)                   /*!< ePWM_CMP2 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM2TRG_ePWM_CMP3_Pos      (3UL)                     /*!< ePWM_CMP3 (Bit 3)                                     */
#define SYSCFG_TIM2TRG_ePWM_CMP3_Msk      (0x8UL)                   /*!< ePWM_CMP3 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM2TRG_ePWM_CMP4_Pos      (4UL)                     /*!< ePWM_CMP4 (Bit 4)                                     */
#define SYSCFG_TIM2TRG_ePWM_CMP4_Msk      (0x10UL)                  /*!< ePWM_CMP4 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM2TRG_ePWM_CMP5_Pos      (5UL)                     /*!< ePWM_CMP5 (Bit 5)                                     */
#define SYSCFG_TIM2TRG_ePWM_CMP5_Msk      (0x20UL)                  /*!< ePWM_CMP5 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM2TRG_ePWM_TRGO_Pos      (6UL)                     /*!< ePWM_TRGO (Bit 6)                                     */
#define SYSCFG_TIM2TRG_ePWM_TRGO_Msk      (0x40UL)                  /*!< ePWM_TRGO (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TIM2TRG_ePWM_OC0_Pos       (7UL)                     /*!< ePWM_OC0 (Bit 7)                                      */
#define SYSCFG_TIM2TRG_ePWM_OC0_Msk       (0x80UL)                  /*!< ePWM_OC0 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TIM2TRG_ePWM_OC1_Pos       (8UL)                     /*!< ePWM_OC1 (Bit 8)                                      */
#define SYSCFG_TIM2TRG_ePWM_OC1_Msk       (0x100UL)                 /*!< ePWM_OC1 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TIM2TRG_ePWM_OC2_Pos       (9UL)                     /*!< ePWM_OC2 (Bit 9)                                      */
#define SYSCFG_TIM2TRG_ePWM_OC2_Msk       (0x200UL)                 /*!< ePWM_OC2 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TIM2TRG_ePWM_OC3_Pos       (10UL)                    /*!< ePWM_OC3 (Bit 10)                                     */
#define SYSCFG_TIM2TRG_ePWM_OC3_Msk       (0x400UL)                 /*!< ePWM_OC3 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TIM2TRG_TIM0_UP_Pos        (11UL)                    /*!< TIM0_UP (Bit 11)                                      */
#define SYSCFG_TIM2TRG_TIM0_UP_Msk        (0x800UL)                 /*!< TIM0_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TIM2TRG_TIM1_UP_Pos        (12UL)                    /*!< TIM1_UP (Bit 12)                                      */
#define SYSCFG_TIM2TRG_TIM1_UP_Msk        (0x1000UL)                /*!< TIM1_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TIM2TRG_TIM2_UP_Pos        (13UL)                    /*!< TIM2_UP (Bit 13)                                      */
#define SYSCFG_TIM2TRG_TIM2_UP_Msk        (0x2000UL)                /*!< TIM2_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TIM2TRG_eDIAG_CMP_Pos      (14UL)                    /*!< eDIAG_CMP (Bit 14)                                    */
#define SYSCFG_TIM2TRG_eDIAG_CMP_Msk      (0x4000UL)                /*!< eDIAG_CMP (Bitfield-Mask: 0x01)                       */
/* =========================================================  TRGO0  ========================================================= */
#define SYSCFG_TRGO0_ePWM_CMP0_Pos        (0UL)                     /*!< ePWM_CMP0 (Bit 0)                                     */
#define SYSCFG_TRGO0_ePWM_CMP0_Msk        (0x1UL)                   /*!< ePWM_CMP0 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO0_ePWM_CMP1_Pos        (1UL)                     /*!< ePWM_CMP1 (Bit 1)                                     */
#define SYSCFG_TRGO0_ePWM_CMP1_Msk        (0x2UL)                   /*!< ePWM_CMP1 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO0_ePWM_CMP2_Pos        (2UL)                     /*!< ePWM_CMP2 (Bit 2)                                     */
#define SYSCFG_TRGO0_ePWM_CMP2_Msk        (0x4UL)                   /*!< ePWM_CMP2 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO0_ePWM_CMP3_Pos        (3UL)                     /*!< ePWM_CMP3 (Bit 3)                                     */
#define SYSCFG_TRGO0_ePWM_CMP3_Msk        (0x8UL)                   /*!< ePWM_CMP3 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO0_ePWM_CMP4_Pos        (4UL)                     /*!< ePWM_CMP4 (Bit 4)                                     */
#define SYSCFG_TRGO0_ePWM_CMP4_Msk        (0x10UL)                  /*!< ePWM_CMP4 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO0_ePWM_CMP5_Pos        (5UL)                     /*!< ePWM_CMP5 (Bit 5)                                     */
#define SYSCFG_TRGO0_ePWM_CMP5_Msk        (0x20UL)                  /*!< ePWM_CMP5 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO0_ePWM_TRGO_Pos        (6UL)                     /*!< ePWM_TRGO (Bit 6)                                     */
#define SYSCFG_TRGO0_ePWM_TRGO_Msk        (0x40UL)                  /*!< ePWM_TRGO (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO0_ePWM_OC0_Pos         (7UL)                     /*!< ePWM_OC0 (Bit 7)                                      */
#define SYSCFG_TRGO0_ePWM_OC0_Msk         (0x80UL)                  /*!< ePWM_OC0 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TRGO0_ePWM_OC1_Pos         (8UL)                     /*!< ePWM_OC1 (Bit 8)                                      */
#define SYSCFG_TRGO0_ePWM_OC1_Msk         (0x100UL)                 /*!< ePWM_OC1 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TRGO0_ePWM_OC2_Pos         (9UL)                     /*!< ePWM_OC2 (Bit 9)                                      */
#define SYSCFG_TRGO0_ePWM_OC2_Msk         (0x200UL)                 /*!< ePWM_OC2 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TRGO0_ePWM_OC3_Pos         (10UL)                    /*!< ePWM_OC3 (Bit 10)                                     */
#define SYSCFG_TRGO0_ePWM_OC3_Msk         (0x400UL)                 /*!< ePWM_OC3 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TRGO0_TIM0_UP_Pos          (11UL)                    /*!< TIM0_UP (Bit 11)                                      */
#define SYSCFG_TRGO0_TIM0_UP_Msk          (0x800UL)                 /*!< TIM0_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TRGO0_TIM1_UP_Pos          (12UL)                    /*!< TIM1_UP (Bit 12)                                      */
#define SYSCFG_TRGO0_TIM1_UP_Msk          (0x1000UL)                /*!< TIM1_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TRGO0_TIM2_UP_Pos          (13UL)                    /*!< TIM2_UP (Bit 13)                                      */
#define SYSCFG_TRGO0_TIM2_UP_Msk          (0x2000UL)                /*!< TIM2_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TRGO0_eDIAG_CMP_Pos        (14UL)                    /*!< eDIAG_CMP (Bit 14)                                    */
#define SYSCFG_TRGO0_eDIAG_CMP_Msk        (0x4000UL)                /*!< eDIAG_CMP (Bitfield-Mask: 0x01)                       */
/* =========================================================  TRGO1  ========================================================= */
#define SYSCFG_TRGO1_ePWM_CMP0_Pos        (0UL)                     /*!< ePWM_CMP0 (Bit 0)                                     */
#define SYSCFG_TRGO1_ePWM_CMP0_Msk        (0x1UL)                   /*!< ePWM_CMP0 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO1_ePWM_CMP1_Pos        (1UL)                     /*!< ePWM_CMP1 (Bit 1)                                     */
#define SYSCFG_TRGO1_ePWM_CMP1_Msk        (0x2UL)                   /*!< ePWM_CMP1 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO1_ePWM_CMP2_Pos        (2UL)                     /*!< ePWM_CMP2 (Bit 2)                                     */
#define SYSCFG_TRGO1_ePWM_CMP2_Msk        (0x4UL)                   /*!< ePWM_CMP2 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO1_ePWM_CMP3_Pos        (3UL)                     /*!< ePWM_CMP3 (Bit 3)                                     */
#define SYSCFG_TRGO1_ePWM_CMP3_Msk        (0x8UL)                   /*!< ePWM_CMP3 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO1_ePWM_CMP4_Pos        (4UL)                     /*!< ePWM_CMP4 (Bit 4)                                     */
#define SYSCFG_TRGO1_ePWM_CMP4_Msk        (0x10UL)                  /*!< ePWM_CMP4 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO1_ePWM_CMP5_Pos        (5UL)                     /*!< ePWM_CMP5 (Bit 5)                                     */
#define SYSCFG_TRGO1_ePWM_CMP5_Msk        (0x20UL)                  /*!< ePWM_CMP5 (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO1_ePWM_TRGO_Pos        (6UL)                     /*!< ePWM_TRGO (Bit 6)                                     */
#define SYSCFG_TRGO1_ePWM_TRGO_Msk        (0x40UL)                  /*!< ePWM_TRGO (Bitfield-Mask: 0x01)                       */
#define SYSCFG_TRGO1_ePWM_OC0_Pos         (7UL)                     /*!< ePWM_OC0 (Bit 7)                                      */
#define SYSCFG_TRGO1_ePWM_OC0_Msk         (0x80UL)                  /*!< ePWM_OC0 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TRGO1_ePWM_OC1_Pos         (8UL)                     /*!< ePWM_OC1 (Bit 8)                                      */
#define SYSCFG_TRGO1_ePWM_OC1_Msk         (0x100UL)                 /*!< ePWM_OC1 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TRGO1_ePWM_OC2_Pos         (9UL)                     /*!< ePWM_OC2 (Bit 9)                                      */
#define SYSCFG_TRGO1_ePWM_OC2_Msk         (0x200UL)                 /*!< ePWM_OC2 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TRGO1_ePWM_OC3_Pos         (10UL)                    /*!< ePWM_OC3 (Bit 10)                                     */
#define SYSCFG_TRGO1_ePWM_OC3_Msk         (0x400UL)                 /*!< ePWM_OC3 (Bitfield-Mask: 0x01)                        */
#define SYSCFG_TRGO1_TIM0_UP_Pos          (11UL)                    /*!< TIM0_UP (Bit 11)                                      */
#define SYSCFG_TRGO1_TIM0_UP_Msk          (0x800UL)                 /*!< TIM0_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TRGO1_TIM1_UP_Pos          (12UL)                    /*!< TIM1_UP (Bit 12)                                      */
#define SYSCFG_TRGO1_TIM1_UP_Msk          (0x1000UL)                /*!< TIM1_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TRGO1_TIM2_UP_Pos          (13UL)                    /*!< TIM2_UP (Bit 13)                                      */
#define SYSCFG_TRGO1_TIM2_UP_Msk          (0x2000UL)                /*!< TIM2_UP (Bitfield-Mask: 0x01)                         */
#define SYSCFG_TRGO1_eDIAG_CMP_Pos        (14UL)                    /*!< eDIAG_CMP (Bit 14)                                    */
#define SYSCFG_TRGO1_eDIAG_CMP_Msk        (0x4000UL)                /*!< eDIAG_CMP (Bitfield-Mask: 0x01)                       */
/* =========================================================  DBGEN  ========================================================= */
#define SYSCFG_DBGEN_KEY_Pos              (24UL)                    /*!< KEY (Bit 24)                                          */
#define SYSCFG_DBGEN_KEY_Msk              (0xff000000UL)            /*!< KEY (Bitfield-Mask: 0xff)                             */
#define SYSCFG_DBGEN_EN_Pos               (0UL)                     /*!< EN (Bit 0)                                            */
#define SYSCFG_DBGEN_EN_Msk               (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ========================================================  DBGLOCK  ======================================================== */
#define SYSCFG_DBGLOCK_KEY_Pos            (24UL)                    /*!< KEY (Bit 24)                                          */
#define SYSCFG_DBGLOCK_KEY_Msk            (0xff000000UL)            /*!< KEY (Bitfield-Mask: 0xff)                             */
#define SYSCFG_DBGLOCK_LOCK_Pos           (0UL)                     /*!< LOCK (Bit 0)                                          */
#define SYSCFG_DBGLOCK_LOCK_Msk           (0x1UL)                   /*!< LOCK (Bitfield-Mask: 0x01)                            */
/* ========================================================  DBGMODE  ======================================================== */
#define SYSCFG_DBGMODE_MODE_Pos           (0UL)                     /*!< MODE (Bit 0)                                          */
#define SYSCFG_DBGMODE_MODE_Msk           (0x7UL)                   /*!< MODE (Bitfield-Mask: 0x07)                            */
/* =========================================================  DFTEN  ========================================================= */
#define SYSCFG_DFTEN_KEY_Pos              (24UL)                    /*!< KEY (Bit 24)                                          */
#define SYSCFG_DFTEN_KEY_Msk              (0xff000000UL)            /*!< KEY (Bitfield-Mask: 0xff)                             */
#define SYSCFG_DFTEN_EN_Pos               (0UL)                     /*!< EN (Bit 0)                                            */
#define SYSCFG_DFTEN_EN_Msk               (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ========================================================  DFTLOCK  ======================================================== */
#define SYSCFG_DFTLOCK_KEY_Pos            (24UL)                    /*!< KEY (Bit 24)                                          */
#define SYSCFG_DFTLOCK_KEY_Msk            (0xff000000UL)            /*!< KEY (Bitfield-Mask: 0xff)                             */
#define SYSCFG_DFTLOCK_LOCK_Pos           (0UL)                     /*!< LOCK (Bit 0)                                          */
#define SYSCFG_DFTLOCK_LOCK_Msk           (0x1UL)                   /*!< LOCK (Bitfield-Mask: 0x01)                            */
/* ========================================================  DFTMODE  ======================================================== */
#define SYSCFG_DFTMODE_MODE_Pos           (0UL)                     /*!< MODE (Bit 0)                                          */
#define SYSCFG_DFTMODE_MODE_Msk           (0xfUL)                   /*!< MODE (Bitfield-Mask: 0x0f)                            */
/* ========================================================  OSCHENR  ======================================================== */
#define SYSCFG_OSCHENR_KEY_Pos            (24UL)                    /*!< KEY (Bit 24)                                          */
#define SYSCFG_OSCHENR_KEY_Msk            (0xff000000UL)            /*!< KEY (Bitfield-Mask: 0xff)                             */
#define SYSCFG_OSCHENR_EN_Pos             (0UL)                     /*!< EN (Bit 0)                                            */
#define SYSCFG_OSCHENR_EN_Msk             (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ======================================================  OSCHENLOCKR  ====================================================== */
#define SYSCFG_OSCHENLOCKR_KEY_Pos        (24UL)                    /*!< KEY (Bit 24)                                          */
#define SYSCFG_OSCHENLOCKR_KEY_Msk        (0xff000000UL)            /*!< KEY (Bitfield-Mask: 0xff)                             */
#define SYSCFG_OSCHENLOCKR_LOCK_Pos       (0UL)                     /*!< LOCK (Bit 0)                                          */
#define SYSCFG_OSCHENLOCKR_LOCK_Msk       (0x1UL)                   /*!< LOCK (Bitfield-Mask: 0x01)                            */
/* ========================================================  REMAPR  ========================================================= */
#define SYSCFG_REMAPR_FLASH1_Pos          (0UL)                     /*!< FLASH1 (Bit 0)                                        */
#define SYSCFG_REMAPR_FLASH1_Msk          (0x1UL)                   /*!< FLASH1 (Bitfield-Mask: 0x01)                          */
#define SYSCFG_REMAPR_RAM_Pos             (1UL)                     /*!< RAM (Bit 1)                                           */
#define SYSCFG_REMAPR_RAM_Msk             (0x2UL)                   /*!< RAM (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  ISR  ========================================================== */
#define DMA_ISR_GIF1_Pos                  (0UL)                     /*!< GIF1 (Bit 0)                                          */
#define DMA_ISR_GIF1_Msk                  (0x1UL)                   /*!< GIF1 (Bitfield-Mask: 0x01)                            */
#define DMA_ISR_TCIF1_Pos                 (1UL)                     /*!< TCIF1 (Bit 1)                                         */
#define DMA_ISR_TCIF1_Msk                 (0x2UL)                   /*!< TCIF1 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_HTIF1_Pos                 (2UL)                     /*!< HTIF1 (Bit 2)                                         */
#define DMA_ISR_HTIF1_Msk                 (0x4UL)                   /*!< HTIF1 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_TEIF1_Pos                 (3UL)                     /*!< TEIF1 (Bit 3)                                         */
#define DMA_ISR_TEIF1_Msk                 (0x8UL)                   /*!< TEIF1 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_GIF2_Pos                  (4UL)                     /*!< GIF2 (Bit 4)                                          */
#define DMA_ISR_GIF2_Msk                  (0x10UL)                  /*!< GIF2 (Bitfield-Mask: 0x01)                            */
#define DMA_ISR_TCIF2_Pos                 (5UL)                     /*!< TCIF2 (Bit 5)                                         */
#define DMA_ISR_TCIF2_Msk                 (0x20UL)                  /*!< TCIF2 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_HTIF2_Pos                 (6UL)                     /*!< HTIF2 (Bit 6)                                         */
#define DMA_ISR_HTIF2_Msk                 (0x40UL)                  /*!< HTIF2 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_TEIF2_Pos                 (7UL)                     /*!< TEIF2 (Bit 7)                                         */
#define DMA_ISR_TEIF2_Msk                 (0x80UL)                  /*!< TEIF2 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_GIF3_Pos                  (8UL)                     /*!< GIF3 (Bit 8)                                          */
#define DMA_ISR_GIF3_Msk                  (0x100UL)                 /*!< GIF3 (Bitfield-Mask: 0x01)                            */
#define DMA_ISR_TCIF3_Pos                 (9UL)                     /*!< TCIF3 (Bit 9)                                         */
#define DMA_ISR_TCIF3_Msk                 (0x200UL)                 /*!< TCIF3 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_HTIF3_Pos                 (10UL)                    /*!< HTIF3 (Bit 10)                                        */
#define DMA_ISR_HTIF3_Msk                 (0x400UL)                 /*!< HTIF3 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_TEIF3_Pos                 (11UL)                    /*!< TEIF3 (Bit 11)                                        */
#define DMA_ISR_TEIF3_Msk                 (0x800UL)                 /*!< TEIF3 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_GIF4_Pos                  (12UL)                    /*!< GIF4 (Bit 12)                                         */
#define DMA_ISR_GIF4_Msk                  (0x1000UL)                /*!< GIF4 (Bitfield-Mask: 0x01)                            */
#define DMA_ISR_TCIF4_Pos                 (13UL)                    /*!< TCIF4 (Bit 13)                                        */
#define DMA_ISR_TCIF4_Msk                 (0x2000UL)                /*!< TCIF4 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_HTIF4_Pos                 (14UL)                    /*!< HTIF4 (Bit 14)                                        */
#define DMA_ISR_HTIF4_Msk                 (0x4000UL)                /*!< HTIF4 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_TEIF4_Pos                 (15UL)                    /*!< TEIF4 (Bit 15)                                        */
#define DMA_ISR_TEIF4_Msk                 (0x8000UL)                /*!< TEIF4 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_GIF5_Pos                  (16UL)                    /*!< GIF5 (Bit 16)                                         */
#define DMA_ISR_GIF5_Msk                  (0x10000UL)               /*!< GIF5 (Bitfield-Mask: 0x01)                            */
#define DMA_ISR_TCIF5_Pos                 (17UL)                    /*!< TCIF5 (Bit 17)                                        */
#define DMA_ISR_TCIF5_Msk                 (0x20000UL)               /*!< TCIF5 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_HTIF5_Pos                 (18UL)                    /*!< HTIF5 (Bit 18)                                        */
#define DMA_ISR_HTIF5_Msk                 (0x40000UL)               /*!< HTIF5 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_TEIF5_Pos                 (19UL)                    /*!< TEIF5 (Bit 19)                                        */
#define DMA_ISR_TEIF5_Msk                 (0x80000UL)               /*!< TEIF5 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_GIF6_Pos                  (20UL)                    /*!< GIF6 (Bit 20)                                         */
#define DMA_ISR_GIF6_Msk                  (0x100000UL)              /*!< GIF6 (Bitfield-Mask: 0x01)                            */
#define DMA_ISR_TCIF6_Pos                 (21UL)                    /*!< TCIF6 (Bit 21)                                        */
#define DMA_ISR_TCIF6_Msk                 (0x200000UL)              /*!< TCIF6 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_HTIF6_Pos                 (22UL)                    /*!< HTIF6 (Bit 22)                                        */
#define DMA_ISR_HTIF6_Msk                 (0x400000UL)              /*!< HTIF6 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_TEIF6_Pos                 (23UL)                    /*!< TEIF6 (Bit 23)                                        */
#define DMA_ISR_TEIF6_Msk                 (0x800000UL)              /*!< TEIF6 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_GIF7_Pos                  (24UL)                    /*!< GIF7 (Bit 24)                                         */
#define DMA_ISR_GIF7_Msk                  (0x1000000UL)             /*!< GIF7 (Bitfield-Mask: 0x01)                            */
#define DMA_ISR_TCIF7_Pos                 (25UL)                    /*!< TCIF7 (Bit 25)                                        */
#define DMA_ISR_TCIF7_Msk                 (0x2000000UL)             /*!< TCIF7 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_HTIF7_Pos                 (26UL)                    /*!< HTIF7 (Bit 26)                                        */
#define DMA_ISR_HTIF7_Msk                 (0x4000000UL)             /*!< HTIF7 (Bitfield-Mask: 0x01)                           */
#define DMA_ISR_TEIF7_Pos                 (27UL)                    /*!< TEIF7 (Bit 27)                                        */
#define DMA_ISR_TEIF7_Msk                 (0x8000000UL)             /*!< TEIF7 (Bitfield-Mask: 0x01)                           */
/* =========================================================  IFCR  ========================================================== */
#define DMA_IFCR_CGIF1_Pos                (0UL)                     /*!< CGIF1 (Bit 0)                                         */
#define DMA_IFCR_CGIF1_Msk                (0x1UL)                   /*!< CGIF1 (Bitfield-Mask: 0x01)                           */
#define DMA_IFCR_CGIF2_Pos                (4UL)                     /*!< CGIF2 (Bit 4)                                         */
#define DMA_IFCR_CGIF2_Msk                (0x10UL)                  /*!< CGIF2 (Bitfield-Mask: 0x01)                           */
#define DMA_IFCR_CGIF3_Pos                (8UL)                     /*!< CGIF3 (Bit 8)                                         */
#define DMA_IFCR_CGIF3_Msk                (0x100UL)                 /*!< CGIF3 (Bitfield-Mask: 0x01)                           */
#define DMA_IFCR_CGIF4_Pos                (12UL)                    /*!< CGIF4 (Bit 12)                                        */
#define DMA_IFCR_CGIF4_Msk                (0x1000UL)                /*!< CGIF4 (Bitfield-Mask: 0x01)                           */
#define DMA_IFCR_CGIF5_Pos                (16UL)                    /*!< CGIF5 (Bit 16)                                        */
#define DMA_IFCR_CGIF5_Msk                (0x10000UL)               /*!< CGIF5 (Bitfield-Mask: 0x01)                           */
#define DMA_IFCR_CGIF6_Pos                (20UL)                    /*!< CGIF6 (Bit 20)                                        */
#define DMA_IFCR_CGIF6_Msk                (0x100000UL)              /*!< CGIF6 (Bitfield-Mask: 0x01)                           */
#define DMA_IFCR_CGIF7_Pos                (24UL)                    /*!< CGIF7 (Bit 24)                                        */
#define DMA_IFCR_CGIF7_Msk                (0x1000000UL)             /*!< CGIF7 (Bitfield-Mask: 0x01)                           */
#define DMA_IFCR_CTCIF1_Pos               (1UL)                     /*!< CTCIF1 (Bit 1)                                        */
#define DMA_IFCR_CTCIF1_Msk               (0x2UL)                   /*!< CTCIF1 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CTCIF2_Pos               (5UL)                     /*!< CTCIF2 (Bit 5)                                        */
#define DMA_IFCR_CTCIF2_Msk               (0x20UL)                  /*!< CTCIF2 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CTCIF3_Pos               (9UL)                     /*!< CTCIF3 (Bit 9)                                        */
#define DMA_IFCR_CTCIF3_Msk               (0x200UL)                 /*!< CTCIF3 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CTCIF4_Pos               (13UL)                    /*!< CTCIF4 (Bit 13)                                       */
#define DMA_IFCR_CTCIF4_Msk               (0x2000UL)                /*!< CTCIF4 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CTCIF5_Pos               (17UL)                    /*!< CTCIF5 (Bit 17)                                       */
#define DMA_IFCR_CTCIF5_Msk               (0x20000UL)               /*!< CTCIF5 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CTCIF6_Pos               (21UL)                    /*!< CTCIF6 (Bit 21)                                       */
#define DMA_IFCR_CTCIF6_Msk               (0x200000UL)              /*!< CTCIF6 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CTCIF7_Pos               (25UL)                    /*!< CTCIF7 (Bit 25)                                       */
#define DMA_IFCR_CTCIF7_Msk               (0x2000000UL)             /*!< CTCIF7 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CHTIF1_Pos               (2UL)                     /*!< CHTIF1 (Bit 2)                                        */
#define DMA_IFCR_CHTIF1_Msk               (0x4UL)                   /*!< CHTIF1 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CHTIF2_Pos               (6UL)                     /*!< CHTIF2 (Bit 6)                                        */
#define DMA_IFCR_CHTIF2_Msk               (0x40UL)                  /*!< CHTIF2 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CHTIF3_Pos               (10UL)                    /*!< CHTIF3 (Bit 10)                                       */
#define DMA_IFCR_CHTIF3_Msk               (0x400UL)                 /*!< CHTIF3 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CHTIF4_Pos               (14UL)                    /*!< CHTIF4 (Bit 14)                                       */
#define DMA_IFCR_CHTIF4_Msk               (0x4000UL)                /*!< CHTIF4 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CHTIF5_Pos               (18UL)                    /*!< CHTIF5 (Bit 18)                                       */
#define DMA_IFCR_CHTIF5_Msk               (0x40000UL)               /*!< CHTIF5 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CHTIF6_Pos               (22UL)                    /*!< CHTIF6 (Bit 22)                                       */
#define DMA_IFCR_CHTIF6_Msk               (0x400000UL)              /*!< CHTIF6 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CHTIF7_Pos               (26UL)                    /*!< CHTIF7 (Bit 26)                                       */
#define DMA_IFCR_CHTIF7_Msk               (0x4000000UL)             /*!< CHTIF7 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CTEIF1_Pos               (3UL)                     /*!< CTEIF1 (Bit 3)                                        */
#define DMA_IFCR_CTEIF1_Msk               (0x8UL)                   /*!< CTEIF1 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CTEIF2_Pos               (7UL)                     /*!< CTEIF2 (Bit 7)                                        */
#define DMA_IFCR_CTEIF2_Msk               (0x80UL)                  /*!< CTEIF2 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CTEIF3_Pos               (11UL)                    /*!< CTEIF3 (Bit 11)                                       */
#define DMA_IFCR_CTEIF3_Msk               (0x800UL)                 /*!< CTEIF3 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CTEIF4_Pos               (15UL)                    /*!< CTEIF4 (Bit 15)                                       */
#define DMA_IFCR_CTEIF4_Msk               (0x8000UL)                /*!< CTEIF4 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CTEIF5_Pos               (19UL)                    /*!< CTEIF5 (Bit 19)                                       */
#define DMA_IFCR_CTEIF5_Msk               (0x80000UL)               /*!< CTEIF5 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CTEIF6_Pos               (23UL)                    /*!< CTEIF6 (Bit 23)                                       */
#define DMA_IFCR_CTEIF6_Msk               (0x800000UL)              /*!< CTEIF6 (Bitfield-Mask: 0x01)                          */
#define DMA_IFCR_CTEIF7_Pos               (27UL)                    /*!< CTEIF7 (Bit 27)                                       */
#define DMA_IFCR_CTEIF7_Msk               (0x8000000UL)             /*!< CTEIF7 (Bitfield-Mask: 0x01)                          */
/* =========================================================  CCR1  ========================================================== */
#define DMA_CCR1_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CCR1_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define DMA_CCR1_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CCR1_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR1_HTIE_Pos                 (2UL)                     /*!< HTIE (Bit 2)                                          */
#define DMA_CCR1_HTIE_Msk                 (0x4UL)                   /*!< HTIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR1_TEIE_Pos                 (3UL)                     /*!< TEIE (Bit 3)                                          */
#define DMA_CCR1_TEIE_Msk                 (0x8UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR1_DIR_Pos                  (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA_CCR1_DIR_Msk                  (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA_CCR1_CIRC_Pos                 (5UL)                     /*!< CIRC (Bit 5)                                          */
#define DMA_CCR1_CIRC_Msk                 (0x20UL)                  /*!< CIRC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR1_PINC_Pos                 (6UL)                     /*!< PINC (Bit 6)                                          */
#define DMA_CCR1_PINC_Msk                 (0x40UL)                  /*!< PINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR1_MINC_Pos                 (7UL)                     /*!< MINC (Bit 7)                                          */
#define DMA_CCR1_MINC_Msk                 (0x80UL)                  /*!< MINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR1_PSIZE_Pos                (8UL)                     /*!< PSIZE (Bit 8)                                         */
#define DMA_CCR1_PSIZE_Msk                (0x300UL)                 /*!< PSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR1_MSIZE_Pos                (10UL)                    /*!< MSIZE (Bit 10)                                        */
#define DMA_CCR1_MSIZE_Msk                (0xc00UL)                 /*!< MSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR1_PL_Pos                   (12UL)                    /*!< PL (Bit 12)                                           */
#define DMA_CCR1_PL_Msk                   (0x3000UL)                /*!< PL (Bitfield-Mask: 0x03)                              */
#define DMA_CCR1_MEM2MEM_Pos              (14UL)                    /*!< MEM2MEM (Bit 14)                                      */
#define DMA_CCR1_MEM2MEM_Msk              (0x4000UL)                /*!< MEM2MEM (Bitfield-Mask: 0x01)                         */
/* ========================================================  CNDTR1  ========================================================= */
#define DMA_CNDTR1_NDT_Pos                (0UL)                     /*!< NDT (Bit 0)                                           */
#define DMA_CNDTR1_NDT_Msk                (0xffffUL)                /*!< NDT (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CPAR1  ========================================================= */
#define DMA_CPAR1_PA_Pos                  (0UL)                     /*!< PA (Bit 0)                                            */
#define DMA_CPAR1_PA_Msk                  (0xffffffffUL)            /*!< PA (Bitfield-Mask: 0xffffffff)                        */
/* =========================================================  CMAR1  ========================================================= */
#define DMA_CMAR1_MA_Pos                  (0UL)                     /*!< MA (Bit 0)                                            */
#define DMA_CMAR1_MA_Msk                  (0xffffffffUL)            /*!< MA (Bitfield-Mask: 0xffffffff)                        */
/* =========================================================  CCR2  ========================================================== */
#define DMA_CCR2_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CCR2_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define DMA_CCR2_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CCR2_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR2_HTIE_Pos                 (2UL)                     /*!< HTIE (Bit 2)                                          */
#define DMA_CCR2_HTIE_Msk                 (0x4UL)                   /*!< HTIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR2_TEIE_Pos                 (3UL)                     /*!< TEIE (Bit 3)                                          */
#define DMA_CCR2_TEIE_Msk                 (0x8UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR2_DIR_Pos                  (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA_CCR2_DIR_Msk                  (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA_CCR2_CIRC_Pos                 (5UL)                     /*!< CIRC (Bit 5)                                          */
#define DMA_CCR2_CIRC_Msk                 (0x20UL)                  /*!< CIRC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR2_PINC_Pos                 (6UL)                     /*!< PINC (Bit 6)                                          */
#define DMA_CCR2_PINC_Msk                 (0x40UL)                  /*!< PINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR2_MINC_Pos                 (7UL)                     /*!< MINC (Bit 7)                                          */
#define DMA_CCR2_MINC_Msk                 (0x80UL)                  /*!< MINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR2_PSIZE_Pos                (8UL)                     /*!< PSIZE (Bit 8)                                         */
#define DMA_CCR2_PSIZE_Msk                (0x300UL)                 /*!< PSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR2_MSIZE_Pos                (10UL)                    /*!< MSIZE (Bit 10)                                        */
#define DMA_CCR2_MSIZE_Msk                (0xc00UL)                 /*!< MSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR2_PL_Pos                   (12UL)                    /*!< PL (Bit 12)                                           */
#define DMA_CCR2_PL_Msk                   (0x3000UL)                /*!< PL (Bitfield-Mask: 0x03)                              */
#define DMA_CCR2_MEM2MEM_Pos              (14UL)                    /*!< MEM2MEM (Bit 14)                                      */
#define DMA_CCR2_MEM2MEM_Msk              (0x4000UL)                /*!< MEM2MEM (Bitfield-Mask: 0x01)                         */
/* ========================================================  CNDTR2  ========================================================= */
#define DMA_CNDTR2_NDT_Pos                (0UL)                     /*!< NDT (Bit 0)                                           */
#define DMA_CNDTR2_NDT_Msk                (0xffffUL)                /*!< NDT (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CPAR2  ========================================================= */
#define DMA_CPAR2_PA_Pos                  (0UL)                     /*!< PA (Bit 0)                                            */
#define DMA_CPAR2_PA_Msk                  (0xffffffffUL)            /*!< PA (Bitfield-Mask: 0xffffffff)                        */
/* =========================================================  CMAR2  ========================================================= */
#define DMA_CMAR2_MA_Pos                  (0UL)                     /*!< MA (Bit 0)                                            */
#define DMA_CMAR2_MA_Msk                  (0xffffffffUL)            /*!< MA (Bitfield-Mask: 0xffffffff)                        */
/* =========================================================  CCR3  ========================================================== */
#define DMA_CCR3_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CCR3_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define DMA_CCR3_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CCR3_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR3_HTIE_Pos                 (2UL)                     /*!< HTIE (Bit 2)                                          */
#define DMA_CCR3_HTIE_Msk                 (0x4UL)                   /*!< HTIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR3_TEIE_Pos                 (3UL)                     /*!< TEIE (Bit 3)                                          */
#define DMA_CCR3_TEIE_Msk                 (0x8UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR3_DIR_Pos                  (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA_CCR3_DIR_Msk                  (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA_CCR3_CIRC_Pos                 (5UL)                     /*!< CIRC (Bit 5)                                          */
#define DMA_CCR3_CIRC_Msk                 (0x20UL)                  /*!< CIRC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR3_PINC_Pos                 (6UL)                     /*!< PINC (Bit 6)                                          */
#define DMA_CCR3_PINC_Msk                 (0x40UL)                  /*!< PINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR3_MINC_Pos                 (7UL)                     /*!< MINC (Bit 7)                                          */
#define DMA_CCR3_MINC_Msk                 (0x80UL)                  /*!< MINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR3_PSIZE_Pos                (8UL)                     /*!< PSIZE (Bit 8)                                         */
#define DMA_CCR3_PSIZE_Msk                (0x300UL)                 /*!< PSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR3_MSIZE_Pos                (10UL)                    /*!< MSIZE (Bit 10)                                        */
#define DMA_CCR3_MSIZE_Msk                (0xc00UL)                 /*!< MSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR3_PL_Pos                   (12UL)                    /*!< PL (Bit 12)                                           */
#define DMA_CCR3_PL_Msk                   (0x3000UL)                /*!< PL (Bitfield-Mask: 0x03)                              */
#define DMA_CCR3_MEM2MEM_Pos              (14UL)                    /*!< MEM2MEM (Bit 14)                                      */
#define DMA_CCR3_MEM2MEM_Msk              (0x4000UL)                /*!< MEM2MEM (Bitfield-Mask: 0x01)                         */
/* ========================================================  CNDTR3  ========================================================= */
#define DMA_CNDTR3_NDT_Pos                (0UL)                     /*!< NDT (Bit 0)                                           */
#define DMA_CNDTR3_NDT_Msk                (0xffffUL)                /*!< NDT (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CPAR3  ========================================================= */
#define DMA_CPAR3_PA_Pos                  (0UL)                     /*!< PA (Bit 0)                                            */
#define DMA_CPAR3_PA_Msk                  (0xffffffffUL)            /*!< PA (Bitfield-Mask: 0xffffffff)                        */
/* =========================================================  CMAR3  ========================================================= */
#define DMA_CMAR3_MA_Pos                  (0UL)                     /*!< MA (Bit 0)                                            */
#define DMA_CMAR3_MA_Msk                  (0xffffffffUL)            /*!< MA (Bitfield-Mask: 0xffffffff)                        */
/* =========================================================  CCR4  ========================================================== */
#define DMA_CCR4_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CCR4_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define DMA_CCR4_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CCR4_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR4_HTIE_Pos                 (2UL)                     /*!< HTIE (Bit 2)                                          */
#define DMA_CCR4_HTIE_Msk                 (0x4UL)                   /*!< HTIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR4_TEIE_Pos                 (3UL)                     /*!< TEIE (Bit 3)                                          */
#define DMA_CCR4_TEIE_Msk                 (0x8UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR4_DIR_Pos                  (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA_CCR4_DIR_Msk                  (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA_CCR4_CIRC_Pos                 (5UL)                     /*!< CIRC (Bit 5)                                          */
#define DMA_CCR4_CIRC_Msk                 (0x20UL)                  /*!< CIRC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR4_PINC_Pos                 (6UL)                     /*!< PINC (Bit 6)                                          */
#define DMA_CCR4_PINC_Msk                 (0x40UL)                  /*!< PINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR4_MINC_Pos                 (7UL)                     /*!< MINC (Bit 7)                                          */
#define DMA_CCR4_MINC_Msk                 (0x80UL)                  /*!< MINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR4_PSIZE_Pos                (8UL)                     /*!< PSIZE (Bit 8)                                         */
#define DMA_CCR4_PSIZE_Msk                (0x300UL)                 /*!< PSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR4_MSIZE_Pos                (10UL)                    /*!< MSIZE (Bit 10)                                        */
#define DMA_CCR4_MSIZE_Msk                (0xc00UL)                 /*!< MSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR4_PL_Pos                   (12UL)                    /*!< PL (Bit 12)                                           */
#define DMA_CCR4_PL_Msk                   (0x3000UL)                /*!< PL (Bitfield-Mask: 0x03)                              */
#define DMA_CCR4_MEM2MEM_Pos              (14UL)                    /*!< MEM2MEM (Bit 14)                                      */
#define DMA_CCR4_MEM2MEM_Msk              (0x4000UL)                /*!< MEM2MEM (Bitfield-Mask: 0x01)                         */
/* ========================================================  CNDTR4  ========================================================= */
#define DMA_CNDTR4_NDT_Pos                (0UL)                     /*!< NDT (Bit 0)                                           */
#define DMA_CNDTR4_NDT_Msk                (0xffffUL)                /*!< NDT (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CPAR4  ========================================================= */
#define DMA_CPAR4_PA_Pos                  (0UL)                     /*!< PA (Bit 0)                                            */
#define DMA_CPAR4_PA_Msk                  (0xffffffffUL)            /*!< PA (Bitfield-Mask: 0xffffffff)                        */
/* =========================================================  CMAR4  ========================================================= */
#define DMA_CMAR4_MA_Pos                  (0UL)                     /*!< MA (Bit 0)                                            */
#define DMA_CMAR4_MA_Msk                  (0xffffffffUL)            /*!< MA (Bitfield-Mask: 0xffffffff)                        */
/* =========================================================  CCR5  ========================================================== */
#define DMA_CCR5_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CCR5_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define DMA_CCR5_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CCR5_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR5_HTIE_Pos                 (2UL)                     /*!< HTIE (Bit 2)                                          */
#define DMA_CCR5_HTIE_Msk                 (0x4UL)                   /*!< HTIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR5_TEIE_Pos                 (3UL)                     /*!< TEIE (Bit 3)                                          */
#define DMA_CCR5_TEIE_Msk                 (0x8UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR5_DIR_Pos                  (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA_CCR5_DIR_Msk                  (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA_CCR5_CIRC_Pos                 (5UL)                     /*!< CIRC (Bit 5)                                          */
#define DMA_CCR5_CIRC_Msk                 (0x20UL)                  /*!< CIRC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR5_PINC_Pos                 (6UL)                     /*!< PINC (Bit 6)                                          */
#define DMA_CCR5_PINC_Msk                 (0x40UL)                  /*!< PINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR5_MINC_Pos                 (7UL)                     /*!< MINC (Bit 7)                                          */
#define DMA_CCR5_MINC_Msk                 (0x80UL)                  /*!< MINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR5_PSIZE_Pos                (8UL)                     /*!< PSIZE (Bit 8)                                         */
#define DMA_CCR5_PSIZE_Msk                (0x300UL)                 /*!< PSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR5_MSIZE_Pos                (10UL)                    /*!< MSIZE (Bit 10)                                        */
#define DMA_CCR5_MSIZE_Msk                (0xc00UL)                 /*!< MSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR5_PL_Pos                   (12UL)                    /*!< PL (Bit 12)                                           */
#define DMA_CCR5_PL_Msk                   (0x3000UL)                /*!< PL (Bitfield-Mask: 0x03)                              */
#define DMA_CCR5_MEM2MEM_Pos              (14UL)                    /*!< MEM2MEM (Bit 14)                                      */
#define DMA_CCR5_MEM2MEM_Msk              (0x4000UL)                /*!< MEM2MEM (Bitfield-Mask: 0x01)                         */
/* ========================================================  CNDTR5  ========================================================= */
#define DMA_CNDTR5_NDT_Pos                (0UL)                     /*!< NDT (Bit 0)                                           */
#define DMA_CNDTR5_NDT_Msk                (0xffffUL)                /*!< NDT (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CPAR5  ========================================================= */
#define DMA_CPAR5_PA_Pos                  (0UL)                     /*!< PA (Bit 0)                                            */
#define DMA_CPAR5_PA_Msk                  (0xffffffffUL)            /*!< PA (Bitfield-Mask: 0xffffffff)                        */
/* =========================================================  CMAR5  ========================================================= */
#define DMA_CMAR5_MA_Pos                  (0UL)                     /*!< MA (Bit 0)                                            */
#define DMA_CMAR5_MA_Msk                  (0xffffffffUL)            /*!< MA (Bitfield-Mask: 0xffffffff)                        */
/* =========================================================  CCR6  ========================================================== */
#define DMA_CCR6_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CCR6_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define DMA_CCR6_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CCR6_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR6_HTIE_Pos                 (2UL)                     /*!< HTIE (Bit 2)                                          */
#define DMA_CCR6_HTIE_Msk                 (0x4UL)                   /*!< HTIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR6_TEIE_Pos                 (3UL)                     /*!< TEIE (Bit 3)                                          */
#define DMA_CCR6_TEIE_Msk                 (0x8UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR6_DIR_Pos                  (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA_CCR6_DIR_Msk                  (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA_CCR6_CIRC_Pos                 (5UL)                     /*!< CIRC (Bit 5)                                          */
#define DMA_CCR6_CIRC_Msk                 (0x20UL)                  /*!< CIRC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR6_PINC_Pos                 (6UL)                     /*!< PINC (Bit 6)                                          */
#define DMA_CCR6_PINC_Msk                 (0x40UL)                  /*!< PINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR6_MINC_Pos                 (7UL)                     /*!< MINC (Bit 7)                                          */
#define DMA_CCR6_MINC_Msk                 (0x80UL)                  /*!< MINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR6_PSIZE_Pos                (8UL)                     /*!< PSIZE (Bit 8)                                         */
#define DMA_CCR6_PSIZE_Msk                (0x300UL)                 /*!< PSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR6_MSIZE_Pos                (10UL)                    /*!< MSIZE (Bit 10)                                        */
#define DMA_CCR6_MSIZE_Msk                (0xc00UL)                 /*!< MSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR6_PL_Pos                   (12UL)                    /*!< PL (Bit 12)                                           */
#define DMA_CCR6_PL_Msk                   (0x3000UL)                /*!< PL (Bitfield-Mask: 0x03)                              */
#define DMA_CCR6_MEM2MEM_Pos              (14UL)                    /*!< MEM2MEM (Bit 14)                                      */
#define DMA_CCR6_MEM2MEM_Msk              (0x4000UL)                /*!< MEM2MEM (Bitfield-Mask: 0x01)                         */
/* ========================================================  CNDTR6  ========================================================= */
#define DMA_CNDTR6_NDT_Pos                (0UL)                     /*!< NDT (Bit 0)                                           */
#define DMA_CNDTR6_NDT_Msk                (0xffffUL)                /*!< NDT (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CPAR6  ========================================================= */
#define DMA_CPAR6_PA_Pos                  (0UL)                     /*!< PA (Bit 0)                                            */
#define DMA_CPAR6_PA_Msk                  (0xffffffffUL)            /*!< PA (Bitfield-Mask: 0xffffffff)                        */
/* =========================================================  CMAR6  ========================================================= */
#define DMA_CMAR6_MA_Pos                  (0UL)                     /*!< MA (Bit 0)                                            */
#define DMA_CMAR6_MA_Msk                  (0xffffffffUL)            /*!< MA (Bitfield-Mask: 0xffffffff)                        */
/* =========================================================  CCR7  ========================================================== */
#define DMA_CCR7_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CCR7_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define DMA_CCR7_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CCR7_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR7_HTIE_Pos                 (2UL)                     /*!< HTIE (Bit 2)                                          */
#define DMA_CCR7_HTIE_Msk                 (0x4UL)                   /*!< HTIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR7_TEIE_Pos                 (3UL)                     /*!< TEIE (Bit 3)                                          */
#define DMA_CCR7_TEIE_Msk                 (0x8UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CCR7_DIR_Pos                  (4UL)                     /*!< DIR (Bit 4)                                           */
#define DMA_CCR7_DIR_Msk                  (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define DMA_CCR7_CIRC_Pos                 (5UL)                     /*!< CIRC (Bit 5)                                          */
#define DMA_CCR7_CIRC_Msk                 (0x20UL)                  /*!< CIRC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR7_PINC_Pos                 (6UL)                     /*!< PINC (Bit 6)                                          */
#define DMA_CCR7_PINC_Msk                 (0x40UL)                  /*!< PINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR7_MINC_Pos                 (7UL)                     /*!< MINC (Bit 7)                                          */
#define DMA_CCR7_MINC_Msk                 (0x80UL)                  /*!< MINC (Bitfield-Mask: 0x01)                            */
#define DMA_CCR7_PSIZE_Pos                (8UL)                     /*!< PSIZE (Bit 8)                                         */
#define DMA_CCR7_PSIZE_Msk                (0x300UL)                 /*!< PSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR7_MSIZE_Pos                (10UL)                    /*!< MSIZE (Bit 10)                                        */
#define DMA_CCR7_MSIZE_Msk                (0xc00UL)                 /*!< MSIZE (Bitfield-Mask: 0x03)                           */
#define DMA_CCR7_PL_Pos                   (12UL)                    /*!< PL (Bit 12)                                           */
#define DMA_CCR7_PL_Msk                   (0x3000UL)                /*!< PL (Bitfield-Mask: 0x03)                              */
#define DMA_CCR7_MEM2MEM_Pos              (14UL)                    /*!< MEM2MEM (Bit 14)                                      */
#define DMA_CCR7_MEM2MEM_Msk              (0x4000UL)                /*!< MEM2MEM (Bitfield-Mask: 0x01)                         */
/* ========================================================  CNDTR7  ========================================================= */
#define DMA_CNDTR7_NDT_Pos                (0UL)                     /*!< NDT (Bit 0)                                           */
#define DMA_CNDTR7_NDT_Msk                (0xffffUL)                /*!< NDT (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CPAR7  ========================================================= */
#define DMA_CPAR7_PA_Pos                  (0UL)                     /*!< PA (Bit 0)                                            */
#define DMA_CPAR7_PA_Msk                  (0xffffffffUL)            /*!< PA (Bitfield-Mask: 0xffffffff)                        */
/* =========================================================  CMAR7  ========================================================= */
#define DMA_CMAR7_MA_Pos                  (0UL)                     /*!< MA (Bit 0)                                            */
#define DMA_CMAR7_MA_Msk                  (0xffffffffUL)            /*!< MA (Bitfield-Mask: 0xffffffff)                        */


/* =========================================================================================================================== */
/* ================                                           eCAP                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
#define eCAP_CR1_CKD_Pos                  (8UL)                     /*!< CKD (Bit 8)                                           */
#define eCAP_CR1_CKD_Msk                  (0x300UL)                 /*!< CKD (Bitfield-Mask: 0x03)                             */
#define eCAP_CR1_ARPE_Pos                 (7UL)                     /*!< ARPE (Bit 7)                                          */
#define eCAP_CR1_ARPE_Msk                 (0x80UL)                  /*!< ARPE (Bitfield-Mask: 0x01)                            */
#define eCAP_CR1_CMS_Pos                  (5UL)                     /*!< CMS (Bit 5)                                           */
#define eCAP_CR1_CMS_Msk                  (0x60UL)                  /*!< CMS (Bitfield-Mask: 0x03)                             */
#define eCAP_CR1_DIR_Pos                  (4UL)                     /*!< DIR (Bit 4)                                           */
#define eCAP_CR1_DIR_Msk                  (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define eCAP_CR1_OPM_Pos                  (3UL)                     /*!< OPM (Bit 3)                                           */
#define eCAP_CR1_OPM_Msk                  (0x8UL)                   /*!< OPM (Bitfield-Mask: 0x01)                             */
#define eCAP_CR1_URS_Pos                  (2UL)                     /*!< URS (Bit 2)                                           */
#define eCAP_CR1_URS_Msk                  (0x4UL)                   /*!< URS (Bitfield-Mask: 0x01)                             */
#define eCAP_CR1_UDIS_Pos                 (1UL)                     /*!< UDIS (Bit 1)                                          */
#define eCAP_CR1_UDIS_Msk                 (0x2UL)                   /*!< UDIS (Bitfield-Mask: 0x01)                            */
#define eCAP_CR1_CEN_Pos                  (0UL)                     /*!< CEN (Bit 0)                                           */
#define eCAP_CR1_CEN_Msk                  (0x1UL)                   /*!< CEN (Bitfield-Mask: 0x01)                             */
/* ==========================================================  CR2  ========================================================== */
#define eCAP_CR2_TI1S_Pos                 (7UL)                     /*!< TI1S (Bit 7)                                          */
#define eCAP_CR2_TI1S_Msk                 (0x80UL)                  /*!< TI1S (Bitfield-Mask: 0x01)                            */
#define eCAP_CR2_MMS_Pos                  (4UL)                     /*!< MMS (Bit 4)                                           */
#define eCAP_CR2_MMS_Msk                  (0x70UL)                  /*!< MMS (Bitfield-Mask: 0x07)                             */
#define eCAP_CR2_CCDS_Pos                 (3UL)                     /*!< CCDS (Bit 3)                                          */
#define eCAP_CR2_CCDS_Msk                 (0x8UL)                   /*!< CCDS (Bitfield-Mask: 0x01)                            */
/* =========================================================  SMCR  ========================================================== */
#define eCAP_SMCR_ETP_Pos                 (15UL)                    /*!< ETP (Bit 15)                                          */
#define eCAP_SMCR_ETP_Msk                 (0x8000UL)                /*!< ETP (Bitfield-Mask: 0x01)                             */
#define eCAP_SMCR_ECE_Pos                 (14UL)                    /*!< ECE (Bit 14)                                          */
#define eCAP_SMCR_ECE_Msk                 (0x4000UL)                /*!< ECE (Bitfield-Mask: 0x01)                             */
#define eCAP_SMCR_ETPS_Pos                (12UL)                    /*!< ETPS (Bit 12)                                         */
#define eCAP_SMCR_ETPS_Msk                (0x3000UL)                /*!< ETPS (Bitfield-Mask: 0x03)                            */
#define eCAP_SMCR_ETF_Pos                 (8UL)                     /*!< ETF (Bit 8)                                           */
#define eCAP_SMCR_ETF_Msk                 (0xf00UL)                 /*!< ETF (Bitfield-Mask: 0x0f)                             */
#define eCAP_SMCR_MSM_Pos                 (7UL)                     /*!< MSM (Bit 7)                                           */
#define eCAP_SMCR_MSM_Msk                 (0x80UL)                  /*!< MSM (Bitfield-Mask: 0x01)                             */
#define eCAP_SMCR_TS_Pos                  (4UL)                     /*!< TS (Bit 4)                                            */
#define eCAP_SMCR_TS_Msk                  (0x70UL)                  /*!< TS (Bitfield-Mask: 0x07)                              */
#define eCAP_SMCR_SMS_Pos                 (0UL)                     /*!< SMS (Bit 0)                                           */
#define eCAP_SMCR_SMS_Msk                 (0x7UL)                   /*!< SMS (Bitfield-Mask: 0x07)                             */
/* =========================================================  DIER  ========================================================== */
#define eCAP_DIER_TDE_Pos                 (14UL)                    /*!< TDE (Bit 14)                                          */
#define eCAP_DIER_TDE_Msk                 (0x4000UL)                /*!< TDE (Bitfield-Mask: 0x01)                             */
#define eCAP_DIER_CC4DE_Pos               (12UL)                    /*!< CC4DE (Bit 12)                                        */
#define eCAP_DIER_CC4DE_Msk               (0x1000UL)                /*!< CC4DE (Bitfield-Mask: 0x01)                           */
#define eCAP_DIER_CC3DE_Pos               (11UL)                    /*!< CC3DE (Bit 11)                                        */
#define eCAP_DIER_CC3DE_Msk               (0x800UL)                 /*!< CC3DE (Bitfield-Mask: 0x01)                           */
#define eCAP_DIER_CC2DE_Pos               (10UL)                    /*!< CC2DE (Bit 10)                                        */
#define eCAP_DIER_CC2DE_Msk               (0x400UL)                 /*!< CC2DE (Bitfield-Mask: 0x01)                           */
#define eCAP_DIER_CC1DE_Pos               (9UL)                     /*!< CC1DE (Bit 9)                                         */
#define eCAP_DIER_CC1DE_Msk               (0x200UL)                 /*!< CC1DE (Bitfield-Mask: 0x01)                           */
#define eCAP_DIER_UDE_Pos                 (8UL)                     /*!< UDE (Bit 8)                                           */
#define eCAP_DIER_UDE_Msk                 (0x100UL)                 /*!< UDE (Bitfield-Mask: 0x01)                             */
#define eCAP_DIER_TIE_Pos                 (6UL)                     /*!< TIE (Bit 6)                                           */
#define eCAP_DIER_TIE_Msk                 (0x40UL)                  /*!< TIE (Bitfield-Mask: 0x01)                             */
#define eCAP_DIER_CC4IE_Pos               (4UL)                     /*!< CC4IE (Bit 4)                                         */
#define eCAP_DIER_CC4IE_Msk               (0x10UL)                  /*!< CC4IE (Bitfield-Mask: 0x01)                           */
#define eCAP_DIER_CC3IE_Pos               (3UL)                     /*!< CC3IE (Bit 3)                                         */
#define eCAP_DIER_CC3IE_Msk               (0x8UL)                   /*!< CC3IE (Bitfield-Mask: 0x01)                           */
#define eCAP_DIER_CC2IE_Pos               (2UL)                     /*!< CC2IE (Bit 2)                                         */
#define eCAP_DIER_CC2IE_Msk               (0x4UL)                   /*!< CC2IE (Bitfield-Mask: 0x01)                           */
#define eCAP_DIER_CC1IE_Pos               (1UL)                     /*!< CC1IE (Bit 1)                                         */
#define eCAP_DIER_CC1IE_Msk               (0x2UL)                   /*!< CC1IE (Bitfield-Mask: 0x01)                           */
#define eCAP_DIER_UIE_Pos                 (0UL)                     /*!< UIE (Bit 0)                                           */
#define eCAP_DIER_UIE_Msk                 (0x1UL)                   /*!< UIE (Bitfield-Mask: 0x01)                             */
/* ==========================================================  SR  =========================================================== */
#define eCAP_SR_CC4OF_Pos                 (12UL)                    /*!< CC4OF (Bit 12)                                        */
#define eCAP_SR_CC4OF_Msk                 (0x1000UL)                /*!< CC4OF (Bitfield-Mask: 0x01)                           */
#define eCAP_SR_CC3OF_Pos                 (11UL)                    /*!< CC3OF (Bit 11)                                        */
#define eCAP_SR_CC3OF_Msk                 (0x800UL)                 /*!< CC3OF (Bitfield-Mask: 0x01)                           */
#define eCAP_SR_CC2OF_Pos                 (10UL)                    /*!< CC2OF (Bit 10)                                        */
#define eCAP_SR_CC2OF_Msk                 (0x400UL)                 /*!< CC2OF (Bitfield-Mask: 0x01)                           */
#define eCAP_SR_CC1OF_Pos                 (9UL)                     /*!< CC1OF (Bit 9)                                         */
#define eCAP_SR_CC1OF_Msk                 (0x200UL)                 /*!< CC1OF (Bitfield-Mask: 0x01)                           */
#define eCAP_SR_TIF_Pos                   (6UL)                     /*!< TIF (Bit 6)                                           */
#define eCAP_SR_TIF_Msk                   (0x40UL)                  /*!< TIF (Bitfield-Mask: 0x01)                             */
#define eCAP_SR_CC4IF_Pos                 (4UL)                     /*!< CC4IF (Bit 4)                                         */
#define eCAP_SR_CC4IF_Msk                 (0x10UL)                  /*!< CC4IF (Bitfield-Mask: 0x01)                           */
#define eCAP_SR_CC3IF_Pos                 (3UL)                     /*!< CC3IF (Bit 3)                                         */
#define eCAP_SR_CC3IF_Msk                 (0x8UL)                   /*!< CC3IF (Bitfield-Mask: 0x01)                           */
#define eCAP_SR_CC2IF_Pos                 (2UL)                     /*!< CC2IF (Bit 2)                                         */
#define eCAP_SR_CC2IF_Msk                 (0x4UL)                   /*!< CC2IF (Bitfield-Mask: 0x01)                           */
#define eCAP_SR_CC1IF_Pos                 (1UL)                     /*!< CC1IF (Bit 1)                                         */
#define eCAP_SR_CC1IF_Msk                 (0x2UL)                   /*!< CC1IF (Bitfield-Mask: 0x01)                           */
#define eCAP_SR_UIF_Pos                   (0UL)                     /*!< UIF (Bit 0)                                           */
#define eCAP_SR_UIF_Msk                   (0x1UL)                   /*!< UIF (Bitfield-Mask: 0x01)                             */
/* ==========================================================  EGR  ========================================================== */
#define eCAP_EGR_TG_Pos                   (6UL)                     /*!< TG (Bit 6)                                            */
#define eCAP_EGR_TG_Msk                   (0x40UL)                  /*!< TG (Bitfield-Mask: 0x01)                              */
#define eCAP_EGR_CC4G_Pos                 (4UL)                     /*!< CC4G (Bit 4)                                          */
#define eCAP_EGR_CC4G_Msk                 (0x10UL)                  /*!< CC4G (Bitfield-Mask: 0x01)                            */
#define eCAP_EGR_CC3G_Pos                 (3UL)                     /*!< CC3G (Bit 3)                                          */
#define eCAP_EGR_CC3G_Msk                 (0x8UL)                   /*!< CC3G (Bitfield-Mask: 0x01)                            */
#define eCAP_EGR_CC2G_Pos                 (2UL)                     /*!< CC2G (Bit 2)                                          */
#define eCAP_EGR_CC2G_Msk                 (0x4UL)                   /*!< CC2G (Bitfield-Mask: 0x01)                            */
#define eCAP_EGR_CC1G_Pos                 (1UL)                     /*!< CC1G (Bit 1)                                          */
#define eCAP_EGR_CC1G_Msk                 (0x2UL)                   /*!< CC1G (Bitfield-Mask: 0x01)                            */
#define eCAP_EGR_UG_Pos                   (0UL)                     /*!< UG (Bit 0)                                            */
#define eCAP_EGR_UG_Msk                   (0x1UL)                   /*!< UG (Bitfield-Mask: 0x01)                              */
/* =========================================================  CCMR1  ========================================================= */
#define eCAP_CCMR1_IC2F_Pos               (12UL)                    /*!< IC2F (Bit 12)                                         */
#define eCAP_CCMR1_IC2F_Msk               (0xf000UL)                /*!< IC2F (Bitfield-Mask: 0x0f)                            */
#define eCAP_CCMR1_IC2PSC_Pos             (10UL)                    /*!< IC2PSC (Bit 10)                                       */
#define eCAP_CCMR1_IC2PSC_Msk             (0xc00UL)                 /*!< IC2PSC (Bitfield-Mask: 0x03)                          */
#define eCAP_CCMR1_CC2S_Pos               (8UL)                     /*!< CC2S (Bit 8)                                          */
#define eCAP_CCMR1_CC2S_Msk               (0x300UL)                 /*!< CC2S (Bitfield-Mask: 0x03)                            */
#define eCAP_CCMR1_IC1F_Pos               (4UL)                     /*!< IC1F (Bit 4)                                          */
#define eCAP_CCMR1_IC1F_Msk               (0xf0UL)                  /*!< IC1F (Bitfield-Mask: 0x0f)                            */
#define eCAP_CCMR1_IC1PSC_Pos             (2UL)                     /*!< IC1PSC (Bit 2)                                        */
#define eCAP_CCMR1_IC1PSC_Msk             (0xcUL)                   /*!< IC1PSC (Bitfield-Mask: 0x03)                          */
#define eCAP_CCMR1_CC1S_Pos               (0UL)                     /*!< CC1S (Bit 0)                                          */
#define eCAP_CCMR1_CC1S_Msk               (0x3UL)                   /*!< CC1S (Bitfield-Mask: 0x03)                            */
/* =========================================================  CCMR2  ========================================================= */
#define eCAP_CCMR2_IC4F_Pos               (12UL)                    /*!< IC4F (Bit 12)                                         */
#define eCAP_CCMR2_IC4F_Msk               (0xf000UL)                /*!< IC4F (Bitfield-Mask: 0x0f)                            */
#define eCAP_CCMR2_IC4PSC_Pos             (10UL)                    /*!< IC4PSC (Bit 10)                                       */
#define eCAP_CCMR2_IC4PSC_Msk             (0xc00UL)                 /*!< IC4PSC (Bitfield-Mask: 0x03)                          */
#define eCAP_CCMR2_CC4S_Pos               (8UL)                     /*!< CC4S (Bit 8)                                          */
#define eCAP_CCMR2_CC4S_Msk               (0x300UL)                 /*!< CC4S (Bitfield-Mask: 0x03)                            */
#define eCAP_CCMR2_IC3F_Pos               (4UL)                     /*!< IC3F (Bit 4)                                          */
#define eCAP_CCMR2_IC3F_Msk               (0xf0UL)                  /*!< IC3F (Bitfield-Mask: 0x0f)                            */
#define eCAP_CCMR2_IC3PSC_Pos             (2UL)                     /*!< IC3PSC (Bit 2)                                        */
#define eCAP_CCMR2_IC3PSC_Msk             (0xcUL)                   /*!< IC3PSC (Bitfield-Mask: 0x03)                          */
#define eCAP_CCMR2_CC3S_Pos               (0UL)                     /*!< CC3S (Bit 0)                                          */
#define eCAP_CCMR2_CC3S_Msk               (0x3UL)                   /*!< CC3S (Bitfield-Mask: 0x03)                            */
/* =========================================================  CCER  ========================================================== */
#define eCAP_CCER_CC4P_Pos                (13UL)                    /*!< CC4P (Bit 13)                                         */
#define eCAP_CCER_CC4P_Msk                (0x2000UL)                /*!< CC4P (Bitfield-Mask: 0x01)                            */
#define eCAP_CCER_CC4E_Pos                (12UL)                    /*!< CC4E (Bit 12)                                         */
#define eCAP_CCER_CC4E_Msk                (0x1000UL)                /*!< CC4E (Bitfield-Mask: 0x01)                            */
#define eCAP_CCER_CC3P_Pos                (9UL)                     /*!< CC3P (Bit 9)                                          */
#define eCAP_CCER_CC3P_Msk                (0x200UL)                 /*!< CC3P (Bitfield-Mask: 0x01)                            */
#define eCAP_CCER_CC3E_Pos                (8UL)                     /*!< CC3E (Bit 8)                                          */
#define eCAP_CCER_CC3E_Msk                (0x100UL)                 /*!< CC3E (Bitfield-Mask: 0x01)                            */
#define eCAP_CCER_CC2P_Pos                (5UL)                     /*!< CC2P (Bit 5)                                          */
#define eCAP_CCER_CC2P_Msk                (0x20UL)                  /*!< CC2P (Bitfield-Mask: 0x01)                            */
#define eCAP_CCER_CC2E_Pos                (4UL)                     /*!< CC2E (Bit 4)                                          */
#define eCAP_CCER_CC2E_Msk                (0x10UL)                  /*!< CC2E (Bitfield-Mask: 0x01)                            */
#define eCAP_CCER_CC1P_Pos                (1UL)                     /*!< CC1P (Bit 1)                                          */
#define eCAP_CCER_CC1P_Msk                (0x2UL)                   /*!< CC1P (Bitfield-Mask: 0x01)                            */
#define eCAP_CCER_CC1E_Pos                (0UL)                     /*!< CC1E (Bit 0)                                          */
#define eCAP_CCER_CC1E_Msk                (0x1UL)                   /*!< CC1E (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CNT  ========================================================== */
#define eCAP_CNT_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define eCAP_CNT_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  PSC  ========================================================== */
#define eCAP_PSC_PSC_Pos                  (0UL)                     /*!< PSC (Bit 0)                                           */
#define eCAP_PSC_PSC_Msk                  (0xffffUL)                /*!< PSC (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  ARR  ========================================================== */
#define eCAP_ARR_ARR_Pos                  (0UL)                     /*!< ARR (Bit 0)                                           */
#define eCAP_ARR_ARR_Msk                  (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CCR1  ========================================================== */
#define eCAP_CCR1_CCR1_Pos                (0UL)                     /*!< CCR1 (Bit 0)                                          */
#define eCAP_CCR1_CCR1_Msk                (0xffffUL)                /*!< CCR1 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR2  ========================================================== */
#define eCAP_CCR2_CCR2_Pos                (0UL)                     /*!< CCR2 (Bit 0)                                          */
#define eCAP_CCR2_CCR2_Msk                (0xffffUL)                /*!< CCR2 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR3  ========================================================== */
#define eCAP_CCR3_CCR3_Pos                (0UL)                     /*!< CCR3 (Bit 0)                                          */
#define eCAP_CCR3_CCR3_Msk                (0xffffUL)                /*!< CCR3 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR4  ========================================================== */
#define eCAP_CCR4_CCR4_Pos                (0UL)                     /*!< CCR4 (Bit 0)                                          */
#define eCAP_CCR4_CCR4_Msk                (0xffffUL)                /*!< CCR4 (Bitfield-Mask: 0xffff)                          */


/* =========================================================================================================================== */
/* ================                                            TIM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define TIM_CR_TRGEN_Pos                  (2UL)                     /*!< TRGEN (Bit 2)                                         */
#define TIM_CR_TRGEN_Msk                  (0x4UL)                   /*!< TRGEN (Bitfield-Mask: 0x01)                           */
#define TIM_CR_EXTEN_Pos                  (1UL)                     /*!< EXTEN (Bit 1)                                         */
#define TIM_CR_EXTEN_Msk                  (0x2UL)                   /*!< EXTEN (Bitfield-Mask: 0x01)                           */
#define TIM_CR_EN_Pos                     (0UL)                     /*!< EN (Bit 0)                                            */
#define TIM_CR_EN_Msk                     (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CNT  ========================================================== */
#define TIM_CNT_CNT_Pos                   (0UL)                     /*!< CNT (Bit 0)                                           */
#define TIM_CNT_CNT_Msk                   (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  IER  ========================================================== */
#define TIM_IER_OVE_Pos                   (0UL)                     /*!< OVE (Bit 0)                                           */
#define TIM_IER_OVE_Msk                   (0x1UL)                   /*!< OVE (Bitfield-Mask: 0x01)                             */
/* ==========================================================  SR  =========================================================== */
#define TIM_SR_OVF_Pos                    (0UL)                     /*!< OVF (Bit 0)                                           */
#define TIM_SR_OVF_Msk                    (0x1UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
/* ==========================================================  CLR  ========================================================== */
#define TIM_CLR_OVCLR_Pos                 (0UL)                     /*!< OVCLR (Bit 0)                                         */
#define TIM_CLR_OVCLR_Msk                 (0x1UL)                   /*!< OVCLR (Bitfield-Mask: 0x01)                           */
/* ==========================================================  PRD  ========================================================== */
#define TIM_PRD_PRD_Pos                   (0UL)                     /*!< PRD (Bit 0)                                           */
#define TIM_PRD_PRD_Msk                   (0xffffUL)                /*!< PRD (Bitfield-Mask: 0xffff)                           */


/* =========================================================================================================================== */
/* ================                                           WWDG                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define WWDG_CR_WDGA_Pos                  (7UL)                     /*!< WDGA (Bit 7)                                          */
#define WWDG_CR_WDGA_Msk                  (0x80UL)                  /*!< WDGA (Bitfield-Mask: 0x01)                            */
#define WWDG_CR_T_Pos                     (0UL)                     /*!< T (Bit 0)                                             */
#define WWDG_CR_T_Msk                     (0x7fUL)                  /*!< T (Bitfield-Mask: 0x7f)                               */
/* ==========================================================  CFR  ========================================================== */
#define WWDG_CFR_EWI_Pos                  (9UL)                     /*!< EWI (Bit 9)                                           */
#define WWDG_CFR_EWI_Msk                  (0x200UL)                 /*!< EWI (Bitfield-Mask: 0x01)                             */
#define WWDG_CFR_WDGTB_Pos                (7UL)                     /*!< WDGTB (Bit 7)                                         */
#define WWDG_CFR_WDGTB_Msk                (0x180UL)                 /*!< WDGTB (Bitfield-Mask: 0x03)                           */
#define WWDG_CFR_W_Pos                    (0UL)                     /*!< W (Bit 0)                                             */
#define WWDG_CFR_W_Msk                    (0x7fUL)                  /*!< W (Bitfield-Mask: 0x7f)                               */
/* ==========================================================  SR  =========================================================== */
#define WWDG_SR_EWIF_Pos                  (0UL)                     /*!< EWIF (Bit 0)                                          */
#define WWDG_SR_EWIF_Msk                  (0x1UL)                   /*!< EWIF (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                           IWDG                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  KR  =========================================================== */
#define IWDG_KR_KEY_Pos                   (0UL)                     /*!< KEY (Bit 0)                                           */
#define IWDG_KR_KEY_Msk                   (0xffffUL)                /*!< KEY (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  PR  =========================================================== */
#define IWDG_PR_PR_Pos                    (0UL)                     /*!< PR (Bit 0)                                            */
#define IWDG_PR_PR_Msk                    (0x7UL)                   /*!< PR (Bitfield-Mask: 0x07)                              */
/* ==========================================================  RLR  ========================================================== */
#define IWDG_RLR_RL_Pos                   (0UL)                     /*!< RL (Bit 0)                                            */
#define IWDG_RLR_RL_Msk                   (0xfffUL)                 /*!< RL (Bitfield-Mask: 0xfff)                             */
/* ==========================================================  SR  =========================================================== */
#define IWDG_SR_PVU_Pos                   (0UL)                     /*!< PVU (Bit 0)                                           */
#define IWDG_SR_PVU_Msk                   (0x1UL)                   /*!< PVU (Bitfield-Mask: 0x01)                             */
#define IWDG_SR_RVU_Pos                   (1UL)                     /*!< RVU (Bit 1)                                           */
#define IWDG_SR_RVU_Msk                   (0x2UL)                   /*!< RVU (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                            LIN                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  LINCR1  ========================================================= */
#define LIN_LINCR1_NLSE_Pos               (16UL)                    /*!< NLSE (Bit 16)                                         */
#define LIN_LINCR1_NLSE_Msk               (0x10000UL)               /*!< NLSE (Bitfield-Mask: 0x01)                            */
#define LIN_LINCR1_CCD_Pos                (15UL)                    /*!< CCD (Bit 15)                                          */
#define LIN_LINCR1_CCD_Msk                (0x8000UL)                /*!< CCD (Bitfield-Mask: 0x01)                             */
#define LIN_LINCR1_CFD_Pos                (14UL)                    /*!< CFD (Bit 14)                                          */
#define LIN_LINCR1_CFD_Msk                (0x4000UL)                /*!< CFD (Bitfield-Mask: 0x01)                             */
#define LIN_LINCR1_LASE_Pos               (13UL)                    /*!< LASE (Bit 13)                                         */
#define LIN_LINCR1_LASE_Msk               (0x2000UL)                /*!< LASE (Bitfield-Mask: 0x01)                            */
#define LIN_LINCR1_AUTOWU_Pos             (12UL)                    /*!< AUTOWU (Bit 12)                                       */
#define LIN_LINCR1_AUTOWU_Msk             (0x1000UL)                /*!< AUTOWU (Bitfield-Mask: 0x01)                          */
#define LIN_LINCR1_MBL_Pos                (8UL)                     /*!< MBL (Bit 8)                                           */
#define LIN_LINCR1_MBL_Msk                (0xf00UL)                 /*!< MBL (Bitfield-Mask: 0x0f)                             */
#define LIN_LINCR1_BF_Pos                 (7UL)                     /*!< BF (Bit 7)                                            */
#define LIN_LINCR1_BF_Msk                 (0x80UL)                  /*!< BF (Bitfield-Mask: 0x01)                              */
#define LIN_LINCR1_LBKM_Pos               (5UL)                     /*!< LBKM (Bit 5)                                          */
#define LIN_LINCR1_LBKM_Msk               (0x20UL)                  /*!< LBKM (Bitfield-Mask: 0x01)                            */
#define LIN_LINCR1_MME_Pos                (4UL)                     /*!< MME (Bit 4)                                           */
#define LIN_LINCR1_MME_Msk                (0x10UL)                  /*!< MME (Bitfield-Mask: 0x01)                             */
#define LIN_LINCR1_SSBL_Pos               (3UL)                     /*!< SSBL (Bit 3)                                          */
#define LIN_LINCR1_SSBL_Msk               (0x8UL)                   /*!< SSBL (Bitfield-Mask: 0x01)                            */
#define LIN_LINCR1_RBLM_Pos               (2UL)                     /*!< RBLM (Bit 2)                                          */
#define LIN_LINCR1_RBLM_Msk               (0x4UL)                   /*!< RBLM (Bitfield-Mask: 0x01)                            */
#define LIN_LINCR1_SLEEP_Pos              (1UL)                     /*!< SLEEP (Bit 1)                                         */
#define LIN_LINCR1_SLEEP_Msk              (0x2UL)                   /*!< SLEEP (Bitfield-Mask: 0x01)                           */
#define LIN_LINCR1_INIT_Pos               (0UL)                     /*!< INIT (Bit 0)                                          */
#define LIN_LINCR1_INIT_Msk               (0x1UL)                   /*!< INIT (Bitfield-Mask: 0x01)                            */
/* ========================================================  LINIER  ========================================================= */
#define LIN_LINIER_SZIE_Pos               (15UL)                    /*!< SZIE (Bit 15)                                         */
#define LIN_LINIER_SZIE_Msk               (0x8000UL)                /*!< SZIE (Bitfield-Mask: 0x01)                            */
#define LIN_LINIER_OCIE_Pos               (14UL)                    /*!< OCIE (Bit 14)                                         */
#define LIN_LINIER_OCIE_Msk               (0x4000UL)                /*!< OCIE (Bitfield-Mask: 0x01)                            */
#define LIN_LINIER_BEIE_Pos               (13UL)                    /*!< BEIE (Bit 13)                                         */
#define LIN_LINIER_BEIE_Msk               (0x2000UL)                /*!< BEIE (Bitfield-Mask: 0x01)                            */
#define LIN_LINIER_CEIE_Pos               (12UL)                    /*!< CEIE (Bit 12)                                         */
#define LIN_LINIER_CEIE_Msk               (0x1000UL)                /*!< CEIE (Bitfield-Mask: 0x01)                            */
#define LIN_LINIER_HEIE_Pos               (11UL)                    /*!< HEIE (Bit 11)                                         */
#define LIN_LINIER_HEIE_Msk               (0x800UL)                 /*!< HEIE (Bitfield-Mask: 0x01)                            */
#define LIN_LINIER_FEIE_Pos               (8UL)                     /*!< FEIE (Bit 8)                                          */
#define LIN_LINIER_FEIE_Msk               (0x100UL)                 /*!< FEIE (Bitfield-Mask: 0x01)                            */
#define LIN_LINIER_BOIE_Pos               (7UL)                     /*!< BOIE (Bit 7)                                          */
#define LIN_LINIER_BOIE_Msk               (0x80UL)                  /*!< BOIE (Bitfield-Mask: 0x01)                            */
#define LIN_LINIER_LSIE_Pos               (6UL)                     /*!< LSIE (Bit 6)                                          */
#define LIN_LINIER_LSIE_Msk               (0x40UL)                  /*!< LSIE (Bitfield-Mask: 0x01)                            */
#define LIN_LINIER_WUIE_Pos               (5UL)                     /*!< WUIE (Bit 5)                                          */
#define LIN_LINIER_WUIE_Msk               (0x20UL)                  /*!< WUIE (Bitfield-Mask: 0x01)                            */
#define LIN_LINIER_TOIE_Pos               (3UL)                     /*!< TOIE (Bit 3)                                          */
#define LIN_LINIER_TOIE_Msk               (0x8UL)                   /*!< TOIE (Bitfield-Mask: 0x01)                            */
#define LIN_LINIER_DRIE_Pos               (2UL)                     /*!< DRIE (Bit 2)                                          */
#define LIN_LINIER_DRIE_Msk               (0x4UL)                   /*!< DRIE (Bitfield-Mask: 0x01)                            */
#define LIN_LINIER_DTIE_Pos               (1UL)                     /*!< DTIE (Bit 1)                                          */
#define LIN_LINIER_DTIE_Msk               (0x2UL)                   /*!< DTIE (Bitfield-Mask: 0x01)                            */
#define LIN_LINIER_HRIE_Pos               (0UL)                     /*!< HRIE (Bit 0)                                          */
#define LIN_LINIER_HRIE_Msk               (0x1UL)                   /*!< HRIE (Bitfield-Mask: 0x01)                            */
/* =========================================================  LINSR  ========================================================= */
#define LIN_LINSR_AUTOSYNC_COMP_Pos       (19UL)                    /*!< AUTOSYNC_COMP (Bit 19)                                */
#define LIN_LINSR_AUTOSYNC_COMP_Msk       (0x80000UL)               /*!< AUTOSYNC_COMP (Bitfield-Mask: 0x01)                   */
#define LIN_LINSR_RDC_Pos                 (16UL)                    /*!< RDC (Bit 16)                                          */
#define LIN_LINSR_RDC_Msk                 (0x70000UL)               /*!< RDC (Bitfield-Mask: 0x07)                             */
#define LIN_LINSR_LINS_Pos                (12UL)                    /*!< LINS (Bit 12)                                         */
#define LIN_LINSR_LINS_Msk                (0xf000UL)                /*!< LINS (Bitfield-Mask: 0x0f)                            */
#define LIN_LINSR_RMB_Pos                 (9UL)                     /*!< RMB (Bit 9)                                           */
#define LIN_LINSR_RMB_Msk                 (0x200UL)                 /*!< RMB (Bitfield-Mask: 0x01)                             */
#define LIN_LINSR_DRBNE_Pos               (8UL)                     /*!< DRBNE (Bit 8)                                         */
#define LIN_LINSR_DRBNE_Msk               (0x100UL)                 /*!< DRBNE (Bitfield-Mask: 0x01)                           */
#define LIN_LINSR_RXBUSY_Pos              (7UL)                     /*!< RXBUSY (Bit 7)                                        */
#define LIN_LINSR_RXBUSY_Msk              (0x80UL)                  /*!< RXBUSY (Bitfield-Mask: 0x01)                          */
#define LIN_LINSR_RDI_Pos                 (6UL)                     /*!< RDI (Bit 6)                                           */
#define LIN_LINSR_RDI_Msk                 (0x40UL)                  /*!< RDI (Bitfield-Mask: 0x01)                             */
#define LIN_LINSR_WUF_Pos                 (5UL)                     /*!< WUF (Bit 5)                                           */
#define LIN_LINSR_WUF_Msk                 (0x20UL)                  /*!< WUF (Bitfield-Mask: 0x01)                             */
#define LIN_LINSR_DRF_Pos                 (2UL)                     /*!< DRF (Bit 2)                                           */
#define LIN_LINSR_DRF_Msk                 (0x4UL)                   /*!< DRF (Bitfield-Mask: 0x01)                             */
#define LIN_LINSR_DTF_Pos                 (1UL)                     /*!< DTF (Bit 1)                                           */
#define LIN_LINSR_DTF_Msk                 (0x2UL)                   /*!< DTF (Bitfield-Mask: 0x01)                             */
#define LIN_LINSR_HRF_Pos                 (0UL)                     /*!< HRF (Bit 0)                                           */
#define LIN_LINSR_HRF_Msk                 (0x1UL)                   /*!< HRF (Bitfield-Mask: 0x01)                             */
/* ========================================================  LINESR  ========================================================= */
#define LIN_LINESR_SZF_Pos                (15UL)                    /*!< SZF (Bit 15)                                          */
#define LIN_LINESR_SZF_Msk                (0x8000UL)                /*!< SZF (Bitfield-Mask: 0x01)                             */
#define LIN_LINESR_OCF_Pos                (14UL)                    /*!< OCF (Bit 14)                                          */
#define LIN_LINESR_OCF_Msk                (0x4000UL)                /*!< OCF (Bitfield-Mask: 0x01)                             */
#define LIN_LINESR_BEF_Pos                (13UL)                    /*!< BEF (Bit 13)                                          */
#define LIN_LINESR_BEF_Msk                (0x2000UL)                /*!< BEF (Bitfield-Mask: 0x01)                             */
#define LIN_LINESR_CEF_Pos                (12UL)                    /*!< CEF (Bit 12)                                          */
#define LIN_LINESR_CEF_Msk                (0x1000UL)                /*!< CEF (Bitfield-Mask: 0x01)                             */
#define LIN_LINESR_SFEF_Pos               (11UL)                    /*!< SFEF (Bit 11)                                         */
#define LIN_LINESR_SFEF_Msk               (0x800UL)                 /*!< SFEF (Bitfield-Mask: 0x01)                            */
#define LIN_LINESR_SDEF_Pos               (10UL)                    /*!< SDEF (Bit 10)                                         */
#define LIN_LINESR_SDEF_Msk               (0x400UL)                 /*!< SDEF (Bitfield-Mask: 0x01)                            */
#define LIN_LINESR_IDPEF_Pos              (9UL)                     /*!< IDPEF (Bit 9)                                         */
#define LIN_LINESR_IDPEF_Msk              (0x200UL)                 /*!< IDPEF (Bitfield-Mask: 0x01)                           */
#define LIN_LINESR_FEF_Pos                (8UL)                     /*!< FEF (Bit 8)                                           */
#define LIN_LINESR_FEF_Msk                (0x100UL)                 /*!< FEF (Bitfield-Mask: 0x01)                             */
#define LIN_LINESR_BOF_Pos                (7UL)                     /*!< BOF (Bit 7)                                           */
#define LIN_LINESR_BOF_Msk                (0x80UL)                  /*!< BOF (Bitfield-Mask: 0x01)                             */
#define LIN_LINESR_NF_Pos                 (0UL)                     /*!< NF (Bit 0)                                            */
#define LIN_LINESR_NF_Msk                 (0x1UL)                   /*!< NF (Bitfield-Mask: 0x01)                              */
/* ========================================================  UARTCR  ========================================================= */
#define LIN_UARTCR_MIS_Pos                (31UL)                    /*!< MIS (Bit 31)                                          */
#define LIN_UARTCR_MIS_Msk                (0x80000000UL)            /*!< MIS (Bitfield-Mask: 0x01)                             */
#define LIN_UARTCR_CSP_Pos                (28UL)                    /*!< CSP (Bit 28)                                          */
#define LIN_UARTCR_CSP_Msk                (0x70000000UL)            /*!< CSP (Bitfield-Mask: 0x07)                             */
#define LIN_UARTCR_OSR_Pos                (24UL)                    /*!< OSR (Bit 24)                                          */
#define LIN_UARTCR_OSR_Msk                (0xf000000UL)             /*!< OSR (Bitfield-Mask: 0x0f)                             */
#define LIN_UARTCR_ROSE_Pos               (23UL)                    /*!< ROSE (Bit 23)                                         */
#define LIN_UARTCR_ROSE_Msk               (0x800000UL)              /*!< ROSE (Bitfield-Mask: 0x01)                            */
#define LIN_UARTCR_NEF_Pos                (20UL)                    /*!< NEF (Bit 20)                                          */
#define LIN_UARTCR_NEF_Msk                (0x700000UL)              /*!< NEF (Bitfield-Mask: 0x07)                             */
#define LIN_UARTCR_DTU_Pos                (19UL)                    /*!< DTU (Bit 19)                                          */
#define LIN_UARTCR_DTU_Msk                (0x80000UL)               /*!< DTU (Bitfield-Mask: 0x01)                             */
#define LIN_UARTCR_SBUR_Pos               (17UL)                    /*!< SBUR (Bit 17)                                         */
#define LIN_UARTCR_SBUR_Msk               (0x60000UL)               /*!< SBUR (Bitfield-Mask: 0x03)                            */
#define LIN_UARTCR_WLS_Pos                (16UL)                    /*!< WLS (Bit 16)                                          */
#define LIN_UARTCR_WLS_Msk                (0x10000UL)               /*!< WLS (Bitfield-Mask: 0x01)                             */
#define LIN_UARTCR_TDFL_TFC_Pos           (13UL)                    /*!< TDFL_TFC (Bit 13)                                     */
#define LIN_UARTCR_TDFL_TFC_Msk           (0xe000UL)                /*!< TDFL_TFC (Bitfield-Mask: 0x07)                        */
#define LIN_UARTCR_RDFL_RFC_Pos           (10UL)                    /*!< RDFL_RFC (Bit 10)                                     */
#define LIN_UARTCR_RDFL_RFC_Msk           (0x1c00UL)                /*!< RDFL_RFC (Bitfield-Mask: 0x07)                        */
#define LIN_UARTCR_RFBM_Pos               (9UL)                     /*!< RFBM (Bit 9)                                          */
#define LIN_UARTCR_RFBM_Msk               (0x200UL)                 /*!< RFBM (Bitfield-Mask: 0x01)                            */
#define LIN_UARTCR_TFBM_Pos               (8UL)                     /*!< TFBM (Bit 8)                                          */
#define LIN_UARTCR_TFBM_Msk               (0x100UL)                 /*!< TFBM (Bitfield-Mask: 0x01)                            */
#define LIN_UARTCR_WL1_Pos                (7UL)                     /*!< WL1 (Bit 7)                                           */
#define LIN_UARTCR_WL1_Msk                (0x80UL)                  /*!< WL1 (Bitfield-Mask: 0x01)                             */
#define LIN_UARTCR_PC1_Pos                (6UL)                     /*!< PC1 (Bit 6)                                           */
#define LIN_UARTCR_PC1_Msk                (0x40UL)                  /*!< PC1 (Bitfield-Mask: 0x01)                             */
#define LIN_UARTCR_RXEN_Pos               (5UL)                     /*!< RXEN (Bit 5)                                          */
#define LIN_UARTCR_RXEN_Msk               (0x20UL)                  /*!< RXEN (Bitfield-Mask: 0x01)                            */
#define LIN_UARTCR_TXEN_Pos               (4UL)                     /*!< TXEN (Bit 4)                                          */
#define LIN_UARTCR_TXEN_Msk               (0x10UL)                  /*!< TXEN (Bitfield-Mask: 0x01)                            */
#define LIN_UARTCR_PC0_Pos                (3UL)                     /*!< PC0 (Bit 3)                                           */
#define LIN_UARTCR_PC0_Msk                (0x8UL)                   /*!< PC0 (Bitfield-Mask: 0x01)                             */
#define LIN_UARTCR_PCE_Pos                (2UL)                     /*!< PCE (Bit 2)                                           */
#define LIN_UARTCR_PCE_Msk                (0x4UL)                   /*!< PCE (Bitfield-Mask: 0x01)                             */
#define LIN_UARTCR_WL0_Pos                (1UL)                     /*!< WL0 (Bit 1)                                           */
#define LIN_UARTCR_WL0_Msk                (0x2UL)                   /*!< WL0 (Bitfield-Mask: 0x01)                             */
#define LIN_UARTCR_UART_Pos               (0UL)                     /*!< UART (Bit 0)                                          */
#define LIN_UARTCR_UART_Msk               (0x1UL)                   /*!< UART (Bitfield-Mask: 0x01)                            */
/* ========================================================  UARTSR  ========================================================= */
#define LIN_UARTSR_SZF_Pos                (15UL)                    /*!< SZF (Bit 15)                                          */
#define LIN_UARTSR_SZF_Msk                (0x8000UL)                /*!< SZF (Bitfield-Mask: 0x01)                             */
#define LIN_UARTSR_OCF_Pos                (14UL)                    /*!< OCF (Bit 14)                                          */
#define LIN_UARTSR_OCF_Msk                (0x4000UL)                /*!< OCF (Bitfield-Mask: 0x01)                             */
#define LIN_UARTSR_PE_Pos                 (10UL)                    /*!< PE (Bit 10)                                           */
#define LIN_UARTSR_PE_Msk                 (0x3c00UL)                /*!< PE (Bitfield-Mask: 0x0f)                              */
#define LIN_UARTSR_RMB_Pos                (9UL)                     /*!< RMB (Bit 9)                                           */
#define LIN_UARTSR_RMB_Msk                (0x200UL)                 /*!< RMB (Bitfield-Mask: 0x01)                             */
#define LIN_UARTSR_FEF_Pos                (8UL)                     /*!< FEF (Bit 8)                                           */
#define LIN_UARTSR_FEF_Msk                (0x100UL)                 /*!< FEF (Bitfield-Mask: 0x01)                             */
#define LIN_UARTSR_BOF_Pos                (7UL)                     /*!< BOF (Bit 7)                                           */
#define LIN_UARTSR_BOF_Msk                (0x80UL)                  /*!< BOF (Bitfield-Mask: 0x01)                             */
#define LIN_UARTSR_RDI_Pos                (6UL)                     /*!< RDI (Bit 6)                                           */
#define LIN_UARTSR_RDI_Msk                (0x40UL)                  /*!< RDI (Bitfield-Mask: 0x01)                             */
#define LIN_UARTSR_WUF_Pos                (5UL)                     /*!< WUF (Bit 5)                                           */
#define LIN_UARTSR_WUF_Msk                (0x20UL)                  /*!< WUF (Bitfield-Mask: 0x01)                             */
#define LIN_UARTSR_RFNE_Pos               (4UL)                     /*!< RFNE (Bit 4)                                          */
#define LIN_UARTSR_RFNE_Msk               (0x10UL)                  /*!< RFNE (Bitfield-Mask: 0x01)                            */
#define LIN_UARTSR_TO_Pos                 (3UL)                     /*!< TO (Bit 3)                                            */
#define LIN_UARTSR_TO_Msk                 (0x8UL)                   /*!< TO (Bitfield-Mask: 0x01)                              */
#define LIN_UARTSR_DRF_RFE_Pos            (2UL)                     /*!< DRF_RFE (Bit 2)                                       */
#define LIN_UARTSR_DRF_RFE_Msk            (0x4UL)                   /*!< DRF_RFE (Bitfield-Mask: 0x01)                         */
#define LIN_UARTSR_DTF_TFF_Pos            (1UL)                     /*!< DTF_TFF (Bit 1)                                       */
#define LIN_UARTSR_DTF_TFF_Msk            (0x2UL)                   /*!< DTF_TFF (Bitfield-Mask: 0x01)                         */
#define LIN_UARTSR_NF_Pos                 (0UL)                     /*!< NF (Bit 0)                                            */
#define LIN_UARTSR_NF_Msk                 (0x1UL)                   /*!< NF (Bitfield-Mask: 0x01)                              */
/* ========================================================  LINTCSR  ======================================================== */
#define LIN_LINTCSR_MODE_Pos              (10UL)                    /*!< MODE (Bit 10)                                         */
#define LIN_LINTCSR_MODE_Msk              (0x400UL)                 /*!< MODE (Bitfield-Mask: 0x01)                            */
#define LIN_LINTCSR_IOT_Pos               (9UL)                     /*!< IOT (Bit 9)                                           */
#define LIN_LINTCSR_IOT_Msk               (0x200UL)                 /*!< IOT (Bitfield-Mask: 0x01)                             */
#define LIN_LINTCSR_TOCE_Pos              (8UL)                     /*!< TOCE (Bit 8)                                          */
#define LIN_LINTCSR_TOCE_Msk              (0x100UL)                 /*!< TOCE (Bitfield-Mask: 0x01)                            */
#define LIN_LINTCSR_CNT_Pos               (0UL)                     /*!< CNT (Bit 0)                                           */
#define LIN_LINTCSR_CNT_Msk               (0xffUL)                  /*!< CNT (Bitfield-Mask: 0xff)                             */
/* ========================================================  LINOCR  ========================================================= */
#define LIN_LINOCR_OC2_Pos                (8UL)                     /*!< OC2 (Bit 8)                                           */
#define LIN_LINOCR_OC2_Msk                (0xff00UL)                /*!< OC2 (Bitfield-Mask: 0xff)                             */
#define LIN_LINOCR_OC1_Pos                (0UL)                     /*!< OC1 (Bit 0)                                           */
#define LIN_LINOCR_OC1_Msk                (0xffUL)                  /*!< OC1 (Bitfield-Mask: 0xff)                             */
/* ========================================================  LINTOCR  ======================================================== */
#define LIN_LINTOCR_RTO_Pos               (8UL)                     /*!< RTO (Bit 8)                                           */
#define LIN_LINTOCR_RTO_Msk               (0xf00UL)                 /*!< RTO (Bitfield-Mask: 0x0f)                             */
#define LIN_LINTOCR_HTO_Pos               (0UL)                     /*!< HTO (Bit 0)                                           */
#define LIN_LINTOCR_HTO_Msk               (0x7fUL)                  /*!< HTO (Bitfield-Mask: 0x7f)                             */
/* ========================================================  LINFBRR  ======================================================== */
#define LIN_LINFBRR_FBR_Pos               (0UL)                     /*!< FBR (Bit 0)                                           */
#define LIN_LINFBRR_FBR_Msk               (0xfUL)                   /*!< FBR (Bitfield-Mask: 0x0f)                             */
/* ========================================================  LINIBRR  ======================================================== */
#define LIN_LINIBRR_IBR_Pos               (0UL)                     /*!< IBR (Bit 0)                                           */
#define LIN_LINIBRR_IBR_Msk               (0xfffffUL)               /*!< IBR (Bitfield-Mask: 0xfffff)                          */
/* ========================================================  LINCFR  ========================================================= */
#define LIN_LINCFR_CF_Pos                 (0UL)                     /*!< CF (Bit 0)                                            */
#define LIN_LINCFR_CF_Msk                 (0xffUL)                  /*!< CF (Bitfield-Mask: 0xff)                              */
/* ========================================================  LINCR2  ========================================================= */
#define LIN_LINCR2_TBDE_Pos               (15UL)                    /*!< TBDE (Bit 15)                                         */
#define LIN_LINCR2_TBDE_Msk               (0x8000UL)                /*!< TBDE (Bitfield-Mask: 0x01)                            */
#define LIN_LINCR2_IOBE_Pos               (14UL)                    /*!< IOBE (Bit 14)                                         */
#define LIN_LINCR2_IOBE_Msk               (0x4000UL)                /*!< IOBE (Bitfield-Mask: 0x01)                            */
#define LIN_LINCR2_IOPE_Pos               (13UL)                    /*!< IOPE (Bit 13)                                         */
#define LIN_LINCR2_IOPE_Msk               (0x2000UL)                /*!< IOPE (Bitfield-Mask: 0x01)                            */
#define LIN_LINCR2_WURQ_Pos               (12UL)                    /*!< WURQ (Bit 12)                                         */
#define LIN_LINCR2_WURQ_Msk               (0x1000UL)                /*!< WURQ (Bitfield-Mask: 0x01)                            */
#define LIN_LINCR2_DDRQ_Pos               (11UL)                    /*!< DDRQ (Bit 11)                                         */
#define LIN_LINCR2_DDRQ_Msk               (0x800UL)                 /*!< DDRQ (Bitfield-Mask: 0x01)                            */
#define LIN_LINCR2_DTRQ_Pos               (10UL)                    /*!< DTRQ (Bit 10)                                         */
#define LIN_LINCR2_DTRQ_Msk               (0x400UL)                 /*!< DTRQ (Bitfield-Mask: 0x01)                            */
#define LIN_LINCR2_ABRQ_Pos               (9UL)                     /*!< ABRQ (Bit 9)                                          */
#define LIN_LINCR2_ABRQ_Msk               (0x200UL)                 /*!< ABRQ (Bitfield-Mask: 0x01)                            */
#define LIN_LINCR2_HTRQ_Pos               (8UL)                     /*!< HTRQ (Bit 8)                                          */
#define LIN_LINCR2_HTRQ_Msk               (0x100UL)                 /*!< HTRQ (Bitfield-Mask: 0x01)                            */
/* =========================================================  BIDR  ========================================================== */
#define LIN_BIDR_CCS_A_Pos                (16UL)                    /*!< CCS_A (Bit 16)                                        */
#define LIN_BIDR_CCS_A_Msk                (0x10000UL)               /*!< CCS_A (Bitfield-Mask: 0x01)                           */
#define LIN_BIDR_DFL_Pos                  (10UL)                    /*!< DFL (Bit 10)                                          */
#define LIN_BIDR_DFL_Msk                  (0x1c00UL)                /*!< DFL (Bitfield-Mask: 0x07)                             */
#define LIN_BIDR_DIR_Pos                  (9UL)                     /*!< DIR (Bit 9)                                           */
#define LIN_BIDR_DIR_Msk                  (0x200UL)                 /*!< DIR (Bitfield-Mask: 0x01)                             */
#define LIN_BIDR_CCS_Pos                  (8UL)                     /*!< CCS (Bit 8)                                           */
#define LIN_BIDR_CCS_Msk                  (0x100UL)                 /*!< CCS (Bitfield-Mask: 0x01)                             */
#define LIN_BIDR_ID_Pos                   (0UL)                     /*!< ID (Bit 0)                                            */
#define LIN_BIDR_ID_Msk                   (0x3fUL)                  /*!< ID (Bitfield-Mask: 0x3f)                              */
/* =========================================================  BDRL  ========================================================== */
#define LIN_BDRL_DATA0_Pos                (0UL)                     /*!< DATA0 (Bit 0)                                         */
#define LIN_BDRL_DATA0_Msk                (0xffUL)                  /*!< DATA0 (Bitfield-Mask: 0xff)                           */
#define LIN_BDRL_DATA1_Pos                (8UL)                     /*!< DATA1 (Bit 8)                                         */
#define LIN_BDRL_DATA1_Msk                (0xff00UL)                /*!< DATA1 (Bitfield-Mask: 0xff)                           */
#define LIN_BDRL_DATA2_Pos                (16UL)                    /*!< DATA2 (Bit 16)                                        */
#define LIN_BDRL_DATA2_Msk                (0xff0000UL)              /*!< DATA2 (Bitfield-Mask: 0xff)                           */
#define LIN_BDRL_DATA3_Pos                (24UL)                    /*!< DATA3 (Bit 24)                                        */
#define LIN_BDRL_DATA3_Msk                (0xff000000UL)            /*!< DATA3 (Bitfield-Mask: 0xff)                           */
/* =========================================================  BDRM  ========================================================== */
#define LIN_BDRM_DATA4_Pos                (0UL)                     /*!< DATA4 (Bit 0)                                         */
#define LIN_BDRM_DATA4_Msk                (0xffUL)                  /*!< DATA4 (Bitfield-Mask: 0xff)                           */
#define LIN_BDRM_DATA5_Pos                (8UL)                     /*!< DATA5 (Bit 8)                                         */
#define LIN_BDRM_DATA5_Msk                (0xff00UL)                /*!< DATA5 (Bitfield-Mask: 0xff)                           */
#define LIN_BDRM_DATA6_Pos                (16UL)                    /*!< DATA6 (Bit 16)                                        */
#define LIN_BDRM_DATA6_Msk                (0xff0000UL)              /*!< DATA6 (Bitfield-Mask: 0xff)                           */
#define LIN_BDRM_DATA7_Pos                (24UL)                    /*!< DATA7 (Bit 24)                                        */
#define LIN_BDRM_DATA7_Msk                (0xff000000UL)            /*!< DATA7 (Bitfield-Mask: 0xff)                           */
/* =========================================================  IFER  ========================================================== */
#define LIN_IFER_FACT_Pos                 (0UL)                     /*!< FACT (Bit 0)                                          */
#define LIN_IFER_FACT_Msk                 (0xffffUL)                /*!< FACT (Bitfield-Mask: 0xffff)                          */
/* =========================================================  IFMI  ========================================================== */
#define LIN_IFMI_IFMI_Pos                 (0UL)                     /*!< IFMI (Bit 0)                                          */
#define LIN_IFMI_IFMI_Msk                 (0x1fUL)                  /*!< IFMI (Bitfield-Mask: 0x1f)                            */
/* =========================================================  IFMR  ========================================================== */
#define LIN_IFMR_IFM_Pos                  (0UL)                     /*!< IFM (Bit 0)                                           */
#define LIN_IFMR_IFM_Msk                  (0xffUL)                  /*!< IFM (Bitfield-Mask: 0xff)                             */
/* =========================================================  IFCR  ========================================================== */
#define LIN_IFCR_DFL_Pos                  (10UL)                    /*!< DFL (Bit 10)                                          */
#define LIN_IFCR_DFL_Msk                  (0x1c00UL)                /*!< DFL (Bitfield-Mask: 0x07)                             */
#define LIN_IFCR_DIR_Pos                  (9UL)                     /*!< DIR (Bit 9)                                           */
#define LIN_IFCR_DIR_Msk                  (0x200UL)                 /*!< DIR (Bitfield-Mask: 0x01)                             */
#define LIN_IFCR_CCS_Pos                  (8UL)                     /*!< CCS (Bit 8)                                           */
#define LIN_IFCR_CCS_Msk                  (0x100UL)                 /*!< CCS (Bitfield-Mask: 0x01)                             */
#define LIN_IFCR_ID_Pos                   (0UL)                     /*!< ID (Bit 0)                                            */
#define LIN_IFCR_ID_Msk                   (0x3fUL)                  /*!< ID (Bitfield-Mask: 0x3f)                              */
/* ==========================================================  GCR  ========================================================== */
#define LIN_GCR_TDFBM_Pos                 (5UL)                     /*!< TDFBM (Bit 5)                                         */
#define LIN_GCR_TDFBM_Msk                 (0x20UL)                  /*!< TDFBM (Bitfield-Mask: 0x01)                           */
#define LIN_GCR_RDFBM_Pos                 (4UL)                     /*!< RDFBM (Bit 4)                                         */
#define LIN_GCR_RDFBM_Msk                 (0x10UL)                  /*!< RDFBM (Bitfield-Mask: 0x01)                           */
#define LIN_GCR_TDLIS_Pos                 (3UL)                     /*!< TDLIS (Bit 3)                                         */
#define LIN_GCR_TDLIS_Msk                 (0x8UL)                   /*!< TDLIS (Bitfield-Mask: 0x01)                           */
#define LIN_GCR_RDLIS_Pos                 (2UL)                     /*!< RDLIS (Bit 2)                                         */
#define LIN_GCR_RDLIS_Msk                 (0x4UL)                   /*!< RDLIS (Bitfield-Mask: 0x01)                           */
#define LIN_GCR_STOP_Pos                  (1UL)                     /*!< STOP (Bit 1)                                          */
#define LIN_GCR_STOP_Msk                  (0x2UL)                   /*!< STOP (Bitfield-Mask: 0x01)                            */
#define LIN_GCR_SR_Pos                    (0UL)                     /*!< SR (Bit 0)                                            */
#define LIN_GCR_SR_Msk                    (0x1UL)                   /*!< SR (Bitfield-Mask: 0x01)                              */
/* ========================================================  UARTPTO  ======================================================== */
#define LIN_UARTPTO_PTO_Pos               (0UL)                     /*!< PTO (Bit 0)                                           */
#define LIN_UARTPTO_PTO_Msk               (0xfffUL)                 /*!< PTO (Bitfield-Mask: 0xfff)                            */
/* ========================================================  UARTCTO  ======================================================== */
#define LIN_UARTCTO_CTO_Pos               (0UL)                     /*!< CTO (Bit 0)                                           */
#define LIN_UARTCTO_CTO_Msk               (0xfffUL)                 /*!< CTO (Bitfield-Mask: 0xfff)                            */
/* =======================================================  LINOUTPHY  ======================================================= */
#define LIN_LINOUTPHY_TXEN_Pos            (0UL)                     /*!< TXEN (Bit 0)                                          */
#define LIN_LINOUTPHY_TXEN_Msk            (0x1UL)                   /*!< TXEN (Bitfield-Mask: 0x01)                            */
#define LIN_LINOUTPHY_RXEN_Pos            (1UL)                     /*!< RXEN (Bit 1)                                          */
#define LIN_LINOUTPHY_RXEN_Msk            (0x2UL)                   /*!< RXEN (Bitfield-Mask: 0x01)                            */
#define LIN_LINOUTPHY_TXPU_1K_Pos         (2UL)                     /*!< TXPU_1K (Bit 2)                                       */
#define LIN_LINOUTPHY_TXPU_1K_Msk         (0x4UL)                   /*!< TXPU_1K (Bitfield-Mask: 0x01)                         */
#define LIN_LINOUTPHY_TXPU_30K_Pos        (3UL)                     /*!< TXPU_30K (Bit 3)                                      */
#define LIN_LINOUTPHY_TXPU_30K_Msk        (0x8UL)                   /*!< TXPU_30K (Bitfield-Mask: 0x01)                        */
#define LIN_LINOUTPHY_SLOPE_ENHANCE_Pos   (4UL)                     /*!< SLOPE_ENHANCE (Bit 4)                                 */
#define LIN_LINOUTPHY_SLOPE_ENHANCE_Msk   (0x10UL)                  /*!< SLOPE_ENHANCE (Bitfield-Mask: 0x01)                   */
#define LIN_LINOUTPHY_SLOPE_SEL_Pos       (5UL)                     /*!< SLOPE_SEL (Bit 5)                                     */
#define LIN_LINOUTPHY_SLOPE_SEL_Msk       (0x1e0UL)                 /*!< SLOPE_SEL (Bitfield-Mask: 0x0f)                       */
#define LIN_LINOUTPHY_STR_Pos             (9UL)                     /*!< STR (Bit 9)                                           */
#define LIN_LINOUTPHY_STR_Msk             (0x600UL)                 /*!< STR (Bitfield-Mask: 0x03)                             */
/* =======================================================  LININPHY  ======================================================== */
#define LIN_LININPHY_TXEN_Pos             (0UL)                     /*!< TXEN (Bit 0)                                          */
#define LIN_LININPHY_TXEN_Msk             (0x1UL)                   /*!< TXEN (Bitfield-Mask: 0x01)                            */
#define LIN_LININPHY_RXEN_Pos             (1UL)                     /*!< RXEN (Bit 1)                                          */
#define LIN_LININPHY_RXEN_Msk             (0x2UL)                   /*!< RXEN (Bitfield-Mask: 0x01)                            */
#define LIN_LININPHY_TXPU_Pos             (2UL)                     /*!< TXPU (Bit 2)                                          */
#define LIN_LININPHY_TXPU_Msk             (0x4UL)                   /*!< TXPU (Bitfield-Mask: 0x01)                            */
#define LIN_LININPHY_SLOPE_ENHANCE_Pos    (3UL)                     /*!< SLOPE_ENHANCE (Bit 3)                                 */
#define LIN_LININPHY_SLOPE_ENHANCE_Msk    (0x8UL)                   /*!< SLOPE_ENHANCE (Bitfield-Mask: 0x01)                   */
#define LIN_LININPHY_SLOPE_SEL_Pos        (4UL)                     /*!< SLOPE_SEL (Bit 4)                                     */
#define LIN_LININPHY_SLOPE_SEL_Msk        (0xf0UL)                  /*!< SLOPE_SEL (Bitfield-Mask: 0x0f)                       */
#define LIN_LININPHY_STR_Pos              (8UL)                     /*!< STR (Bit 8)                                           */
#define LIN_LININPHY_STR_Msk              (0x300UL)                 /*!< STR (Bitfield-Mask: 0x03)                             */
/* =======================================================  LINSWITCH  ======================================================= */
#define LIN_LINSWITCH_EN_Pos              (0UL)                     /*!< EN (Bit 0)                                            */
#define LIN_LINSWITCH_EN_Msk              (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ======================================================  LINTESTMODE  ====================================================== */
#define LIN_LINTESTMODE_switch_dbg_en_Pos (0UL)                     /*!< switch_dbg_en (Bit 0)                                 */
#define LIN_LINTESTMODE_switch_dbg_en_Msk (0x1UL)                   /*!< switch_dbg_en (Bitfield-Mask: 0x01)                   */
#define LIN_LINTESTMODE_switch_dbg_sel_Pos (1UL)                    /*!< switch_dbg_sel (Bit 1)                                */
#define LIN_LINTESTMODE_switch_dbg_sel_Msk (0x6UL)                  /*!< switch_dbg_sel (Bitfield-Mask: 0x03)                  */
#define LIN_LINTESTMODE_switch_linc_slave_Pos (3UL)                 /*!< switch_linc_slave (Bit 3)                             */
#define LIN_LINTESTMODE_switch_linc_slave_Msk (0x8UL)               /*!< switch_linc_slave (Bitfield-Mask: 0x01)               */
#define LIN_LINTESTMODE_switch_monitor_en_Pos (4UL)                 /*!< switch_monitor_en (Bit 4)                             */
#define LIN_LINTESTMODE_switch_monitor_en_Msk (0x10UL)              /*!< switch_monitor_en (Bitfield-Mask: 0x01)               */
#define LIN_LINTESTMODE_KEY_Pos           (24UL)                    /*!< KEY (Bit 24)                                          */
#define LIN_LINTESTMODE_KEY_Msk           (0xff000000UL)            /*!< KEY (Bitfield-Mask: 0xff)                             */
/* =======================================================  LINPHYCFG  ======================================================= */
#define LIN_LINPHYCFG_TXDUTCNT_Pos        (16UL)                    /*!< TXDUTCNT (Bit 16)                                     */
#define LIN_LINPHYCFG_TXDUTCNT_Msk        (0xff0000UL)              /*!< TXDUTCNT (Bitfield-Mask: 0xff)                        */
#define LIN_LINPHYCFG_DUTSEL_Pos          (3UL)                     /*!< DUTSEL (Bit 3)                                        */
#define LIN_LINPHYCFG_DUTSEL_Msk          (0x8UL)                   /*!< DUTSEL (Bitfield-Mask: 0x01)                          */
#define LIN_LINPHYCFG_DUTEN_Pos           (2UL)                     /*!< DUTEN (Bit 2)                                         */
#define LIN_LINPHYCFG_DUTEN_Msk           (0x4UL)                   /*!< DUTEN (Bitfield-Mask: 0x01)                           */
#define LIN_LINPHYCFG_MTOTEN_Pos          (1UL)                     /*!< MTOTEN (Bit 1)                                        */
#define LIN_LINPHYCFG_MTOTEN_Msk          (0x2UL)                   /*!< MTOTEN (Bitfield-Mask: 0x01)                          */
#define LIN_LINPHYCFG_STOTEN_Pos          (0UL)                     /*!< STOTEN (Bit 0)                                        */
#define LIN_LINPHYCFG_STOTEN_Msk          (0x1UL)                   /*!< STOTEN (Bitfield-Mask: 0x01)                          */
/* =======================================================  LINPHYIE  ======================================================== */
#define LIN_LINPHYIE_MTXTOE_Pos           (1UL)                     /*!< MTXTOE (Bit 1)                                        */
#define LIN_LINPHYIE_MTXTOE_Msk           (0x2UL)                   /*!< MTXTOE (Bitfield-Mask: 0x01)                          */
#define LIN_LINPHYIE_STXTOE_Pos           (0UL)                     /*!< STXTOE (Bit 0)                                        */
#define LIN_LINPHYIE_STXTOE_Msk           (0x1UL)                   /*!< STXTOE (Bitfield-Mask: 0x01)                          */
/* =======================================================  LINPHYSR  ======================================================== */
#define LIN_LINPHYSR_MTXTOF_Pos           (1UL)                     /*!< MTXTOF (Bit 1)                                        */
#define LIN_LINPHYSR_MTXTOF_Msk           (0x2UL)                   /*!< MTXTOF (Bitfield-Mask: 0x01)                          */
#define LIN_LINPHYSR_STXTOF_Pos           (0UL)                     /*!< STXTOF (Bit 0)                                        */
#define LIN_LINPHYSR_STXTOF_Msk           (0x1UL)                   /*!< STXTOF (Bitfield-Mask: 0x01)                          */
/* =======================================================  LINPHYCLR  ======================================================= */
#define LIN_LINPHYCLR_MTXTOCLR_Pos        (1UL)                     /*!< MTXTOCLR (Bit 1)                                      */
#define LIN_LINPHYCLR_MTXTOCLR_Msk        (0x2UL)                   /*!< MTXTOCLR (Bitfield-Mask: 0x01)                        */
#define LIN_LINPHYCLR_STXTOCLR_Pos        (0UL)                     /*!< STXTOCLR (Bit 0)                                      */
#define LIN_LINPHYCLR_STXTOCLR_Msk        (0x1UL)                   /*!< STXTOCLR (Bitfield-Mask: 0x01)                        */
/* =====================================================  LINPHYMTOCNT  ====================================================== */
#define LIN_LINPHYMTOCNT_MTOT_Pos         (0UL)                     /*!< MTOT (Bit 0)                                          */
#define LIN_LINPHYMTOCNT_MTOT_Msk         (0x3fffffUL)              /*!< MTOT (Bitfield-Mask: 0x3fffff)                        */
/* =====================================================  LINPHYSTOCNT  ====================================================== */
#define LIN_LINPHYSTOCNT_STOT_Pos         (0UL)                     /*!< STOT (Bit 0)                                          */
#define LIN_LINPHYSTOCNT_STOT_Msk         (0x3fffffUL)              /*!< STOT (Bitfield-Mask: 0x3fffff)                        */


/* =========================================================================================================================== */
/* ================                                            CAN                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CREL  ========================================================== */
#define CAN_CREL_REL_Pos                  (28UL)                    /*!< REL (Bit 28)                                          */
#define CAN_CREL_REL_Msk                  (0xf0000000UL)            /*!< REL (Bitfield-Mask: 0x0f)                             */
#define CAN_CREL_STEP_Pos                 (24UL)                    /*!< STEP (Bit 24)                                         */
#define CAN_CREL_STEP_Msk                 (0xf000000UL)             /*!< STEP (Bitfield-Mask: 0x0f)                            */
#define CAN_CREL_SUBSTEP_Pos              (20UL)                    /*!< SUBSTEP (Bit 20)                                      */
#define CAN_CREL_SUBSTEP_Msk              (0xf00000UL)              /*!< SUBSTEP (Bitfield-Mask: 0x0f)                         */
#define CAN_CREL_YEAR_Pos                 (16UL)                    /*!< YEAR (Bit 16)                                         */
#define CAN_CREL_YEAR_Msk                 (0xf0000UL)               /*!< YEAR (Bitfield-Mask: 0x0f)                            */
#define CAN_CREL_MON_Pos                  (8UL)                     /*!< MON (Bit 8)                                           */
#define CAN_CREL_MON_Msk                  (0xff00UL)                /*!< MON (Bitfield-Mask: 0xff)                             */
#define CAN_CREL_DAY_Pos                  (0UL)                     /*!< DAY (Bit 0)                                           */
#define CAN_CREL_DAY_Msk                  (0xffUL)                  /*!< DAY (Bitfield-Mask: 0xff)                             */
/* =========================================================  ENDN  ========================================================== */
#define CAN_ENDN_ETV_Pos                  (0UL)                     /*!< ETV (Bit 0)                                           */
#define CAN_ENDN_ETV_Msk                  (0xffffffffUL)            /*!< ETV (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  DBTP  ========================================================== */
#define CAN_DBTP_TDC_Pos                  (23UL)                    /*!< TDC (Bit 23)                                          */
#define CAN_DBTP_TDC_Msk                  (0x800000UL)              /*!< TDC (Bitfield-Mask: 0x01)                             */
#define CAN_DBTP_DBRP_Pos                 (16UL)                    /*!< DBRP (Bit 16)                                         */
#define CAN_DBTP_DBRP_Msk                 (0x1f0000UL)              /*!< DBRP (Bitfield-Mask: 0x1f)                            */
#define CAN_DBTP_DTSEG1_Pos               (8UL)                     /*!< DTSEG1 (Bit 8)                                        */
#define CAN_DBTP_DTSEG1_Msk               (0x1f00UL)                /*!< DTSEG1 (Bitfield-Mask: 0x1f)                          */
#define CAN_DBTP_DTSEG2_Pos               (4UL)                     /*!< DTSEG2 (Bit 4)                                        */
#define CAN_DBTP_DTSEG2_Msk               (0xf0UL)                  /*!< DTSEG2 (Bitfield-Mask: 0x0f)                          */
#define CAN_DBTP_DSJW_Pos                 (0UL)                     /*!< DSJW (Bit 0)                                          */
#define CAN_DBTP_DSJW_Msk                 (0xfUL)                   /*!< DSJW (Bitfield-Mask: 0x0f)                            */
/* =========================================================  TEST  ========================================================== */
#define CAN_TEST_SVAL_Pos                 (21UL)                    /*!< SVAL (Bit 21)                                         */
#define CAN_TEST_SVAL_Msk                 (0x200000UL)              /*!< SVAL (Bitfield-Mask: 0x01)                            */
#define CAN_TEST_TXBNS_Pos                (16UL)                    /*!< TXBNS (Bit 16)                                        */
#define CAN_TEST_TXBNS_Msk                (0x1f0000UL)              /*!< TXBNS (Bitfield-Mask: 0x1f)                           */
#define CAN_TEST_PVAL_Pos                 (13UL)                    /*!< PVAL (Bit 13)                                         */
#define CAN_TEST_PVAL_Msk                 (0x2000UL)                /*!< PVAL (Bitfield-Mask: 0x01)                            */
#define CAN_TEST_RX_Pos                   (7UL)                     /*!< RX (Bit 7)                                            */
#define CAN_TEST_RX_Msk                   (0x80UL)                  /*!< RX (Bitfield-Mask: 0x01)                              */
#define CAN_TEST_TX_Pos                   (5UL)                     /*!< TX (Bit 5)                                            */
#define CAN_TEST_TX_Msk                   (0x60UL)                  /*!< TX (Bitfield-Mask: 0x03)                              */
#define CAN_TEST_LBCK_Pos                 (4UL)                     /*!< LBCK (Bit 4)                                          */
#define CAN_TEST_LBCK_Msk                 (0x10UL)                  /*!< LBCK (Bitfield-Mask: 0x01)                            */
/* ==========================================================  RWD  ========================================================== */
#define CAN_RWD_WDV_Pos                   (8UL)                     /*!< WDV (Bit 8)                                           */
#define CAN_RWD_WDV_Msk                   (0xff00UL)                /*!< WDV (Bitfield-Mask: 0xff)                             */
#define CAN_RWD_WDC_Pos                   (0UL)                     /*!< WDC (Bit 0)                                           */
#define CAN_RWD_WDC_Msk                   (0xffUL)                  /*!< WDC (Bitfield-Mask: 0xff)                             */
/* =========================================================  CCCR  ========================================================== */
#define CAN_CCCR_NISO_Pos                 (15UL)                    /*!< NISO (Bit 15)                                         */
#define CAN_CCCR_NISO_Msk                 (0x8000UL)                /*!< NISO (Bitfield-Mask: 0x01)                            */
#define CAN_CCCR_TXP_Pos                  (14UL)                    /*!< TXP (Bit 14)                                          */
#define CAN_CCCR_TXP_Msk                  (0x4000UL)                /*!< TXP (Bitfield-Mask: 0x01)                             */
#define CAN_CCCR_EFBI_Pos                 (13UL)                    /*!< EFBI (Bit 13)                                         */
#define CAN_CCCR_EFBI_Msk                 (0x2000UL)                /*!< EFBI (Bitfield-Mask: 0x01)                            */
#define CAN_CCCR_PXHD_Pos                 (12UL)                    /*!< PXHD (Bit 12)                                         */
#define CAN_CCCR_PXHD_Msk                 (0x1000UL)                /*!< PXHD (Bitfield-Mask: 0x01)                            */
#define CAN_CCCR_WMM_Pos                  (11UL)                    /*!< WMM (Bit 11)                                          */
#define CAN_CCCR_WMM_Msk                  (0x800UL)                 /*!< WMM (Bitfield-Mask: 0x01)                             */
#define CAN_CCCR_UTSU_Pos                 (10UL)                    /*!< UTSU (Bit 10)                                         */
#define CAN_CCCR_UTSU_Msk                 (0x400UL)                 /*!< UTSU (Bitfield-Mask: 0x01)                            */
#define CAN_CCCR_BRSE_Pos                 (9UL)                     /*!< BRSE (Bit 9)                                          */
#define CAN_CCCR_BRSE_Msk                 (0x200UL)                 /*!< BRSE (Bitfield-Mask: 0x01)                            */
#define CAN_CCCR_FDOE_Pos                 (8UL)                     /*!< FDOE (Bit 8)                                          */
#define CAN_CCCR_FDOE_Msk                 (0x100UL)                 /*!< FDOE (Bitfield-Mask: 0x01)                            */
#define CAN_CCCR_TEST_Pos                 (7UL)                     /*!< TEST (Bit 7)                                          */
#define CAN_CCCR_TEST_Msk                 (0x80UL)                  /*!< TEST (Bitfield-Mask: 0x01)                            */
#define CAN_CCCR_DAR_Pos                  (6UL)                     /*!< DAR (Bit 6)                                           */
#define CAN_CCCR_DAR_Msk                  (0x40UL)                  /*!< DAR (Bitfield-Mask: 0x01)                             */
#define CAN_CCCR_MON_Pos                  (5UL)                     /*!< MON (Bit 5)                                           */
#define CAN_CCCR_MON_Msk                  (0x20UL)                  /*!< MON (Bitfield-Mask: 0x01)                             */
#define CAN_CCCR_CSR_Pos                  (4UL)                     /*!< CSR (Bit 4)                                           */
#define CAN_CCCR_CSR_Msk                  (0x10UL)                  /*!< CSR (Bitfield-Mask: 0x01)                             */
#define CAN_CCCR_CSA_Pos                  (3UL)                     /*!< CSA (Bit 3)                                           */
#define CAN_CCCR_CSA_Msk                  (0x8UL)                   /*!< CSA (Bitfield-Mask: 0x01)                             */
#define CAN_CCCR_ASM_Pos                  (2UL)                     /*!< ASM (Bit 2)                                           */
#define CAN_CCCR_ASM_Msk                  (0x4UL)                   /*!< ASM (Bitfield-Mask: 0x01)                             */
#define CAN_CCCR_CCE_Pos                  (1UL)                     /*!< CCE (Bit 1)                                           */
#define CAN_CCCR_CCE_Msk                  (0x2UL)                   /*!< CCE (Bitfield-Mask: 0x01)                             */
#define CAN_CCCR_INIT_Pos                 (0UL)                     /*!< INIT (Bit 0)                                          */
#define CAN_CCCR_INIT_Msk                 (0x1UL)                   /*!< INIT (Bitfield-Mask: 0x01)                            */
/* =========================================================  NBTP  ========================================================== */
#define CAN_NBTP_NSJW_Pos                 (25UL)                    /*!< NSJW (Bit 25)                                         */
#define CAN_NBTP_NSJW_Msk                 (0xfe000000UL)            /*!< NSJW (Bitfield-Mask: 0x7f)                            */
#define CAN_NBTP_NBRP_Pos                 (16UL)                    /*!< NBRP (Bit 16)                                         */
#define CAN_NBTP_NBRP_Msk                 (0x1ff0000UL)             /*!< NBRP (Bitfield-Mask: 0x1ff)                           */
#define CAN_NBTP_NTSEG1_Pos               (8UL)                     /*!< NTSEG1 (Bit 8)                                        */
#define CAN_NBTP_NTSEG1_Msk               (0xff00UL)                /*!< NTSEG1 (Bitfield-Mask: 0xff)                          */
#define CAN_NBTP_NTSEG2_Pos               (0UL)                     /*!< NTSEG2 (Bit 0)                                        */
#define CAN_NBTP_NTSEG2_Msk               (0x7fUL)                  /*!< NTSEG2 (Bitfield-Mask: 0x7f)                          */
/* =========================================================  TSCC  ========================================================== */
#define CAN_TSCC_TCP_Pos                  (16UL)                    /*!< TCP (Bit 16)                                          */
#define CAN_TSCC_TCP_Msk                  (0xf0000UL)               /*!< TCP (Bitfield-Mask: 0x0f)                             */
#define CAN_TSCC_TSS_Pos                  (0UL)                     /*!< TSS (Bit 0)                                           */
#define CAN_TSCC_TSS_Msk                  (0x3UL)                   /*!< TSS (Bitfield-Mask: 0x03)                             */
/* =========================================================  TSCV  ========================================================== */
#define CAN_TSCV_TSC_Pos                  (0UL)                     /*!< TSC (Bit 0)                                           */
#define CAN_TSCV_TSC_Msk                  (0xffffUL)                /*!< TSC (Bitfield-Mask: 0xffff)                           */
/* =========================================================  TOCC  ========================================================== */
#define CAN_TOCC_TOP_Pos                  (16UL)                    /*!< TOP (Bit 16)                                          */
#define CAN_TOCC_TOP_Msk                  (0xffff0000UL)            /*!< TOP (Bitfield-Mask: 0xffff)                           */
#define CAN_TOCC_TOS_Pos                  (1UL)                     /*!< TOS (Bit 1)                                           */
#define CAN_TOCC_TOS_Msk                  (0x6UL)                   /*!< TOS (Bitfield-Mask: 0x03)                             */
#define CAN_TOCC_ETOC_Pos                 (0UL)                     /*!< ETOC (Bit 0)                                          */
#define CAN_TOCC_ETOC_Msk                 (0x1UL)                   /*!< ETOC (Bitfield-Mask: 0x01)                            */
/* =========================================================  TOCV  ========================================================== */
#define CAN_TOCV_TOC_Pos                  (0UL)                     /*!< TOC (Bit 0)                                           */
#define CAN_TOCV_TOC_Msk                  (0xffffUL)                /*!< TOC (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  ECR  ========================================================== */
#define CAN_ECR_CEL_Pos                   (16UL)                    /*!< CEL (Bit 16)                                          */
#define CAN_ECR_CEL_Msk                   (0xff0000UL)              /*!< CEL (Bitfield-Mask: 0xff)                             */
#define CAN_ECR_REC_Pos                   (8UL)                     /*!< REC (Bit 8)                                           */
#define CAN_ECR_REC_Msk                   (0x7f00UL)                /*!< REC (Bitfield-Mask: 0x7f)                             */
#define CAN_ECR_TEC_Pos                   (0UL)                     /*!< TEC (Bit 0)                                           */
#define CAN_ECR_TEC_Msk                   (0xffUL)                  /*!< TEC (Bitfield-Mask: 0xff)                             */
/* ==========================================================  PSR  ========================================================== */
#define CAN_PSR_TDCV_Pos                  (16UL)                    /*!< TDCV (Bit 16)                                         */
#define CAN_PSR_TDCV_Msk                  (0x7f0000UL)              /*!< TDCV (Bitfield-Mask: 0x7f)                            */
#define CAN_PSR_PXE_Pos                   (14UL)                    /*!< PXE (Bit 14)                                          */
#define CAN_PSR_PXE_Msk                   (0x4000UL)                /*!< PXE (Bitfield-Mask: 0x01)                             */
#define CAN_PSR_RFDF_Pos                  (13UL)                    /*!< RFDF (Bit 13)                                         */
#define CAN_PSR_RFDF_Msk                  (0x2000UL)                /*!< RFDF (Bitfield-Mask: 0x01)                            */
#define CAN_PSR_RBRS_Pos                  (12UL)                    /*!< RBRS (Bit 12)                                         */
#define CAN_PSR_RBRS_Msk                  (0x1000UL)                /*!< RBRS (Bitfield-Mask: 0x01)                            */
#define CAN_PSR_RESI_Pos                  (11UL)                    /*!< RESI (Bit 11)                                         */
#define CAN_PSR_RESI_Msk                  (0x800UL)                 /*!< RESI (Bitfield-Mask: 0x01)                            */
#define CAN_PSR_DLEC_Pos                  (8UL)                     /*!< DLEC (Bit 8)                                          */
#define CAN_PSR_DLEC_Msk                  (0x700UL)                 /*!< DLEC (Bitfield-Mask: 0x07)                            */
#define CAN_PSR_BO_Pos                    (7UL)                     /*!< BO (Bit 7)                                            */
#define CAN_PSR_BO_Msk                    (0x80UL)                  /*!< BO (Bitfield-Mask: 0x01)                              */
#define CAN_PSR_EW_Pos                    (6UL)                     /*!< EW (Bit 6)                                            */
#define CAN_PSR_EW_Msk                    (0x40UL)                  /*!< EW (Bitfield-Mask: 0x01)                              */
#define CAN_PSR_EP_Pos                    (5UL)                     /*!< EP (Bit 5)                                            */
#define CAN_PSR_EP_Msk                    (0x20UL)                  /*!< EP (Bitfield-Mask: 0x01)                              */
#define CAN_PSR_ACT_Pos                   (3UL)                     /*!< ACT (Bit 3)                                           */
#define CAN_PSR_ACT_Msk                   (0x18UL)                  /*!< ACT (Bitfield-Mask: 0x03)                             */
#define CAN_PSR_LEC_Pos                   (0UL)                     /*!< LEC (Bit 0)                                           */
#define CAN_PSR_LEC_Msk                   (0x7UL)                   /*!< LEC (Bitfield-Mask: 0x07)                             */
/* =========================================================  TDCR  ========================================================== */
#define CAN_TDCR_TDCO_Pos                 (8UL)                     /*!< TDCO (Bit 8)                                          */
#define CAN_TDCR_TDCO_Msk                 (0x7f00UL)                /*!< TDCO (Bitfield-Mask: 0x7f)                            */
#define CAN_TDCR_TDCF_Pos                 (0UL)                     /*!< TDCF (Bit 0)                                          */
#define CAN_TDCR_TDCF_Msk                 (0x7fUL)                  /*!< TDCF (Bitfield-Mask: 0x7f)                            */
/* ==========================================================  IR  =========================================================== */
#define CAN_IR_ARA_Pos                    (29UL)                    /*!< ARA (Bit 29)                                          */
#define CAN_IR_ARA_Msk                    (0x20000000UL)            /*!< ARA (Bitfield-Mask: 0x01)                             */
#define CAN_IR_PED_Pos                    (28UL)                    /*!< PED (Bit 28)                                          */
#define CAN_IR_PED_Msk                    (0x10000000UL)            /*!< PED (Bitfield-Mask: 0x01)                             */
#define CAN_IR_PEA_Pos                    (27UL)                    /*!< PEA (Bit 27)                                          */
#define CAN_IR_PEA_Msk                    (0x8000000UL)             /*!< PEA (Bitfield-Mask: 0x01)                             */
#define CAN_IR_WDI_Pos                    (26UL)                    /*!< WDI (Bit 26)                                          */
#define CAN_IR_WDI_Msk                    (0x4000000UL)             /*!< WDI (Bitfield-Mask: 0x01)                             */
#define CAN_IR_BO_Pos                     (25UL)                    /*!< BO (Bit 25)                                           */
#define CAN_IR_BO_Msk                     (0x2000000UL)             /*!< BO (Bitfield-Mask: 0x01)                              */
#define CAN_IR_EW_Pos                     (24UL)                    /*!< EW (Bit 24)                                           */
#define CAN_IR_EW_Msk                     (0x1000000UL)             /*!< EW (Bitfield-Mask: 0x01)                              */
#define CAN_IR_EP_Pos                     (23UL)                    /*!< EP (Bit 23)                                           */
#define CAN_IR_EP_Msk                     (0x800000UL)              /*!< EP (Bitfield-Mask: 0x01)                              */
#define CAN_IR_ELO_Pos                    (22UL)                    /*!< ELO (Bit 22)                                          */
#define CAN_IR_ELO_Msk                    (0x400000UL)              /*!< ELO (Bitfield-Mask: 0x01)                             */
#define CAN_IR_BEU_Pos                    (21UL)                    /*!< BEU (Bit 21)                                          */
#define CAN_IR_BEU_Msk                    (0x200000UL)              /*!< BEU (Bitfield-Mask: 0x01)                             */
#define CAN_IR_BEC_Pos                    (20UL)                    /*!< BEC (Bit 20)                                          */
#define CAN_IR_BEC_Msk                    (0x100000UL)              /*!< BEC (Bitfield-Mask: 0x01)                             */
#define CAN_IR_DRX_Pos                    (19UL)                    /*!< DRX (Bit 19)                                          */
#define CAN_IR_DRX_Msk                    (0x80000UL)               /*!< DRX (Bitfield-Mask: 0x01)                             */
#define CAN_IR_TOO_Pos                    (18UL)                    /*!< TOO (Bit 18)                                          */
#define CAN_IR_TOO_Msk                    (0x40000UL)               /*!< TOO (Bitfield-Mask: 0x01)                             */
#define CAN_IR_MRAF_Pos                   (17UL)                    /*!< MRAF (Bit 17)                                         */
#define CAN_IR_MRAF_Msk                   (0x20000UL)               /*!< MRAF (Bitfield-Mask: 0x01)                            */
#define CAN_IR_TSW_Pos                    (16UL)                    /*!< TSW (Bit 16)                                          */
#define CAN_IR_TSW_Msk                    (0x10000UL)               /*!< TSW (Bitfield-Mask: 0x01)                             */
#define CAN_IR_TEFL_Pos                   (15UL)                    /*!< TEFL (Bit 15)                                         */
#define CAN_IR_TEFL_Msk                   (0x8000UL)                /*!< TEFL (Bitfield-Mask: 0x01)                            */
#define CAN_IR_TEFF_Pos                   (14UL)                    /*!< TEFF (Bit 14)                                         */
#define CAN_IR_TEFF_Msk                   (0x4000UL)                /*!< TEFF (Bitfield-Mask: 0x01)                            */
#define CAN_IR_TEFW_Pos                   (13UL)                    /*!< TEFW (Bit 13)                                         */
#define CAN_IR_TEFW_Msk                   (0x2000UL)                /*!< TEFW (Bitfield-Mask: 0x01)                            */
#define CAN_IR_TEFN_Pos                   (12UL)                    /*!< TEFN (Bit 12)                                         */
#define CAN_IR_TEFN_Msk                   (0x1000UL)                /*!< TEFN (Bitfield-Mask: 0x01)                            */
#define CAN_IR_TFE_Pos                    (11UL)                    /*!< TFE (Bit 11)                                          */
#define CAN_IR_TFE_Msk                    (0x800UL)                 /*!< TFE (Bitfield-Mask: 0x01)                             */
#define CAN_IR_TCF_Pos                    (10UL)                    /*!< TCF (Bit 10)                                          */
#define CAN_IR_TCF_Msk                    (0x400UL)                 /*!< TCF (Bitfield-Mask: 0x01)                             */
#define CAN_IR_TC_Pos                     (9UL)                     /*!< TC (Bit 9)                                            */
#define CAN_IR_TC_Msk                     (0x200UL)                 /*!< TC (Bitfield-Mask: 0x01)                              */
#define CAN_IR_HPM_Pos                    (8UL)                     /*!< HPM (Bit 8)                                           */
#define CAN_IR_HPM_Msk                    (0x100UL)                 /*!< HPM (Bitfield-Mask: 0x01)                             */
#define CAN_IR_RF1L_Pos                   (7UL)                     /*!< RF1L (Bit 7)                                          */
#define CAN_IR_RF1L_Msk                   (0x80UL)                  /*!< RF1L (Bitfield-Mask: 0x01)                            */
#define CAN_IR_RF1F_Pos                   (6UL)                     /*!< RF1F (Bit 6)                                          */
#define CAN_IR_RF1F_Msk                   (0x40UL)                  /*!< RF1F (Bitfield-Mask: 0x01)                            */
#define CAN_IR_RF1W_Pos                   (5UL)                     /*!< RF1W (Bit 5)                                          */
#define CAN_IR_RF1W_Msk                   (0x20UL)                  /*!< RF1W (Bitfield-Mask: 0x01)                            */
#define CAN_IR_RF1N_Pos                   (4UL)                     /*!< RF1N (Bit 4)                                          */
#define CAN_IR_RF1N_Msk                   (0x10UL)                  /*!< RF1N (Bitfield-Mask: 0x01)                            */
#define CAN_IR_RF0L_Pos                   (3UL)                     /*!< RF0L (Bit 3)                                          */
#define CAN_IR_RF0L_Msk                   (0x8UL)                   /*!< RF0L (Bitfield-Mask: 0x01)                            */
#define CAN_IR_RF0F_Pos                   (2UL)                     /*!< RF0F (Bit 2)                                          */
#define CAN_IR_RF0F_Msk                   (0x4UL)                   /*!< RF0F (Bitfield-Mask: 0x01)                            */
#define CAN_IR_RF0W_Pos                   (1UL)                     /*!< RF0W (Bit 1)                                          */
#define CAN_IR_RF0W_Msk                   (0x2UL)                   /*!< RF0W (Bitfield-Mask: 0x01)                            */
#define CAN_IR_RF0N_Pos                   (0UL)                     /*!< RF0N (Bit 0)                                          */
#define CAN_IR_RF0N_Msk                   (0x1UL)                   /*!< RF0N (Bitfield-Mask: 0x01)                            */
/* ==========================================================  IE  =========================================================== */
#define CAN_IE_ARAE_Pos                   (29UL)                    /*!< ARAE (Bit 29)                                         */
#define CAN_IE_ARAE_Msk                   (0x20000000UL)            /*!< ARAE (Bitfield-Mask: 0x01)                            */
#define CAN_IE_PEDE_Pos                   (28UL)                    /*!< PEDE (Bit 28)                                         */
#define CAN_IE_PEDE_Msk                   (0x10000000UL)            /*!< PEDE (Bitfield-Mask: 0x01)                            */
#define CAN_IE_PEAE_Pos                   (27UL)                    /*!< PEAE (Bit 27)                                         */
#define CAN_IE_PEAE_Msk                   (0x8000000UL)             /*!< PEAE (Bitfield-Mask: 0x01)                            */
#define CAN_IE_WDIE_Pos                   (26UL)                    /*!< WDIE (Bit 26)                                         */
#define CAN_IE_WDIE_Msk                   (0x4000000UL)             /*!< WDIE (Bitfield-Mask: 0x01)                            */
#define CAN_IE_BOE_Pos                    (25UL)                    /*!< BOE (Bit 25)                                          */
#define CAN_IE_BOE_Msk                    (0x2000000UL)             /*!< BOE (Bitfield-Mask: 0x01)                             */
#define CAN_IE_EWE_Pos                    (24UL)                    /*!< EWE (Bit 24)                                          */
#define CAN_IE_EWE_Msk                    (0x1000000UL)             /*!< EWE (Bitfield-Mask: 0x01)                             */
#define CAN_IE_EPE_Pos                    (23UL)                    /*!< EPE (Bit 23)                                          */
#define CAN_IE_EPE_Msk                    (0x800000UL)              /*!< EPE (Bitfield-Mask: 0x01)                             */
#define CAN_IE_ELOE_Pos                   (22UL)                    /*!< ELOE (Bit 22)                                         */
#define CAN_IE_ELOE_Msk                   (0x400000UL)              /*!< ELOE (Bitfield-Mask: 0x01)                            */
#define CAN_IE_BEUE_Pos                   (21UL)                    /*!< BEUE (Bit 21)                                         */
#define CAN_IE_BEUE_Msk                   (0x200000UL)              /*!< BEUE (Bitfield-Mask: 0x01)                            */
#define CAN_IE_BECE_Pos                   (20UL)                    /*!< BECE (Bit 20)                                         */
#define CAN_IE_BECE_Msk                   (0x100000UL)              /*!< BECE (Bitfield-Mask: 0x01)                            */
#define CAN_IE_DRXE_Pos                   (19UL)                    /*!< DRXE (Bit 19)                                         */
#define CAN_IE_DRXE_Msk                   (0x80000UL)               /*!< DRXE (Bitfield-Mask: 0x01)                            */
#define CAN_IE_TOOE_Pos                   (18UL)                    /*!< TOOE (Bit 18)                                         */
#define CAN_IE_TOOE_Msk                   (0x40000UL)               /*!< TOOE (Bitfield-Mask: 0x01)                            */
#define CAN_IE_MRAFE_Pos                  (17UL)                    /*!< MRAFE (Bit 17)                                        */
#define CAN_IE_MRAFE_Msk                  (0x20000UL)               /*!< MRAFE (Bitfield-Mask: 0x01)                           */
#define CAN_IE_TSWE_Pos                   (16UL)                    /*!< TSWE (Bit 16)                                         */
#define CAN_IE_TSWE_Msk                   (0x10000UL)               /*!< TSWE (Bitfield-Mask: 0x01)                            */
#define CAN_IE_TEFLE_Pos                  (15UL)                    /*!< TEFLE (Bit 15)                                        */
#define CAN_IE_TEFLE_Msk                  (0x8000UL)                /*!< TEFLE (Bitfield-Mask: 0x01)                           */
#define CAN_IE_TEFFE_Pos                  (14UL)                    /*!< TEFFE (Bit 14)                                        */
#define CAN_IE_TEFFE_Msk                  (0x4000UL)                /*!< TEFFE (Bitfield-Mask: 0x01)                           */
#define CAN_IE_TEFWE_Pos                  (13UL)                    /*!< TEFWE (Bit 13)                                        */
#define CAN_IE_TEFWE_Msk                  (0x2000UL)                /*!< TEFWE (Bitfield-Mask: 0x01)                           */
#define CAN_IE_TEFNE_Pos                  (12UL)                    /*!< TEFNE (Bit 12)                                        */
#define CAN_IE_TEFNE_Msk                  (0x1000UL)                /*!< TEFNE (Bitfield-Mask: 0x01)                           */
#define CAN_IE_TFEE_Pos                   (11UL)                    /*!< TFEE (Bit 11)                                         */
#define CAN_IE_TFEE_Msk                   (0x800UL)                 /*!< TFEE (Bitfield-Mask: 0x01)                            */
#define CAN_IE_TCFE_Pos                   (10UL)                    /*!< TCFE (Bit 10)                                         */
#define CAN_IE_TCFE_Msk                   (0x400UL)                 /*!< TCFE (Bitfield-Mask: 0x01)                            */
#define CAN_IE_TCE_Pos                    (9UL)                     /*!< TCE (Bit 9)                                           */
#define CAN_IE_TCE_Msk                    (0x200UL)                 /*!< TCE (Bitfield-Mask: 0x01)                             */
#define CAN_IE_HPME_Pos                   (8UL)                     /*!< HPME (Bit 8)                                          */
#define CAN_IE_HPME_Msk                   (0x100UL)                 /*!< HPME (Bitfield-Mask: 0x01)                            */
#define CAN_IE_RF1LE_Pos                  (7UL)                     /*!< RF1LE (Bit 7)                                         */
#define CAN_IE_RF1LE_Msk                  (0x80UL)                  /*!< RF1LE (Bitfield-Mask: 0x01)                           */
#define CAN_IE_RF1FE_Pos                  (6UL)                     /*!< RF1FE (Bit 6)                                         */
#define CAN_IE_RF1FE_Msk                  (0x40UL)                  /*!< RF1FE (Bitfield-Mask: 0x01)                           */
#define CAN_IE_RF1WE_Pos                  (5UL)                     /*!< RF1WE (Bit 5)                                         */
#define CAN_IE_RF1WE_Msk                  (0x20UL)                  /*!< RF1WE (Bitfield-Mask: 0x01)                           */
#define CAN_IE_RF1NE_Pos                  (4UL)                     /*!< RF1NE (Bit 4)                                         */
#define CAN_IE_RF1NE_Msk                  (0x10UL)                  /*!< RF1NE (Bitfield-Mask: 0x01)                           */
#define CAN_IE_RF0LE_Pos                  (3UL)                     /*!< RF0LE (Bit 3)                                         */
#define CAN_IE_RF0LE_Msk                  (0x8UL)                   /*!< RF0LE (Bitfield-Mask: 0x01)                           */
#define CAN_IE_RF0FE_Pos                  (2UL)                     /*!< RF0FE (Bit 2)                                         */
#define CAN_IE_RF0FE_Msk                  (0x4UL)                   /*!< RF0FE (Bitfield-Mask: 0x01)                           */
#define CAN_IE_RF0WE_Pos                  (1UL)                     /*!< RF0WE (Bit 1)                                         */
#define CAN_IE_RF0WE_Msk                  (0x2UL)                   /*!< RF0WE (Bitfield-Mask: 0x01)                           */
#define CAN_IE_RF0NE_Pos                  (0UL)                     /*!< RF0NE (Bit 0)                                         */
#define CAN_IE_RF0NE_Msk                  (0x1UL)                   /*!< RF0NE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  ILS  ========================================================== */
#define CAN_ILS_ARAL_Pos                  (29UL)                    /*!< ARAL (Bit 29)                                         */
#define CAN_ILS_ARAL_Msk                  (0x20000000UL)            /*!< ARAL (Bitfield-Mask: 0x01)                            */
#define CAN_ILS_PEDL_Pos                  (28UL)                    /*!< PEDL (Bit 28)                                         */
#define CAN_ILS_PEDL_Msk                  (0x10000000UL)            /*!< PEDL (Bitfield-Mask: 0x01)                            */
#define CAN_ILS_PEAL_Pos                  (27UL)                    /*!< PEAL (Bit 27)                                         */
#define CAN_ILS_PEAL_Msk                  (0x8000000UL)             /*!< PEAL (Bitfield-Mask: 0x01)                            */
#define CAN_ILS_WDIL_Pos                  (26UL)                    /*!< WDIL (Bit 26)                                         */
#define CAN_ILS_WDIL_Msk                  (0x4000000UL)             /*!< WDIL (Bitfield-Mask: 0x01)                            */
#define CAN_ILS_BOL_Pos                   (25UL)                    /*!< BOL (Bit 25)                                          */
#define CAN_ILS_BOL_Msk                   (0x2000000UL)             /*!< BOL (Bitfield-Mask: 0x01)                             */
#define CAN_ILS_EWL_Pos                   (24UL)                    /*!< EWL (Bit 24)                                          */
#define CAN_ILS_EWL_Msk                   (0x1000000UL)             /*!< EWL (Bitfield-Mask: 0x01)                             */
#define CAN_ILS_EPL_Pos                   (23UL)                    /*!< EPL (Bit 23)                                          */
#define CAN_ILS_EPL_Msk                   (0x800000UL)              /*!< EPL (Bitfield-Mask: 0x01)                             */
#define CAN_ILS_ELOL_Pos                  (22UL)                    /*!< ELOL (Bit 22)                                         */
#define CAN_ILS_ELOL_Msk                  (0x400000UL)              /*!< ELOL (Bitfield-Mask: 0x01)                            */
#define CAN_ILS_BEUL_Pos                  (21UL)                    /*!< BEUL (Bit 21)                                         */
#define CAN_ILS_BEUL_Msk                  (0x200000UL)              /*!< BEUL (Bitfield-Mask: 0x01)                            */
#define CAN_ILS_BECL_Pos                  (20UL)                    /*!< BECL (Bit 20)                                         */
#define CAN_ILS_BECL_Msk                  (0x100000UL)              /*!< BECL (Bitfield-Mask: 0x01)                            */
#define CAN_ILS_DRXL_Pos                  (19UL)                    /*!< DRXL (Bit 19)                                         */
#define CAN_ILS_DRXL_Msk                  (0x80000UL)               /*!< DRXL (Bitfield-Mask: 0x01)                            */
#define CAN_ILS_TOOL_Pos                  (18UL)                    /*!< TOOL (Bit 18)                                         */
#define CAN_ILS_TOOL_Msk                  (0x40000UL)               /*!< TOOL (Bitfield-Mask: 0x01)                            */
#define CAN_ILS_MRAFL_Pos                 (17UL)                    /*!< MRAFL (Bit 17)                                        */
#define CAN_ILS_MRAFL_Msk                 (0x20000UL)               /*!< MRAFL (Bitfield-Mask: 0x01)                           */
#define CAN_ILS_TSWL_Pos                  (16UL)                    /*!< TSWL (Bit 16)                                         */
#define CAN_ILS_TSWL_Msk                  (0x10000UL)               /*!< TSWL (Bitfield-Mask: 0x01)                            */
#define CAN_ILS_TEFLL_Pos                 (15UL)                    /*!< TEFLL (Bit 15)                                        */
#define CAN_ILS_TEFLL_Msk                 (0x8000UL)                /*!< TEFLL (Bitfield-Mask: 0x01)                           */
#define CAN_ILS_TEFFL_Pos                 (14UL)                    /*!< TEFFL (Bit 14)                                        */
#define CAN_ILS_TEFFL_Msk                 (0x4000UL)                /*!< TEFFL (Bitfield-Mask: 0x01)                           */
#define CAN_ILS_TEFWL_Pos                 (13UL)                    /*!< TEFWL (Bit 13)                                        */
#define CAN_ILS_TEFWL_Msk                 (0x2000UL)                /*!< TEFWL (Bitfield-Mask: 0x01)                           */
#define CAN_ILS_TEFNL_Pos                 (12UL)                    /*!< TEFNL (Bit 12)                                        */
#define CAN_ILS_TEFNL_Msk                 (0x1000UL)                /*!< TEFNL (Bitfield-Mask: 0x01)                           */
#define CAN_ILS_TFEL_Pos                  (11UL)                    /*!< TFEL (Bit 11)                                         */
#define CAN_ILS_TFEL_Msk                  (0x800UL)                 /*!< TFEL (Bitfield-Mask: 0x01)                            */
#define CAN_ILS_TCFL_Pos                  (10UL)                    /*!< TCFL (Bit 10)                                         */
#define CAN_ILS_TCFL_Msk                  (0x400UL)                 /*!< TCFL (Bitfield-Mask: 0x01)                            */
#define CAN_ILS_TCL_Pos                   (9UL)                     /*!< TCL (Bit 9)                                           */
#define CAN_ILS_TCL_Msk                   (0x200UL)                 /*!< TCL (Bitfield-Mask: 0x01)                             */
#define CAN_ILS_HPML_Pos                  (8UL)                     /*!< HPML (Bit 8)                                          */
#define CAN_ILS_HPML_Msk                  (0x100UL)                 /*!< HPML (Bitfield-Mask: 0x01)                            */
#define CAN_ILS_RF1LL_Pos                 (7UL)                     /*!< RF1LL (Bit 7)                                         */
#define CAN_ILS_RF1LL_Msk                 (0x80UL)                  /*!< RF1LL (Bitfield-Mask: 0x01)                           */
#define CAN_ILS_RF1FL_Pos                 (6UL)                     /*!< RF1FL (Bit 6)                                         */
#define CAN_ILS_RF1FL_Msk                 (0x40UL)                  /*!< RF1FL (Bitfield-Mask: 0x01)                           */
#define CAN_ILS_RF1WL_Pos                 (5UL)                     /*!< RF1WL (Bit 5)                                         */
#define CAN_ILS_RF1WL_Msk                 (0x20UL)                  /*!< RF1WL (Bitfield-Mask: 0x01)                           */
#define CAN_ILS_RF1NL_Pos                 (4UL)                     /*!< RF1NL (Bit 4)                                         */
#define CAN_ILS_RF1NL_Msk                 (0x10UL)                  /*!< RF1NL (Bitfield-Mask: 0x01)                           */
#define CAN_ILS_RF0LL_Pos                 (3UL)                     /*!< RF0LL (Bit 3)                                         */
#define CAN_ILS_RF0LL_Msk                 (0x8UL)                   /*!< RF0LL (Bitfield-Mask: 0x01)                           */
#define CAN_ILS_RF0FL_Pos                 (2UL)                     /*!< RF0FL (Bit 2)                                         */
#define CAN_ILS_RF0FL_Msk                 (0x4UL)                   /*!< RF0FL (Bitfield-Mask: 0x01)                           */
#define CAN_ILS_RF0WL_Pos                 (1UL)                     /*!< RF0WL (Bit 1)                                         */
#define CAN_ILS_RF0WL_Msk                 (0x2UL)                   /*!< RF0WL (Bitfield-Mask: 0x01)                           */
#define CAN_ILS_RF0NL_Pos                 (0UL)                     /*!< RF0NL (Bit 0)                                         */
#define CAN_ILS_RF0NL_Msk                 (0x1UL)                   /*!< RF0NL (Bitfield-Mask: 0x01)                           */
/* ==========================================================  ILE  ========================================================== */
#define CAN_ILE_EINT1_Pos                 (1UL)                     /*!< EINT1 (Bit 1)                                         */
#define CAN_ILE_EINT1_Msk                 (0x2UL)                   /*!< EINT1 (Bitfield-Mask: 0x01)                           */
#define CAN_ILE_EINTO_Pos                 (0UL)                     /*!< EINTO (Bit 0)                                         */
#define CAN_ILE_EINTO_Msk                 (0x1UL)                   /*!< EINTO (Bitfield-Mask: 0x01)                           */
/* ==========================================================  GFC  ========================================================== */
#define CAN_GFC_ANFS_Pos                  (4UL)                     /*!< ANFS (Bit 4)                                          */
#define CAN_GFC_ANFS_Msk                  (0x30UL)                  /*!< ANFS (Bitfield-Mask: 0x03)                            */
#define CAN_GFC_ANFE_Pos                  (2UL)                     /*!< ANFE (Bit 2)                                          */
#define CAN_GFC_ANFE_Msk                  (0xcUL)                   /*!< ANFE (Bitfield-Mask: 0x03)                            */
#define CAN_GFC_RRFS_Pos                  (1UL)                     /*!< RRFS (Bit 1)                                          */
#define CAN_GFC_RRFS_Msk                  (0x2UL)                   /*!< RRFS (Bitfield-Mask: 0x01)                            */
#define CAN_GFC_RRFE_Pos                  (0UL)                     /*!< RRFE (Bit 0)                                          */
#define CAN_GFC_RRFE_Msk                  (0x1UL)                   /*!< RRFE (Bitfield-Mask: 0x01)                            */
/* =========================================================  SIDFC  ========================================================= */
#define CAN_SIDFC_LSS_Pos                 (16UL)                    /*!< LSS (Bit 16)                                          */
#define CAN_SIDFC_LSS_Msk                 (0xff0000UL)              /*!< LSS (Bitfield-Mask: 0xff)                             */
#define CAN_SIDFC_FLSSA_Pos               (2UL)                     /*!< FLSSA (Bit 2)                                         */
#define CAN_SIDFC_FLSSA_Msk               (0xfffcUL)                /*!< FLSSA (Bitfield-Mask: 0x3fff)                         */
/* =========================================================  XIDFC  ========================================================= */
#define CAN_XIDFC_LSE_Pos                 (16UL)                    /*!< LSE (Bit 16)                                          */
#define CAN_XIDFC_LSE_Msk                 (0x7f0000UL)              /*!< LSE (Bitfield-Mask: 0x7f)                             */
#define CAN_XIDFC_FLESA_Pos               (2UL)                     /*!< FLESA (Bit 2)                                         */
#define CAN_XIDFC_FLESA_Msk               (0xfffcUL)                /*!< FLESA (Bitfield-Mask: 0x3fff)                         */
/* =========================================================  XIDAM  ========================================================= */
#define CAN_XIDAM_EIDM_Pos                (0UL)                     /*!< EIDM (Bit 0)                                          */
#define CAN_XIDAM_EIDM_Msk                (0x1fffffffUL)            /*!< EIDM (Bitfield-Mask: 0x1fffffff)                      */
/* =========================================================  HPMS  ========================================================== */
#define CAN_HPMS_FLST_Pos                 (15UL)                    /*!< FLST (Bit 15)                                         */
#define CAN_HPMS_FLST_Msk                 (0x8000UL)                /*!< FLST (Bitfield-Mask: 0x01)                            */
#define CAN_HPMS_FIDX_Pos                 (8UL)                     /*!< FIDX (Bit 8)                                          */
#define CAN_HPMS_FIDX_Msk                 (0x7f00UL)                /*!< FIDX (Bitfield-Mask: 0x7f)                            */
#define CAN_HPMS_MSI_Pos                  (6UL)                     /*!< MSI (Bit 6)                                           */
#define CAN_HPMS_MSI_Msk                  (0xc0UL)                  /*!< MSI (Bitfield-Mask: 0x03)                             */
#define CAN_HPMS_BIDX_Pos                 (0UL)                     /*!< BIDX (Bit 0)                                          */
#define CAN_HPMS_BIDX_Msk                 (0x3fUL)                  /*!< BIDX (Bitfield-Mask: 0x3f)                            */
/* =========================================================  NDAT1  ========================================================= */
#define CAN_NDAT1_ND31_Pos                (31UL)                    /*!< ND31 (Bit 31)                                         */
#define CAN_NDAT1_ND31_Msk                (0x80000000UL)            /*!< ND31 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND30_Pos                (30UL)                    /*!< ND30 (Bit 30)                                         */
#define CAN_NDAT1_ND30_Msk                (0x40000000UL)            /*!< ND30 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND29_Pos                (29UL)                    /*!< ND29 (Bit 29)                                         */
#define CAN_NDAT1_ND29_Msk                (0x20000000UL)            /*!< ND29 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND28_Pos                (28UL)                    /*!< ND28 (Bit 28)                                         */
#define CAN_NDAT1_ND28_Msk                (0x10000000UL)            /*!< ND28 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND27_Pos                (27UL)                    /*!< ND27 (Bit 27)                                         */
#define CAN_NDAT1_ND27_Msk                (0x8000000UL)             /*!< ND27 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND26_Pos                (26UL)                    /*!< ND26 (Bit 26)                                         */
#define CAN_NDAT1_ND26_Msk                (0x4000000UL)             /*!< ND26 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND25_Pos                (25UL)                    /*!< ND25 (Bit 25)                                         */
#define CAN_NDAT1_ND25_Msk                (0x2000000UL)             /*!< ND25 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND24_Pos                (24UL)                    /*!< ND24 (Bit 24)                                         */
#define CAN_NDAT1_ND24_Msk                (0x1000000UL)             /*!< ND24 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND23_Pos                (23UL)                    /*!< ND23 (Bit 23)                                         */
#define CAN_NDAT1_ND23_Msk                (0x800000UL)              /*!< ND23 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND22_Pos                (22UL)                    /*!< ND22 (Bit 22)                                         */
#define CAN_NDAT1_ND22_Msk                (0x400000UL)              /*!< ND22 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND21_Pos                (21UL)                    /*!< ND21 (Bit 21)                                         */
#define CAN_NDAT1_ND21_Msk                (0x200000UL)              /*!< ND21 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND20_Pos                (20UL)                    /*!< ND20 (Bit 20)                                         */
#define CAN_NDAT1_ND20_Msk                (0x100000UL)              /*!< ND20 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND19_Pos                (19UL)                    /*!< ND19 (Bit 19)                                         */
#define CAN_NDAT1_ND19_Msk                (0x80000UL)               /*!< ND19 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND18_Pos                (18UL)                    /*!< ND18 (Bit 18)                                         */
#define CAN_NDAT1_ND18_Msk                (0x40000UL)               /*!< ND18 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND17_Pos                (17UL)                    /*!< ND17 (Bit 17)                                         */
#define CAN_NDAT1_ND17_Msk                (0x20000UL)               /*!< ND17 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND16_Pos                (16UL)                    /*!< ND16 (Bit 16)                                         */
#define CAN_NDAT1_ND16_Msk                (0x10000UL)               /*!< ND16 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND15_Pos                (15UL)                    /*!< ND15 (Bit 15)                                         */
#define CAN_NDAT1_ND15_Msk                (0x8000UL)                /*!< ND15 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND14_Pos                (14UL)                    /*!< ND14 (Bit 14)                                         */
#define CAN_NDAT1_ND14_Msk                (0x4000UL)                /*!< ND14 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND13_Pos                (13UL)                    /*!< ND13 (Bit 13)                                         */
#define CAN_NDAT1_ND13_Msk                (0x2000UL)                /*!< ND13 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND12_Pos                (12UL)                    /*!< ND12 (Bit 12)                                         */
#define CAN_NDAT1_ND12_Msk                (0x1000UL)                /*!< ND12 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND11_Pos                (11UL)                    /*!< ND11 (Bit 11)                                         */
#define CAN_NDAT1_ND11_Msk                (0x800UL)                 /*!< ND11 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND10_Pos                (10UL)                    /*!< ND10 (Bit 10)                                         */
#define CAN_NDAT1_ND10_Msk                (0x400UL)                 /*!< ND10 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT1_ND9_Pos                 (9UL)                     /*!< ND9 (Bit 9)                                           */
#define CAN_NDAT1_ND9_Msk                 (0x200UL)                 /*!< ND9 (Bitfield-Mask: 0x01)                             */
#define CAN_NDAT1_ND8_Pos                 (8UL)                     /*!< ND8 (Bit 8)                                           */
#define CAN_NDAT1_ND8_Msk                 (0x100UL)                 /*!< ND8 (Bitfield-Mask: 0x01)                             */
#define CAN_NDAT1_ND7_Pos                 (7UL)                     /*!< ND7 (Bit 7)                                           */
#define CAN_NDAT1_ND7_Msk                 (0x80UL)                  /*!< ND7 (Bitfield-Mask: 0x01)                             */
#define CAN_NDAT1_ND6_Pos                 (6UL)                     /*!< ND6 (Bit 6)                                           */
#define CAN_NDAT1_ND6_Msk                 (0x40UL)                  /*!< ND6 (Bitfield-Mask: 0x01)                             */
#define CAN_NDAT1_ND5_Pos                 (5UL)                     /*!< ND5 (Bit 5)                                           */
#define CAN_NDAT1_ND5_Msk                 (0x20UL)                  /*!< ND5 (Bitfield-Mask: 0x01)                             */
#define CAN_NDAT1_ND4_Pos                 (4UL)                     /*!< ND4 (Bit 4)                                           */
#define CAN_NDAT1_ND4_Msk                 (0x10UL)                  /*!< ND4 (Bitfield-Mask: 0x01)                             */
#define CAN_NDAT1_ND3_Pos                 (3UL)                     /*!< ND3 (Bit 3)                                           */
#define CAN_NDAT1_ND3_Msk                 (0x8UL)                   /*!< ND3 (Bitfield-Mask: 0x01)                             */
#define CAN_NDAT1_ND2_Pos                 (2UL)                     /*!< ND2 (Bit 2)                                           */
#define CAN_NDAT1_ND2_Msk                 (0x4UL)                   /*!< ND2 (Bitfield-Mask: 0x01)                             */
#define CAN_NDAT1_ND1_Pos                 (1UL)                     /*!< ND1 (Bit 1)                                           */
#define CAN_NDAT1_ND1_Msk                 (0x2UL)                   /*!< ND1 (Bitfield-Mask: 0x01)                             */
#define CAN_NDAT1_ND0_Pos                 (0UL)                     /*!< ND0 (Bit 0)                                           */
#define CAN_NDAT1_ND0_Msk                 (0x1UL)                   /*!< ND0 (Bitfield-Mask: 0x01)                             */
/* =========================================================  NDAT2  ========================================================= */
#define CAN_NDAT2_ND63_Pos                (31UL)                    /*!< ND63 (Bit 31)                                         */
#define CAN_NDAT2_ND63_Msk                (0x80000000UL)            /*!< ND63 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND62_Pos                (30UL)                    /*!< ND62 (Bit 30)                                         */
#define CAN_NDAT2_ND62_Msk                (0x40000000UL)            /*!< ND62 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND61_Pos                (29UL)                    /*!< ND61 (Bit 29)                                         */
#define CAN_NDAT2_ND61_Msk                (0x20000000UL)            /*!< ND61 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND60_Pos                (28UL)                    /*!< ND60 (Bit 28)                                         */
#define CAN_NDAT2_ND60_Msk                (0x10000000UL)            /*!< ND60 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND59_Pos                (27UL)                    /*!< ND59 (Bit 27)                                         */
#define CAN_NDAT2_ND59_Msk                (0x8000000UL)             /*!< ND59 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND58_Pos                (26UL)                    /*!< ND58 (Bit 26)                                         */
#define CAN_NDAT2_ND58_Msk                (0x4000000UL)             /*!< ND58 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND57_Pos                (25UL)                    /*!< ND57 (Bit 25)                                         */
#define CAN_NDAT2_ND57_Msk                (0x2000000UL)             /*!< ND57 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND56_Pos                (24UL)                    /*!< ND56 (Bit 24)                                         */
#define CAN_NDAT2_ND56_Msk                (0x1000000UL)             /*!< ND56 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND55_Pos                (23UL)                    /*!< ND55 (Bit 23)                                         */
#define CAN_NDAT2_ND55_Msk                (0x800000UL)              /*!< ND55 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND54_Pos                (22UL)                    /*!< ND54 (Bit 22)                                         */
#define CAN_NDAT2_ND54_Msk                (0x400000UL)              /*!< ND54 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND53_Pos                (21UL)                    /*!< ND53 (Bit 21)                                         */
#define CAN_NDAT2_ND53_Msk                (0x200000UL)              /*!< ND53 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND52_Pos                (20UL)                    /*!< ND52 (Bit 20)                                         */
#define CAN_NDAT2_ND52_Msk                (0x100000UL)              /*!< ND52 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND51_Pos                (19UL)                    /*!< ND51 (Bit 19)                                         */
#define CAN_NDAT2_ND51_Msk                (0x80000UL)               /*!< ND51 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND50_Pos                (18UL)                    /*!< ND50 (Bit 18)                                         */
#define CAN_NDAT2_ND50_Msk                (0x40000UL)               /*!< ND50 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND49_Pos                (17UL)                    /*!< ND49 (Bit 17)                                         */
#define CAN_NDAT2_ND49_Msk                (0x20000UL)               /*!< ND49 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND48_Pos                (16UL)                    /*!< ND48 (Bit 16)                                         */
#define CAN_NDAT2_ND48_Msk                (0x10000UL)               /*!< ND48 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND47_Pos                (15UL)                    /*!< ND47 (Bit 15)                                         */
#define CAN_NDAT2_ND47_Msk                (0x8000UL)                /*!< ND47 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND46_Pos                (14UL)                    /*!< ND46 (Bit 14)                                         */
#define CAN_NDAT2_ND46_Msk                (0x4000UL)                /*!< ND46 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND45_Pos                (13UL)                    /*!< ND45 (Bit 13)                                         */
#define CAN_NDAT2_ND45_Msk                (0x2000UL)                /*!< ND45 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND44_Pos                (12UL)                    /*!< ND44 (Bit 12)                                         */
#define CAN_NDAT2_ND44_Msk                (0x1000UL)                /*!< ND44 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND43_Pos                (11UL)                    /*!< ND43 (Bit 11)                                         */
#define CAN_NDAT2_ND43_Msk                (0x800UL)                 /*!< ND43 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND42_Pos                (10UL)                    /*!< ND42 (Bit 10)                                         */
#define CAN_NDAT2_ND42_Msk                (0x400UL)                 /*!< ND42 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND41_Pos                (9UL)                     /*!< ND41 (Bit 9)                                          */
#define CAN_NDAT2_ND41_Msk                (0x200UL)                 /*!< ND41 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND40_Pos                (8UL)                     /*!< ND40 (Bit 8)                                          */
#define CAN_NDAT2_ND40_Msk                (0x100UL)                 /*!< ND40 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND39_Pos                (7UL)                     /*!< ND39 (Bit 7)                                          */
#define CAN_NDAT2_ND39_Msk                (0x80UL)                  /*!< ND39 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND38_Pos                (6UL)                     /*!< ND38 (Bit 6)                                          */
#define CAN_NDAT2_ND38_Msk                (0x40UL)                  /*!< ND38 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND37_Pos                (5UL)                     /*!< ND37 (Bit 5)                                          */
#define CAN_NDAT2_ND37_Msk                (0x20UL)                  /*!< ND37 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND36_Pos                (4UL)                     /*!< ND36 (Bit 4)                                          */
#define CAN_NDAT2_ND36_Msk                (0x10UL)                  /*!< ND36 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND35_Pos                (3UL)                     /*!< ND35 (Bit 3)                                          */
#define CAN_NDAT2_ND35_Msk                (0x8UL)                   /*!< ND35 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND34_Pos                (2UL)                     /*!< ND34 (Bit 2)                                          */
#define CAN_NDAT2_ND34_Msk                (0x4UL)                   /*!< ND34 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND33_Pos                (1UL)                     /*!< ND33 (Bit 1)                                          */
#define CAN_NDAT2_ND33_Msk                (0x2UL)                   /*!< ND33 (Bitfield-Mask: 0x01)                            */
#define CAN_NDAT2_ND32_Pos                (0UL)                     /*!< ND32 (Bit 0)                                          */
#define CAN_NDAT2_ND32_Msk                (0x1UL)                   /*!< ND32 (Bitfield-Mask: 0x01)                            */
/* =========================================================  RXF0C  ========================================================= */
#define CAN_RXF0C_F0OM_Pos                (31UL)                    /*!< F0OM (Bit 31)                                         */
#define CAN_RXF0C_F0OM_Msk                (0x80000000UL)            /*!< F0OM (Bitfield-Mask: 0x01)                            */
#define CAN_RXF0C_F0WM_Pos                (24UL)                    /*!< F0WM (Bit 24)                                         */
#define CAN_RXF0C_F0WM_Msk                (0x7f000000UL)            /*!< F0WM (Bitfield-Mask: 0x7f)                            */
#define CAN_RXF0C_F0S_Pos                 (16UL)                    /*!< F0S (Bit 16)                                          */
#define CAN_RXF0C_F0S_Msk                 (0x7f0000UL)              /*!< F0S (Bitfield-Mask: 0x7f)                             */
#define CAN_RXF0C_F0SA_Pos                (2UL)                     /*!< F0SA (Bit 2)                                          */
#define CAN_RXF0C_F0SA_Msk                (0xfffcUL)                /*!< F0SA (Bitfield-Mask: 0x3fff)                          */
/* =========================================================  RXF0S  ========================================================= */
#define CAN_RXF0S_RF0L_Pos                (25UL)                    /*!< RF0L (Bit 25)                                         */
#define CAN_RXF0S_RF0L_Msk                (0x2000000UL)             /*!< RF0L (Bitfield-Mask: 0x01)                            */
#define CAN_RXF0S_F0F_Pos                 (24UL)                    /*!< F0F (Bit 24)                                          */
#define CAN_RXF0S_F0F_Msk                 (0x1000000UL)             /*!< F0F (Bitfield-Mask: 0x01)                             */
#define CAN_RXF0S_F0PI_Pos                (16UL)                    /*!< F0PI (Bit 16)                                         */
#define CAN_RXF0S_F0PI_Msk                (0x3f0000UL)              /*!< F0PI (Bitfield-Mask: 0x3f)                            */
#define CAN_RXF0S_F0GI_Pos                (8UL)                     /*!< F0GI (Bit 8)                                          */
#define CAN_RXF0S_F0GI_Msk                (0x3f00UL)                /*!< F0GI (Bitfield-Mask: 0x3f)                            */
#define CAN_RXF0S_F0FL_Pos                (0UL)                     /*!< F0FL (Bit 0)                                          */
#define CAN_RXF0S_F0FL_Msk                (0x7fUL)                  /*!< F0FL (Bitfield-Mask: 0x7f)                            */
/* =========================================================  RXF0A  ========================================================= */
#define CAN_RXF0A_F0AI_Pos                (0UL)                     /*!< F0AI (Bit 0)                                          */
#define CAN_RXF0A_F0AI_Msk                (0x3fUL)                  /*!< F0AI (Bitfield-Mask: 0x3f)                            */
/* =========================================================  RXBC  ========================================================== */
#define CAN_RXBC_RBSA_Pos                 (2UL)                     /*!< RBSA (Bit 2)                                          */
#define CAN_RXBC_RBSA_Msk                 (0xfffcUL)                /*!< RBSA (Bitfield-Mask: 0x3fff)                          */
/* =========================================================  RXF1C  ========================================================= */
#define CAN_RXF1C_F1OM_Pos                (31UL)                    /*!< F1OM (Bit 31)                                         */
#define CAN_RXF1C_F1OM_Msk                (0x80000000UL)            /*!< F1OM (Bitfield-Mask: 0x01)                            */
#define CAN_RXF1C_F1WM_Pos                (24UL)                    /*!< F1WM (Bit 24)                                         */
#define CAN_RXF1C_F1WM_Msk                (0x7f000000UL)            /*!< F1WM (Bitfield-Mask: 0x7f)                            */
#define CAN_RXF1C_F1S_Pos                 (16UL)                    /*!< F1S (Bit 16)                                          */
#define CAN_RXF1C_F1S_Msk                 (0x7f0000UL)              /*!< F1S (Bitfield-Mask: 0x7f)                             */
#define CAN_RXF1C_F1SA_Pos                (2UL)                     /*!< F1SA (Bit 2)                                          */
#define CAN_RXF1C_F1SA_Msk                (0xfffcUL)                /*!< F1SA (Bitfield-Mask: 0x3fff)                          */
/* =========================================================  RXF1S  ========================================================= */
#define CAN_RXF1S_DMS_Pos                 (30UL)                    /*!< DMS (Bit 30)                                          */
#define CAN_RXF1S_DMS_Msk                 (0xc0000000UL)            /*!< DMS (Bitfield-Mask: 0x03)                             */
#define CAN_RXF1S_RF1L_Pos                (25UL)                    /*!< RF1L (Bit 25)                                         */
#define CAN_RXF1S_RF1L_Msk                (0x2000000UL)             /*!< RF1L (Bitfield-Mask: 0x01)                            */
#define CAN_RXF1S_F1F_Pos                 (24UL)                    /*!< F1F (Bit 24)                                          */
#define CAN_RXF1S_F1F_Msk                 (0x1000000UL)             /*!< F1F (Bitfield-Mask: 0x01)                             */
#define CAN_RXF1S_F1PI_Pos                (16UL)                    /*!< F1PI (Bit 16)                                         */
#define CAN_RXF1S_F1PI_Msk                (0x3f0000UL)              /*!< F1PI (Bitfield-Mask: 0x3f)                            */
#define CAN_RXF1S_F1GI_Pos                (8UL)                     /*!< F1GI (Bit 8)                                          */
#define CAN_RXF1S_F1GI_Msk                (0x3f00UL)                /*!< F1GI (Bitfield-Mask: 0x3f)                            */
#define CAN_RXF1S_F1FL_Pos                (0UL)                     /*!< F1FL (Bit 0)                                          */
#define CAN_RXF1S_F1FL_Msk                (0x7fUL)                  /*!< F1FL (Bitfield-Mask: 0x7f)                            */
/* =========================================================  RXF1A  ========================================================= */
#define CAN_RXF1A_F1Al_Pos                (0UL)                     /*!< F1Al (Bit 0)                                          */
#define CAN_RXF1A_F1Al_Msk                (0x3fUL)                  /*!< F1Al (Bitfield-Mask: 0x3f)                            */
/* =========================================================  RXESC  ========================================================= */
#define CAN_RXESC_RBDS_Pos                (8UL)                     /*!< RBDS (Bit 8)                                          */
#define CAN_RXESC_RBDS_Msk                (0x700UL)                 /*!< RBDS (Bitfield-Mask: 0x07)                            */
#define CAN_RXESC_F1DS_Pos                (4UL)                     /*!< F1DS (Bit 4)                                          */
#define CAN_RXESC_F1DS_Msk                (0x70UL)                  /*!< F1DS (Bitfield-Mask: 0x07)                            */
#define CAN_RXESC_F0DS_Pos                (0UL)                     /*!< F0DS (Bit 0)                                          */
#define CAN_RXESC_F0DS_Msk                (0x7UL)                   /*!< F0DS (Bitfield-Mask: 0x07)                            */
/* =========================================================  TXBC  ========================================================== */
#define CAN_TXBC_TFQM_Pos                 (30UL)                    /*!< TFQM (Bit 30)                                         */
#define CAN_TXBC_TFQM_Msk                 (0x40000000UL)            /*!< TFQM (Bitfield-Mask: 0x01)                            */
#define CAN_TXBC_TFQS_Pos                 (24UL)                    /*!< TFQS (Bit 24)                                         */
#define CAN_TXBC_TFQS_Msk                 (0x3f000000UL)            /*!< TFQS (Bitfield-Mask: 0x3f)                            */
#define CAN_TXBC_NDTB_Pos                 (16UL)                    /*!< NDTB (Bit 16)                                         */
#define CAN_TXBC_NDTB_Msk                 (0x3f0000UL)              /*!< NDTB (Bitfield-Mask: 0x3f)                            */
#define CAN_TXBC_TBSA_Pos                 (2UL)                     /*!< TBSA (Bit 2)                                          */
#define CAN_TXBC_TBSA_Msk                 (0xfffcUL)                /*!< TBSA (Bitfield-Mask: 0x3fff)                          */
/* =========================================================  TXFQS  ========================================================= */
#define CAN_TXFQS_TFQF_Pos                (21UL)                    /*!< TFQF (Bit 21)                                         */
#define CAN_TXFQS_TFQF_Msk                (0x200000UL)              /*!< TFQF (Bitfield-Mask: 0x01)                            */
#define CAN_TXFQS_TFQPI_Pos               (16UL)                    /*!< TFQPI (Bit 16)                                        */
#define CAN_TXFQS_TFQPI_Msk               (0x1f0000UL)              /*!< TFQPI (Bitfield-Mask: 0x1f)                           */
#define CAN_TXFQS_TFGI_Pos                (8UL)                     /*!< TFGI (Bit 8)                                          */
#define CAN_TXFQS_TFGI_Msk                (0x1f00UL)                /*!< TFGI (Bitfield-Mask: 0x1f)                            */
#define CAN_TXFQS_TFFL_Pos                (0UL)                     /*!< TFFL (Bit 0)                                          */
#define CAN_TXFQS_TFFL_Msk                (0x3fUL)                  /*!< TFFL (Bitfield-Mask: 0x3f)                            */
/* =========================================================  TXESC  ========================================================= */
#define CAN_TXESC_TBDS_Pos                (0UL)                     /*!< TBDS (Bit 0)                                          */
#define CAN_TXESC_TBDS_Msk                (0x7UL)                   /*!< TBDS (Bitfield-Mask: 0x07)                            */
/* =========================================================  TXBRP  ========================================================= */
#define CAN_TXBRP_TRP31_Pos               (31UL)                    /*!< TRP31 (Bit 31)                                        */
#define CAN_TXBRP_TRP31_Msk               (0x80000000UL)            /*!< TRP31 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP30_Pos               (30UL)                    /*!< TRP30 (Bit 30)                                        */
#define CAN_TXBRP_TRP30_Msk               (0x40000000UL)            /*!< TRP30 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP29_Pos               (29UL)                    /*!< TRP29 (Bit 29)                                        */
#define CAN_TXBRP_TRP29_Msk               (0x20000000UL)            /*!< TRP29 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP28_Pos               (28UL)                    /*!< TRP28 (Bit 28)                                        */
#define CAN_TXBRP_TRP28_Msk               (0x10000000UL)            /*!< TRP28 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP27_Pos               (27UL)                    /*!< TRP27 (Bit 27)                                        */
#define CAN_TXBRP_TRP27_Msk               (0x8000000UL)             /*!< TRP27 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP26_Pos               (26UL)                    /*!< TRP26 (Bit 26)                                        */
#define CAN_TXBRP_TRP26_Msk               (0x4000000UL)             /*!< TRP26 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP25_Pos               (25UL)                    /*!< TRP25 (Bit 25)                                        */
#define CAN_TXBRP_TRP25_Msk               (0x2000000UL)             /*!< TRP25 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP24_Pos               (24UL)                    /*!< TRP24 (Bit 24)                                        */
#define CAN_TXBRP_TRP24_Msk               (0x1000000UL)             /*!< TRP24 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP23_Pos               (23UL)                    /*!< TRP23 (Bit 23)                                        */
#define CAN_TXBRP_TRP23_Msk               (0x800000UL)              /*!< TRP23 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP22_Pos               (22UL)                    /*!< TRP22 (Bit 22)                                        */
#define CAN_TXBRP_TRP22_Msk               (0x400000UL)              /*!< TRP22 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP21_Pos               (21UL)                    /*!< TRP21 (Bit 21)                                        */
#define CAN_TXBRP_TRP21_Msk               (0x200000UL)              /*!< TRP21 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP20_Pos               (20UL)                    /*!< TRP20 (Bit 20)                                        */
#define CAN_TXBRP_TRP20_Msk               (0x100000UL)              /*!< TRP20 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP19_Pos               (19UL)                    /*!< TRP19 (Bit 19)                                        */
#define CAN_TXBRP_TRP19_Msk               (0x80000UL)               /*!< TRP19 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP18_Pos               (18UL)                    /*!< TRP18 (Bit 18)                                        */
#define CAN_TXBRP_TRP18_Msk               (0x40000UL)               /*!< TRP18 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP17_Pos               (17UL)                    /*!< TRP17 (Bit 17)                                        */
#define CAN_TXBRP_TRP17_Msk               (0x20000UL)               /*!< TRP17 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP16_Pos               (16UL)                    /*!< TRP16 (Bit 16)                                        */
#define CAN_TXBRP_TRP16_Msk               (0x10000UL)               /*!< TRP16 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP15_Pos               (15UL)                    /*!< TRP15 (Bit 15)                                        */
#define CAN_TXBRP_TRP15_Msk               (0x8000UL)                /*!< TRP15 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP14_Pos               (14UL)                    /*!< TRP14 (Bit 14)                                        */
#define CAN_TXBRP_TRP14_Msk               (0x4000UL)                /*!< TRP14 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP13_Pos               (13UL)                    /*!< TRP13 (Bit 13)                                        */
#define CAN_TXBRP_TRP13_Msk               (0x2000UL)                /*!< TRP13 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP12_Pos               (12UL)                    /*!< TRP12 (Bit 12)                                        */
#define CAN_TXBRP_TRP12_Msk               (0x1000UL)                /*!< TRP12 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP11_Pos               (11UL)                    /*!< TRP11 (Bit 11)                                        */
#define CAN_TXBRP_TRP11_Msk               (0x800UL)                 /*!< TRP11 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP10_Pos               (10UL)                    /*!< TRP10 (Bit 10)                                        */
#define CAN_TXBRP_TRP10_Msk               (0x400UL)                 /*!< TRP10 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBRP_TRP9_Pos                (9UL)                     /*!< TRP9 (Bit 9)                                          */
#define CAN_TXBRP_TRP9_Msk                (0x200UL)                 /*!< TRP9 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBRP_TRP8_Pos                (8UL)                     /*!< TRP8 (Bit 8)                                          */
#define CAN_TXBRP_TRP8_Msk                (0x100UL)                 /*!< TRP8 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBRP_TRP7_Pos                (7UL)                     /*!< TRP7 (Bit 7)                                          */
#define CAN_TXBRP_TRP7_Msk                (0x80UL)                  /*!< TRP7 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBRP_TRP6_Pos                (6UL)                     /*!< TRP6 (Bit 6)                                          */
#define CAN_TXBRP_TRP6_Msk                (0x40UL)                  /*!< TRP6 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBRP_TRP5_Pos                (5UL)                     /*!< TRP5 (Bit 5)                                          */
#define CAN_TXBRP_TRP5_Msk                (0x20UL)                  /*!< TRP5 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBRP_TRP4_Pos                (4UL)                     /*!< TRP4 (Bit 4)                                          */
#define CAN_TXBRP_TRP4_Msk                (0x10UL)                  /*!< TRP4 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBRP_TRP3_Pos                (3UL)                     /*!< TRP3 (Bit 3)                                          */
#define CAN_TXBRP_TRP3_Msk                (0x8UL)                   /*!< TRP3 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBRP_TRP2_Pos                (2UL)                     /*!< TRP2 (Bit 2)                                          */
#define CAN_TXBRP_TRP2_Msk                (0x4UL)                   /*!< TRP2 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBRP_TRP1_Pos                (1UL)                     /*!< TRP1 (Bit 1)                                          */
#define CAN_TXBRP_TRP1_Msk                (0x2UL)                   /*!< TRP1 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBRP_TRP0_Pos                (0UL)                     /*!< TRP0 (Bit 0)                                          */
#define CAN_TXBRP_TRP0_Msk                (0x1UL)                   /*!< TRP0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  TXBAR  ========================================================= */
#define CAN_TXBAR_AR31_Pos                (31UL)                    /*!< AR31 (Bit 31)                                         */
#define CAN_TXBAR_AR31_Msk                (0x80000000UL)            /*!< AR31 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR30_Pos                (30UL)                    /*!< AR30 (Bit 30)                                         */
#define CAN_TXBAR_AR30_Msk                (0x40000000UL)            /*!< AR30 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR29_Pos                (29UL)                    /*!< AR29 (Bit 29)                                         */
#define CAN_TXBAR_AR29_Msk                (0x20000000UL)            /*!< AR29 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR28_Pos                (28UL)                    /*!< AR28 (Bit 28)                                         */
#define CAN_TXBAR_AR28_Msk                (0x10000000UL)            /*!< AR28 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR27_Pos                (27UL)                    /*!< AR27 (Bit 27)                                         */
#define CAN_TXBAR_AR27_Msk                (0x8000000UL)             /*!< AR27 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR26_Pos                (26UL)                    /*!< AR26 (Bit 26)                                         */
#define CAN_TXBAR_AR26_Msk                (0x4000000UL)             /*!< AR26 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR25_Pos                (25UL)                    /*!< AR25 (Bit 25)                                         */
#define CAN_TXBAR_AR25_Msk                (0x2000000UL)             /*!< AR25 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR24_Pos                (24UL)                    /*!< AR24 (Bit 24)                                         */
#define CAN_TXBAR_AR24_Msk                (0x1000000UL)             /*!< AR24 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR23_Pos                (23UL)                    /*!< AR23 (Bit 23)                                         */
#define CAN_TXBAR_AR23_Msk                (0x800000UL)              /*!< AR23 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR22_Pos                (22UL)                    /*!< AR22 (Bit 22)                                         */
#define CAN_TXBAR_AR22_Msk                (0x400000UL)              /*!< AR22 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR21_Pos                (21UL)                    /*!< AR21 (Bit 21)                                         */
#define CAN_TXBAR_AR21_Msk                (0x200000UL)              /*!< AR21 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR20_Pos                (20UL)                    /*!< AR20 (Bit 20)                                         */
#define CAN_TXBAR_AR20_Msk                (0x100000UL)              /*!< AR20 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR19_Pos                (19UL)                    /*!< AR19 (Bit 19)                                         */
#define CAN_TXBAR_AR19_Msk                (0x80000UL)               /*!< AR19 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR18_Pos                (18UL)                    /*!< AR18 (Bit 18)                                         */
#define CAN_TXBAR_AR18_Msk                (0x40000UL)               /*!< AR18 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR17_Pos                (17UL)                    /*!< AR17 (Bit 17)                                         */
#define CAN_TXBAR_AR17_Msk                (0x20000UL)               /*!< AR17 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR16_Pos                (16UL)                    /*!< AR16 (Bit 16)                                         */
#define CAN_TXBAR_AR16_Msk                (0x10000UL)               /*!< AR16 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR15_Pos                (15UL)                    /*!< AR15 (Bit 15)                                         */
#define CAN_TXBAR_AR15_Msk                (0x8000UL)                /*!< AR15 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR14_Pos                (14UL)                    /*!< AR14 (Bit 14)                                         */
#define CAN_TXBAR_AR14_Msk                (0x4000UL)                /*!< AR14 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR13_Pos                (13UL)                    /*!< AR13 (Bit 13)                                         */
#define CAN_TXBAR_AR13_Msk                (0x2000UL)                /*!< AR13 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR12_Pos                (12UL)                    /*!< AR12 (Bit 12)                                         */
#define CAN_TXBAR_AR12_Msk                (0x1000UL)                /*!< AR12 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR11_Pos                (11UL)                    /*!< AR11 (Bit 11)                                         */
#define CAN_TXBAR_AR11_Msk                (0x800UL)                 /*!< AR11 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR10_Pos                (10UL)                    /*!< AR10 (Bit 10)                                         */
#define CAN_TXBAR_AR10_Msk                (0x400UL)                 /*!< AR10 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBAR_AR9_Pos                 (9UL)                     /*!< AR9 (Bit 9)                                           */
#define CAN_TXBAR_AR9_Msk                 (0x200UL)                 /*!< AR9 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBAR_AR8_Pos                 (8UL)                     /*!< AR8 (Bit 8)                                           */
#define CAN_TXBAR_AR8_Msk                 (0x100UL)                 /*!< AR8 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBAR_AR7_Pos                 (7UL)                     /*!< AR7 (Bit 7)                                           */
#define CAN_TXBAR_AR7_Msk                 (0x80UL)                  /*!< AR7 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBAR_AR6_Pos                 (6UL)                     /*!< AR6 (Bit 6)                                           */
#define CAN_TXBAR_AR6_Msk                 (0x40UL)                  /*!< AR6 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBAR_AR5_Pos                 (5UL)                     /*!< AR5 (Bit 5)                                           */
#define CAN_TXBAR_AR5_Msk                 (0x20UL)                  /*!< AR5 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBAR_AR4_Pos                 (4UL)                     /*!< AR4 (Bit 4)                                           */
#define CAN_TXBAR_AR4_Msk                 (0x10UL)                  /*!< AR4 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBAR_AR3_Pos                 (3UL)                     /*!< AR3 (Bit 3)                                           */
#define CAN_TXBAR_AR3_Msk                 (0x8UL)                   /*!< AR3 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBAR_AR2_Pos                 (2UL)                     /*!< AR2 (Bit 2)                                           */
#define CAN_TXBAR_AR2_Msk                 (0x4UL)                   /*!< AR2 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBAR_AR1_Pos                 (1UL)                     /*!< AR1 (Bit 1)                                           */
#define CAN_TXBAR_AR1_Msk                 (0x2UL)                   /*!< AR1 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBAR_AR0_Pos                 (0UL)                     /*!< AR0 (Bit 0)                                           */
#define CAN_TXBAR_AR0_Msk                 (0x1UL)                   /*!< AR0 (Bitfield-Mask: 0x01)                             */
/* =========================================================  TXBCR  ========================================================= */
#define CAN_TXBCR_CR31_Pos                (31UL)                    /*!< CR31 (Bit 31)                                         */
#define CAN_TXBCR_CR31_Msk                (0x80000000UL)            /*!< CR31 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR30_Pos                (30UL)                    /*!< CR30 (Bit 30)                                         */
#define CAN_TXBCR_CR30_Msk                (0x40000000UL)            /*!< CR30 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR29_Pos                (29UL)                    /*!< CR29 (Bit 29)                                         */
#define CAN_TXBCR_CR29_Msk                (0x20000000UL)            /*!< CR29 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR28_Pos                (28UL)                    /*!< CR28 (Bit 28)                                         */
#define CAN_TXBCR_CR28_Msk                (0x10000000UL)            /*!< CR28 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR27_Pos                (27UL)                    /*!< CR27 (Bit 27)                                         */
#define CAN_TXBCR_CR27_Msk                (0x8000000UL)             /*!< CR27 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR26_Pos                (26UL)                    /*!< CR26 (Bit 26)                                         */
#define CAN_TXBCR_CR26_Msk                (0x4000000UL)             /*!< CR26 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR25_Pos                (25UL)                    /*!< CR25 (Bit 25)                                         */
#define CAN_TXBCR_CR25_Msk                (0x2000000UL)             /*!< CR25 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR24_Pos                (24UL)                    /*!< CR24 (Bit 24)                                         */
#define CAN_TXBCR_CR24_Msk                (0x1000000UL)             /*!< CR24 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR23_Pos                (23UL)                    /*!< CR23 (Bit 23)                                         */
#define CAN_TXBCR_CR23_Msk                (0x800000UL)              /*!< CR23 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR22_Pos                (22UL)                    /*!< CR22 (Bit 22)                                         */
#define CAN_TXBCR_CR22_Msk                (0x400000UL)              /*!< CR22 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR21_Pos                (21UL)                    /*!< CR21 (Bit 21)                                         */
#define CAN_TXBCR_CR21_Msk                (0x200000UL)              /*!< CR21 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR20_Pos                (20UL)                    /*!< CR20 (Bit 20)                                         */
#define CAN_TXBCR_CR20_Msk                (0x100000UL)              /*!< CR20 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR19_Pos                (19UL)                    /*!< CR19 (Bit 19)                                         */
#define CAN_TXBCR_CR19_Msk                (0x80000UL)               /*!< CR19 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR18_Pos                (18UL)                    /*!< CR18 (Bit 18)                                         */
#define CAN_TXBCR_CR18_Msk                (0x40000UL)               /*!< CR18 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR17_Pos                (17UL)                    /*!< CR17 (Bit 17)                                         */
#define CAN_TXBCR_CR17_Msk                (0x20000UL)               /*!< CR17 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR16_Pos                (16UL)                    /*!< CR16 (Bit 16)                                         */
#define CAN_TXBCR_CR16_Msk                (0x10000UL)               /*!< CR16 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR15_Pos                (15UL)                    /*!< CR15 (Bit 15)                                         */
#define CAN_TXBCR_CR15_Msk                (0x8000UL)                /*!< CR15 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR14_Pos                (14UL)                    /*!< CR14 (Bit 14)                                         */
#define CAN_TXBCR_CR14_Msk                (0x4000UL)                /*!< CR14 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR13_Pos                (13UL)                    /*!< CR13 (Bit 13)                                         */
#define CAN_TXBCR_CR13_Msk                (0x2000UL)                /*!< CR13 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR12_Pos                (12UL)                    /*!< CR12 (Bit 12)                                         */
#define CAN_TXBCR_CR12_Msk                (0x1000UL)                /*!< CR12 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR11_Pos                (11UL)                    /*!< CR11 (Bit 11)                                         */
#define CAN_TXBCR_CR11_Msk                (0x800UL)                 /*!< CR11 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR10_Pos                (10UL)                    /*!< CR10 (Bit 10)                                         */
#define CAN_TXBCR_CR10_Msk                (0x400UL)                 /*!< CR10 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCR_CR9_Pos                 (9UL)                     /*!< CR9 (Bit 9)                                           */
#define CAN_TXBCR_CR9_Msk                 (0x200UL)                 /*!< CR9 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCR_CR8_Pos                 (8UL)                     /*!< CR8 (Bit 8)                                           */
#define CAN_TXBCR_CR8_Msk                 (0x100UL)                 /*!< CR8 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCR_CR7_Pos                 (7UL)                     /*!< CR7 (Bit 7)                                           */
#define CAN_TXBCR_CR7_Msk                 (0x80UL)                  /*!< CR7 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCR_CR6_Pos                 (6UL)                     /*!< CR6 (Bit 6)                                           */
#define CAN_TXBCR_CR6_Msk                 (0x40UL)                  /*!< CR6 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCR_CR5_Pos                 (5UL)                     /*!< CR5 (Bit 5)                                           */
#define CAN_TXBCR_CR5_Msk                 (0x20UL)                  /*!< CR5 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCR_CR4_Pos                 (4UL)                     /*!< CR4 (Bit 4)                                           */
#define CAN_TXBCR_CR4_Msk                 (0x10UL)                  /*!< CR4 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCR_CR3_Pos                 (3UL)                     /*!< CR3 (Bit 3)                                           */
#define CAN_TXBCR_CR3_Msk                 (0x8UL)                   /*!< CR3 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCR_CR2_Pos                 (2UL)                     /*!< CR2 (Bit 2)                                           */
#define CAN_TXBCR_CR2_Msk                 (0x4UL)                   /*!< CR2 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCR_CR1_Pos                 (1UL)                     /*!< CR1 (Bit 1)                                           */
#define CAN_TXBCR_CR1_Msk                 (0x2UL)                   /*!< CR1 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCR_CR0_Pos                 (0UL)                     /*!< CR0 (Bit 0)                                           */
#define CAN_TXBCR_CR0_Msk                 (0x1UL)                   /*!< CR0 (Bitfield-Mask: 0x01)                             */
/* =========================================================  TXBTO  ========================================================= */
#define CAN_TXBTO_TO31_Pos                (31UL)                    /*!< TO31 (Bit 31)                                         */
#define CAN_TXBTO_TO31_Msk                (0x80000000UL)            /*!< TO31 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO30_Pos                (30UL)                    /*!< TO30 (Bit 30)                                         */
#define CAN_TXBTO_TO30_Msk                (0x40000000UL)            /*!< TO30 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO29_Pos                (29UL)                    /*!< TO29 (Bit 29)                                         */
#define CAN_TXBTO_TO29_Msk                (0x20000000UL)            /*!< TO29 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO28_Pos                (28UL)                    /*!< TO28 (Bit 28)                                         */
#define CAN_TXBTO_TO28_Msk                (0x10000000UL)            /*!< TO28 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO27_Pos                (27UL)                    /*!< TO27 (Bit 27)                                         */
#define CAN_TXBTO_TO27_Msk                (0x8000000UL)             /*!< TO27 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO26_Pos                (26UL)                    /*!< TO26 (Bit 26)                                         */
#define CAN_TXBTO_TO26_Msk                (0x4000000UL)             /*!< TO26 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO25_Pos                (25UL)                    /*!< TO25 (Bit 25)                                         */
#define CAN_TXBTO_TO25_Msk                (0x2000000UL)             /*!< TO25 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO24_Pos                (24UL)                    /*!< TO24 (Bit 24)                                         */
#define CAN_TXBTO_TO24_Msk                (0x1000000UL)             /*!< TO24 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO23_Pos                (23UL)                    /*!< TO23 (Bit 23)                                         */
#define CAN_TXBTO_TO23_Msk                (0x800000UL)              /*!< TO23 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO22_Pos                (22UL)                    /*!< TO22 (Bit 22)                                         */
#define CAN_TXBTO_TO22_Msk                (0x400000UL)              /*!< TO22 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO21_Pos                (21UL)                    /*!< TO21 (Bit 21)                                         */
#define CAN_TXBTO_TO21_Msk                (0x200000UL)              /*!< TO21 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO20_Pos                (20UL)                    /*!< TO20 (Bit 20)                                         */
#define CAN_TXBTO_TO20_Msk                (0x100000UL)              /*!< TO20 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO19_Pos                (19UL)                    /*!< TO19 (Bit 19)                                         */
#define CAN_TXBTO_TO19_Msk                (0x80000UL)               /*!< TO19 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO18_Pos                (18UL)                    /*!< TO18 (Bit 18)                                         */
#define CAN_TXBTO_TO18_Msk                (0x40000UL)               /*!< TO18 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO17_Pos                (17UL)                    /*!< TO17 (Bit 17)                                         */
#define CAN_TXBTO_TO17_Msk                (0x20000UL)               /*!< TO17 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO16_Pos                (16UL)                    /*!< TO16 (Bit 16)                                         */
#define CAN_TXBTO_TO16_Msk                (0x10000UL)               /*!< TO16 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO15_Pos                (15UL)                    /*!< TO15 (Bit 15)                                         */
#define CAN_TXBTO_TO15_Msk                (0x8000UL)                /*!< TO15 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO14_Pos                (14UL)                    /*!< TO14 (Bit 14)                                         */
#define CAN_TXBTO_TO14_Msk                (0x4000UL)                /*!< TO14 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO13_Pos                (13UL)                    /*!< TO13 (Bit 13)                                         */
#define CAN_TXBTO_TO13_Msk                (0x2000UL)                /*!< TO13 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO12_Pos                (12UL)                    /*!< TO12 (Bit 12)                                         */
#define CAN_TXBTO_TO12_Msk                (0x1000UL)                /*!< TO12 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO11_Pos                (11UL)                    /*!< TO11 (Bit 11)                                         */
#define CAN_TXBTO_TO11_Msk                (0x800UL)                 /*!< TO11 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO10_Pos                (10UL)                    /*!< TO10 (Bit 10)                                         */
#define CAN_TXBTO_TO10_Msk                (0x400UL)                 /*!< TO10 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTO_TO9_Pos                 (9UL)                     /*!< TO9 (Bit 9)                                           */
#define CAN_TXBTO_TO9_Msk                 (0x200UL)                 /*!< TO9 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBTO_TO8_Pos                 (8UL)                     /*!< TO8 (Bit 8)                                           */
#define CAN_TXBTO_TO8_Msk                 (0x100UL)                 /*!< TO8 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBTO_TO7_Pos                 (7UL)                     /*!< TO7 (Bit 7)                                           */
#define CAN_TXBTO_TO7_Msk                 (0x80UL)                  /*!< TO7 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBTO_TO6_Pos                 (6UL)                     /*!< TO6 (Bit 6)                                           */
#define CAN_TXBTO_TO6_Msk                 (0x40UL)                  /*!< TO6 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBTO_TO5_Pos                 (5UL)                     /*!< TO5 (Bit 5)                                           */
#define CAN_TXBTO_TO5_Msk                 (0x20UL)                  /*!< TO5 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBTO_TO4_Pos                 (4UL)                     /*!< TO4 (Bit 4)                                           */
#define CAN_TXBTO_TO4_Msk                 (0x10UL)                  /*!< TO4 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBTO_TO3_Pos                 (3UL)                     /*!< TO3 (Bit 3)                                           */
#define CAN_TXBTO_TO3_Msk                 (0x8UL)                   /*!< TO3 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBTO_TO2_Pos                 (2UL)                     /*!< TO2 (Bit 2)                                           */
#define CAN_TXBTO_TO2_Msk                 (0x4UL)                   /*!< TO2 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBTO_TO1_Pos                 (1UL)                     /*!< TO1 (Bit 1)                                           */
#define CAN_TXBTO_TO1_Msk                 (0x2UL)                   /*!< TO1 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBTO_TO0_Pos                 (0UL)                     /*!< TO0 (Bit 0)                                           */
#define CAN_TXBTO_TO0_Msk                 (0x1UL)                   /*!< TO0 (Bitfield-Mask: 0x01)                             */
/* =========================================================  TXBCF  ========================================================= */
#define CAN_TXBCF_CF31_Pos                (31UL)                    /*!< CF31 (Bit 31)                                         */
#define CAN_TXBCF_CF31_Msk                (0x80000000UL)            /*!< CF31 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF30_Pos                (30UL)                    /*!< CF30 (Bit 30)                                         */
#define CAN_TXBCF_CF30_Msk                (0x40000000UL)            /*!< CF30 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF29_Pos                (29UL)                    /*!< CF29 (Bit 29)                                         */
#define CAN_TXBCF_CF29_Msk                (0x20000000UL)            /*!< CF29 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF28_Pos                (28UL)                    /*!< CF28 (Bit 28)                                         */
#define CAN_TXBCF_CF28_Msk                (0x10000000UL)            /*!< CF28 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF27_Pos                (27UL)                    /*!< CF27 (Bit 27)                                         */
#define CAN_TXBCF_CF27_Msk                (0x8000000UL)             /*!< CF27 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF26_Pos                (26UL)                    /*!< CF26 (Bit 26)                                         */
#define CAN_TXBCF_CF26_Msk                (0x4000000UL)             /*!< CF26 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF25_Pos                (25UL)                    /*!< CF25 (Bit 25)                                         */
#define CAN_TXBCF_CF25_Msk                (0x2000000UL)             /*!< CF25 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF24_Pos                (24UL)                    /*!< CF24 (Bit 24)                                         */
#define CAN_TXBCF_CF24_Msk                (0x1000000UL)             /*!< CF24 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF23_Pos                (23UL)                    /*!< CF23 (Bit 23)                                         */
#define CAN_TXBCF_CF23_Msk                (0x800000UL)              /*!< CF23 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF22_Pos                (22UL)                    /*!< CF22 (Bit 22)                                         */
#define CAN_TXBCF_CF22_Msk                (0x400000UL)              /*!< CF22 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF21_Pos                (21UL)                    /*!< CF21 (Bit 21)                                         */
#define CAN_TXBCF_CF21_Msk                (0x200000UL)              /*!< CF21 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF20_Pos                (20UL)                    /*!< CF20 (Bit 20)                                         */
#define CAN_TXBCF_CF20_Msk                (0x100000UL)              /*!< CF20 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF19_Pos                (19UL)                    /*!< CF19 (Bit 19)                                         */
#define CAN_TXBCF_CF19_Msk                (0x80000UL)               /*!< CF19 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF18_Pos                (18UL)                    /*!< CF18 (Bit 18)                                         */
#define CAN_TXBCF_CF18_Msk                (0x40000UL)               /*!< CF18 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF17_Pos                (17UL)                    /*!< CF17 (Bit 17)                                         */
#define CAN_TXBCF_CF17_Msk                (0x20000UL)               /*!< CF17 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF16_Pos                (16UL)                    /*!< CF16 (Bit 16)                                         */
#define CAN_TXBCF_CF16_Msk                (0x10000UL)               /*!< CF16 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF15_Pos                (15UL)                    /*!< CF15 (Bit 15)                                         */
#define CAN_TXBCF_CF15_Msk                (0x8000UL)                /*!< CF15 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF14_Pos                (14UL)                    /*!< CF14 (Bit 14)                                         */
#define CAN_TXBCF_CF14_Msk                (0x4000UL)                /*!< CF14 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF13_Pos                (13UL)                    /*!< CF13 (Bit 13)                                         */
#define CAN_TXBCF_CF13_Msk                (0x2000UL)                /*!< CF13 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF12_Pos                (12UL)                    /*!< CF12 (Bit 12)                                         */
#define CAN_TXBCF_CF12_Msk                (0x1000UL)                /*!< CF12 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF11_Pos                (11UL)                    /*!< CF11 (Bit 11)                                         */
#define CAN_TXBCF_CF11_Msk                (0x800UL)                 /*!< CF11 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF10_Pos                (10UL)                    /*!< CF10 (Bit 10)                                         */
#define CAN_TXBCF_CF10_Msk                (0x400UL)                 /*!< CF10 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBCF_CF9_Pos                 (9UL)                     /*!< CF9 (Bit 9)                                           */
#define CAN_TXBCF_CF9_Msk                 (0x200UL)                 /*!< CF9 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCF_CF8_Pos                 (8UL)                     /*!< CF8 (Bit 8)                                           */
#define CAN_TXBCF_CF8_Msk                 (0x100UL)                 /*!< CF8 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCF_CF7_Pos                 (7UL)                     /*!< CF7 (Bit 7)                                           */
#define CAN_TXBCF_CF7_Msk                 (0x80UL)                  /*!< CF7 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCF_CF6_Pos                 (6UL)                     /*!< CF6 (Bit 6)                                           */
#define CAN_TXBCF_CF6_Msk                 (0x40UL)                  /*!< CF6 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCF_CF5_Pos                 (5UL)                     /*!< CF5 (Bit 5)                                           */
#define CAN_TXBCF_CF5_Msk                 (0x20UL)                  /*!< CF5 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCF_CF4_Pos                 (4UL)                     /*!< CF4 (Bit 4)                                           */
#define CAN_TXBCF_CF4_Msk                 (0x10UL)                  /*!< CF4 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCF_CF3_Pos                 (3UL)                     /*!< CF3 (Bit 3)                                           */
#define CAN_TXBCF_CF3_Msk                 (0x8UL)                   /*!< CF3 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCF_CF2_Pos                 (2UL)                     /*!< CF2 (Bit 2)                                           */
#define CAN_TXBCF_CF2_Msk                 (0x4UL)                   /*!< CF2 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCF_CF1_Pos                 (1UL)                     /*!< CF1 (Bit 1)                                           */
#define CAN_TXBCF_CF1_Msk                 (0x2UL)                   /*!< CF1 (Bitfield-Mask: 0x01)                             */
#define CAN_TXBCF_CF0_Pos                 (0UL)                     /*!< CF0 (Bit 0)                                           */
#define CAN_TXBCF_CF0_Msk                 (0x1UL)                   /*!< CF0 (Bitfield-Mask: 0x01)                             */
/* ========================================================  TXBTIE  ========================================================= */
#define CAN_TXBTIE_TIE31_Pos              (31UL)                    /*!< TIE31 (Bit 31)                                        */
#define CAN_TXBTIE_TIE31_Msk              (0x80000000UL)            /*!< TIE31 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE30_Pos              (30UL)                    /*!< TIE30 (Bit 30)                                        */
#define CAN_TXBTIE_TIE30_Msk              (0x40000000UL)            /*!< TIE30 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE29_Pos              (29UL)                    /*!< TIE29 (Bit 29)                                        */
#define CAN_TXBTIE_TIE29_Msk              (0x20000000UL)            /*!< TIE29 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE28_Pos              (28UL)                    /*!< TIE28 (Bit 28)                                        */
#define CAN_TXBTIE_TIE28_Msk              (0x10000000UL)            /*!< TIE28 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE27_Pos              (27UL)                    /*!< TIE27 (Bit 27)                                        */
#define CAN_TXBTIE_TIE27_Msk              (0x8000000UL)             /*!< TIE27 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE26_Pos              (26UL)                    /*!< TIE26 (Bit 26)                                        */
#define CAN_TXBTIE_TIE26_Msk              (0x4000000UL)             /*!< TIE26 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE25_Pos              (25UL)                    /*!< TIE25 (Bit 25)                                        */
#define CAN_TXBTIE_TIE25_Msk              (0x2000000UL)             /*!< TIE25 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE24_Pos              (24UL)                    /*!< TIE24 (Bit 24)                                        */
#define CAN_TXBTIE_TIE24_Msk              (0x1000000UL)             /*!< TIE24 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE23_Pos              (23UL)                    /*!< TIE23 (Bit 23)                                        */
#define CAN_TXBTIE_TIE23_Msk              (0x800000UL)              /*!< TIE23 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE22_Pos              (22UL)                    /*!< TIE22 (Bit 22)                                        */
#define CAN_TXBTIE_TIE22_Msk              (0x400000UL)              /*!< TIE22 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE21_Pos              (21UL)                    /*!< TIE21 (Bit 21)                                        */
#define CAN_TXBTIE_TIE21_Msk              (0x200000UL)              /*!< TIE21 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE20_Pos              (20UL)                    /*!< TIE20 (Bit 20)                                        */
#define CAN_TXBTIE_TIE20_Msk              (0x100000UL)              /*!< TIE20 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE19_Pos              (19UL)                    /*!< TIE19 (Bit 19)                                        */
#define CAN_TXBTIE_TIE19_Msk              (0x80000UL)               /*!< TIE19 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE18_Pos              (18UL)                    /*!< TIE18 (Bit 18)                                        */
#define CAN_TXBTIE_TIE18_Msk              (0x40000UL)               /*!< TIE18 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE17_Pos              (17UL)                    /*!< TIE17 (Bit 17)                                        */
#define CAN_TXBTIE_TIE17_Msk              (0x20000UL)               /*!< TIE17 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE16_Pos              (16UL)                    /*!< TIE16 (Bit 16)                                        */
#define CAN_TXBTIE_TIE16_Msk              (0x10000UL)               /*!< TIE16 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE15_Pos              (15UL)                    /*!< TIE15 (Bit 15)                                        */
#define CAN_TXBTIE_TIE15_Msk              (0x8000UL)                /*!< TIE15 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE14_Pos              (14UL)                    /*!< TIE14 (Bit 14)                                        */
#define CAN_TXBTIE_TIE14_Msk              (0x4000UL)                /*!< TIE14 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE13_Pos              (13UL)                    /*!< TIE13 (Bit 13)                                        */
#define CAN_TXBTIE_TIE13_Msk              (0x2000UL)                /*!< TIE13 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE12_Pos              (12UL)                    /*!< TIE12 (Bit 12)                                        */
#define CAN_TXBTIE_TIE12_Msk              (0x1000UL)                /*!< TIE12 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE11_Pos              (11UL)                    /*!< TIE11 (Bit 11)                                        */
#define CAN_TXBTIE_TIE11_Msk              (0x800UL)                 /*!< TIE11 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE10_Pos              (10UL)                    /*!< TIE10 (Bit 10)                                        */
#define CAN_TXBTIE_TIE10_Msk              (0x400UL)                 /*!< TIE10 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBTIE_TIE9_Pos               (9UL)                     /*!< TIE9 (Bit 9)                                          */
#define CAN_TXBTIE_TIE9_Msk               (0x200UL)                 /*!< TIE9 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTIE_TIE8_Pos               (8UL)                     /*!< TIE8 (Bit 8)                                          */
#define CAN_TXBTIE_TIE8_Msk               (0x100UL)                 /*!< TIE8 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTIE_TIE7_Pos               (7UL)                     /*!< TIE7 (Bit 7)                                          */
#define CAN_TXBTIE_TIE7_Msk               (0x80UL)                  /*!< TIE7 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTIE_TIE6_Pos               (6UL)                     /*!< TIE6 (Bit 6)                                          */
#define CAN_TXBTIE_TIE6_Msk               (0x40UL)                  /*!< TIE6 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTIE_TIE5_Pos               (5UL)                     /*!< TIE5 (Bit 5)                                          */
#define CAN_TXBTIE_TIE5_Msk               (0x20UL)                  /*!< TIE5 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTIE_TIE4_Pos               (4UL)                     /*!< TIE4 (Bit 4)                                          */
#define CAN_TXBTIE_TIE4_Msk               (0x10UL)                  /*!< TIE4 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTIE_TIE3_Pos               (3UL)                     /*!< TIE3 (Bit 3)                                          */
#define CAN_TXBTIE_TIE3_Msk               (0x8UL)                   /*!< TIE3 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTIE_TIE2_Pos               (2UL)                     /*!< TIE2 (Bit 2)                                          */
#define CAN_TXBTIE_TIE2_Msk               (0x4UL)                   /*!< TIE2 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTIE_TIE1_Pos               (1UL)                     /*!< TIE1 (Bit 1)                                          */
#define CAN_TXBTIE_TIE1_Msk               (0x2UL)                   /*!< TIE1 (Bitfield-Mask: 0x01)                            */
#define CAN_TXBTIE_TIE0_Pos               (0UL)                     /*!< TIE0 (Bit 0)                                          */
#define CAN_TXBTIE_TIE0_Msk               (0x1UL)                   /*!< TIE0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  TXBCIE  ========================================================= */
#define CAN_TXBCIE_CFIE31_Pos             (31UL)                    /*!< CFIE31 (Bit 31)                                       */
#define CAN_TXBCIE_CFIE31_Msk             (0x80000000UL)            /*!< CFIE31 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE30_Pos             (30UL)                    /*!< CFIE30 (Bit 30)                                       */
#define CAN_TXBCIE_CFIE30_Msk             (0x40000000UL)            /*!< CFIE30 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE29_Pos             (29UL)                    /*!< CFIE29 (Bit 29)                                       */
#define CAN_TXBCIE_CFIE29_Msk             (0x20000000UL)            /*!< CFIE29 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE28_Pos             (28UL)                    /*!< CFIE28 (Bit 28)                                       */
#define CAN_TXBCIE_CFIE28_Msk             (0x10000000UL)            /*!< CFIE28 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE27_Pos             (27UL)                    /*!< CFIE27 (Bit 27)                                       */
#define CAN_TXBCIE_CFIE27_Msk             (0x8000000UL)             /*!< CFIE27 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE26_Pos             (26UL)                    /*!< CFIE26 (Bit 26)                                       */
#define CAN_TXBCIE_CFIE26_Msk             (0x4000000UL)             /*!< CFIE26 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE25_Pos             (25UL)                    /*!< CFIE25 (Bit 25)                                       */
#define CAN_TXBCIE_CFIE25_Msk             (0x2000000UL)             /*!< CFIE25 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE24_Pos             (24UL)                    /*!< CFIE24 (Bit 24)                                       */
#define CAN_TXBCIE_CFIE24_Msk             (0x1000000UL)             /*!< CFIE24 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE23_Pos             (23UL)                    /*!< CFIE23 (Bit 23)                                       */
#define CAN_TXBCIE_CFIE23_Msk             (0x800000UL)              /*!< CFIE23 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE22_Pos             (22UL)                    /*!< CFIE22 (Bit 22)                                       */
#define CAN_TXBCIE_CFIE22_Msk             (0x400000UL)              /*!< CFIE22 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE21_Pos             (21UL)                    /*!< CFIE21 (Bit 21)                                       */
#define CAN_TXBCIE_CFIE21_Msk             (0x200000UL)              /*!< CFIE21 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE20_Pos             (20UL)                    /*!< CFIE20 (Bit 20)                                       */
#define CAN_TXBCIE_CFIE20_Msk             (0x100000UL)              /*!< CFIE20 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE19_Pos             (19UL)                    /*!< CFIE19 (Bit 19)                                       */
#define CAN_TXBCIE_CFIE19_Msk             (0x80000UL)               /*!< CFIE19 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE18_Pos             (18UL)                    /*!< CFIE18 (Bit 18)                                       */
#define CAN_TXBCIE_CFIE18_Msk             (0x40000UL)               /*!< CFIE18 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE17_Pos             (17UL)                    /*!< CFIE17 (Bit 17)                                       */
#define CAN_TXBCIE_CFIE17_Msk             (0x20000UL)               /*!< CFIE17 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE16_Pos             (16UL)                    /*!< CFIE16 (Bit 16)                                       */
#define CAN_TXBCIE_CFIE16_Msk             (0x10000UL)               /*!< CFIE16 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE15_Pos             (15UL)                    /*!< CFIE15 (Bit 15)                                       */
#define CAN_TXBCIE_CFIE15_Msk             (0x8000UL)                /*!< CFIE15 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE14_Pos             (14UL)                    /*!< CFIE14 (Bit 14)                                       */
#define CAN_TXBCIE_CFIE14_Msk             (0x4000UL)                /*!< CFIE14 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE13_Pos             (13UL)                    /*!< CFIE13 (Bit 13)                                       */
#define CAN_TXBCIE_CFIE13_Msk             (0x2000UL)                /*!< CFIE13 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE12_Pos             (12UL)                    /*!< CFIE12 (Bit 12)                                       */
#define CAN_TXBCIE_CFIE12_Msk             (0x1000UL)                /*!< CFIE12 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE11_Pos             (11UL)                    /*!< CFIE11 (Bit 11)                                       */
#define CAN_TXBCIE_CFIE11_Msk             (0x800UL)                 /*!< CFIE11 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE10_Pos             (10UL)                    /*!< CFIE10 (Bit 10)                                       */
#define CAN_TXBCIE_CFIE10_Msk             (0x400UL)                 /*!< CFIE10 (Bitfield-Mask: 0x01)                          */
#define CAN_TXBCIE_CFIE9_Pos              (9UL)                     /*!< CFIE9 (Bit 9)                                         */
#define CAN_TXBCIE_CFIE9_Msk              (0x200UL)                 /*!< CFIE9 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBCIE_CFIE8_Pos              (8UL)                     /*!< CFIE8 (Bit 8)                                         */
#define CAN_TXBCIE_CFIE8_Msk              (0x100UL)                 /*!< CFIE8 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBCIE_CFIE7_Pos              (7UL)                     /*!< CFIE7 (Bit 7)                                         */
#define CAN_TXBCIE_CFIE7_Msk              (0x80UL)                  /*!< CFIE7 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBCIE_CFIE6_Pos              (6UL)                     /*!< CFIE6 (Bit 6)                                         */
#define CAN_TXBCIE_CFIE6_Msk              (0x40UL)                  /*!< CFIE6 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBCIE_CFIE5_Pos              (5UL)                     /*!< CFIE5 (Bit 5)                                         */
#define CAN_TXBCIE_CFIE5_Msk              (0x20UL)                  /*!< CFIE5 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBCIE_CFIE4_Pos              (4UL)                     /*!< CFIE4 (Bit 4)                                         */
#define CAN_TXBCIE_CFIE4_Msk              (0x10UL)                  /*!< CFIE4 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBCIE_CFIE3_Pos              (3UL)                     /*!< CFIE3 (Bit 3)                                         */
#define CAN_TXBCIE_CFIE3_Msk              (0x8UL)                   /*!< CFIE3 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBCIE_CFIE2_Pos              (2UL)                     /*!< CFIE2 (Bit 2)                                         */
#define CAN_TXBCIE_CFIE2_Msk              (0x4UL)                   /*!< CFIE2 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBCIE_CFIE1_Pos              (1UL)                     /*!< CFIE1 (Bit 1)                                         */
#define CAN_TXBCIE_CFIE1_Msk              (0x2UL)                   /*!< CFIE1 (Bitfield-Mask: 0x01)                           */
#define CAN_TXBCIE_CFIE0_Pos              (0UL)                     /*!< CFIE0 (Bit 0)                                         */
#define CAN_TXBCIE_CFIE0_Msk              (0x1UL)                   /*!< CFIE0 (Bitfield-Mask: 0x01)                           */
/* =========================================================  TXEFC  ========================================================= */
#define CAN_TXEFC_EFWM_Pos                (24UL)                    /*!< EFWM (Bit 24)                                         */
#define CAN_TXEFC_EFWM_Msk                (0x3f000000UL)            /*!< EFWM (Bitfield-Mask: 0x3f)                            */
#define CAN_TXEFC_EFS_Pos                 (16UL)                    /*!< EFS (Bit 16)                                          */
#define CAN_TXEFC_EFS_Msk                 (0x3f0000UL)              /*!< EFS (Bitfield-Mask: 0x3f)                             */
#define CAN_TXEFC_EFSA_Pos                (2UL)                     /*!< EFSA (Bit 2)                                          */
#define CAN_TXEFC_EFSA_Msk                (0xfffcUL)                /*!< EFSA (Bitfield-Mask: 0x3fff)                          */
/* =========================================================  TXEFS  ========================================================= */
#define CAN_TXEFS_TEFL_Pos                (25UL)                    /*!< TEFL (Bit 25)                                         */
#define CAN_TXEFS_TEFL_Msk                (0x2000000UL)             /*!< TEFL (Bitfield-Mask: 0x01)                            */
#define CAN_TXEFS_EFF_Pos                 (24UL)                    /*!< EFF (Bit 24)                                          */
#define CAN_TXEFS_EFF_Msk                 (0x1000000UL)             /*!< EFF (Bitfield-Mask: 0x01)                             */
#define CAN_TXEFS_EFPI_Pos                (16UL)                    /*!< EFPI (Bit 16)                                         */
#define CAN_TXEFS_EFPI_Msk                (0x1f0000UL)              /*!< EFPI (Bitfield-Mask: 0x1f)                            */
#define CAN_TXEFS_EFGI_Pos                (8UL)                     /*!< EFGI (Bit 8)                                          */
#define CAN_TXEFS_EFGI_Msk                (0x1f00UL)                /*!< EFGI (Bitfield-Mask: 0x1f)                            */
#define CAN_TXEFS_EFFL_Pos                (0UL)                     /*!< EFFL (Bit 0)                                          */
#define CAN_TXEFS_EFFL_Msk                (0x3fUL)                  /*!< EFFL (Bitfield-Mask: 0x3f)                            */
/* =========================================================  TXEFA  ========================================================= */
#define CAN_TXEFA_EFAI_Pos                (0UL)                     /*!< EFAI (Bit 0)                                          */
#define CAN_TXEFA_EFAI_Msk                (0x1fUL)                  /*!< EFAI (Bitfield-Mask: 0x1f)                            */


/* =========================================================================================================================== */
/* ================                                            RCC                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  CLK_DIV  ======================================================== */
#define RCC_CLK_DIV_CSS_FLAG_Pos          (14UL)                    /*!< CSS_FLAG (Bit 14)                                     */
#define RCC_CLK_DIV_CSS_FLAG_Msk          (0x4000UL)                /*!< CSS_FLAG (Bitfield-Mask: 0x01)                        */
#define RCC_CLK_DIV_CSS_EN_Pos            (13UL)                    /*!< CSS_EN (Bit 13)                                       */
#define RCC_CLK_DIV_CSS_EN_Msk            (0x2000UL)                /*!< CSS_EN (Bitfield-Mask: 0x01)                          */
#define RCC_CLK_DIV_PCLK_DIV_UP_Pos       (12UL)                    /*!< PCLK_DIV_UP (Bit 12)                                  */
#define RCC_CLK_DIV_PCLK_DIV_UP_Msk       (0x1000UL)                /*!< PCLK_DIV_UP (Bitfield-Mask: 0x01)                     */
#define RCC_CLK_DIV_PCLK_DIV_Pos          (8UL)                     /*!< PCLK_DIV (Bit 8)                                      */
#define RCC_CLK_DIV_PCLK_DIV_Msk          (0x300UL)                 /*!< PCLK_DIV (Bitfield-Mask: 0x03)                        */
#define RCC_CLK_DIV_CLKSEL_Pos            (5UL)                     /*!< CLKSEL (Bit 5)                                        */
#define RCC_CLK_DIV_CLKSEL_Msk            (0x60UL)                  /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
#define RCC_CLK_DIV_CLK_DIV_UP_Pos        (4UL)                     /*!< CLK_DIV_UP (Bit 4)                                    */
#define RCC_CLK_DIV_CLK_DIV_UP_Msk        (0x10UL)                  /*!< CLK_DIV_UP (Bitfield-Mask: 0x01)                      */
#define RCC_CLK_DIV_CLK_DIV_FACTOR_Pos    (0UL)                     /*!< CLK_DIV_FACTOR (Bit 0)                                */
#define RCC_CLK_DIV_CLK_DIV_FACTOR_Msk    (0xfUL)                   /*!< CLK_DIV_FACTOR (Bitfield-Mask: 0x0f)                  */
/* =====================================================  CLK_GATE_APB  ====================================================== */
#define RCC_CLK_GATE_APB_CLK_EN_DFLASH_Pos (17UL)                   /*!< CLK_EN_DFLASH (Bit 17)                                */
#define RCC_CLK_GATE_APB_CLK_EN_DFLASH_Msk (0x20000UL)              /*!< CLK_EN_DFLASH (Bitfield-Mask: 0x01)                   */
#define RCC_CLK_GATE_APB_CLK_EN_IWDG_Pos  (16UL)                    /*!< CLK_EN_IWDG (Bit 16)                                  */
#define RCC_CLK_GATE_APB_CLK_EN_IWDG_Msk  (0x10000UL)               /*!< CLK_EN_IWDG (Bitfield-Mask: 0x01)                     */
#define RCC_CLK_GATE_APB_CLK_EN_CAN_Pos   (15UL)                    /*!< CLK_EN_CAN (Bit 15)                                   */
#define RCC_CLK_GATE_APB_CLK_EN_CAN_Msk   (0x8000UL)                /*!< CLK_EN_CAN (Bitfield-Mask: 0x01)                      */
#define RCC_CLK_GATE_APB_CLK_EN_EDIAG_Pos (13UL)                    /*!< CLK_EN_EDIAG (Bit 13)                                 */
#define RCC_CLK_GATE_APB_CLK_EN_EDIAG_Msk (0x2000UL)                /*!< CLK_EN_EDIAG (Bitfield-Mask: 0x01)                    */
#define RCC_CLK_GATE_APB_CLK_EN_ECAP_Pos  (12UL)                    /*!< CLK_EN_ECAP (Bit 12)                                  */
#define RCC_CLK_GATE_APB_CLK_EN_ECAP_Msk  (0x1000UL)                /*!< CLK_EN_ECAP (Bitfield-Mask: 0x01)                     */
#define RCC_CLK_GATE_APB_CLK_EN_EPWM_Pos  (11UL)                    /*!< CLK_EN_EPWM (Bit 11)                                  */
#define RCC_CLK_GATE_APB_CLK_EN_EPWM_Msk  (0x800UL)                 /*!< CLK_EN_EPWM (Bitfield-Mask: 0x01)                     */
#define RCC_CLK_GATE_APB_CLK_EN_SPI1_Pos  (10UL)                    /*!< CLK_EN_SPI1 (Bit 10)                                  */
#define RCC_CLK_GATE_APB_CLK_EN_SPI1_Msk  (0x400UL)                 /*!< CLK_EN_SPI1 (Bitfield-Mask: 0x01)                     */
#define RCC_CLK_GATE_APB_CLK_EN_SPI0_Pos  (9UL)                     /*!< CLK_EN_SPI0 (Bit 9)                                   */
#define RCC_CLK_GATE_APB_CLK_EN_SPI0_Msk  (0x200UL)                 /*!< CLK_EN_SPI0 (Bitfield-Mask: 0x01)                     */
#define RCC_CLK_GATE_APB_CLK_EN_ADC1_Pos  (8UL)                     /*!< CLK_EN_ADC1 (Bit 8)                                   */
#define RCC_CLK_GATE_APB_CLK_EN_ADC1_Msk  (0x100UL)                 /*!< CLK_EN_ADC1 (Bitfield-Mask: 0x01)                     */
#define RCC_CLK_GATE_APB_CLK_EN_ADC0_Pos  (7UL)                     /*!< CLK_EN_ADC0 (Bit 7)                                   */
#define RCC_CLK_GATE_APB_CLK_EN_ADC0_Msk  (0x80UL)                  /*!< CLK_EN_ADC0 (Bitfield-Mask: 0x01)                     */
#define RCC_CLK_GATE_APB_CLK_EN_SYSCTRL_Pos (5UL)                   /*!< CLK_EN_SYSCTRL (Bit 5)                                */
#define RCC_CLK_GATE_APB_CLK_EN_SYSCTRL_Msk (0x20UL)                /*!< CLK_EN_SYSCTRL (Bitfield-Mask: 0x01)                  */
#define RCC_CLK_GATE_APB_CLK_EN_TIM0_Pos  (4UL)                     /*!< CLK_EN_TIM0 (Bit 4)                                   */
#define RCC_CLK_GATE_APB_CLK_EN_TIM0_Msk  (0x10UL)                  /*!< CLK_EN_TIM0 (Bitfield-Mask: 0x01)                     */
#define RCC_CLK_GATE_APB_CLK_EN_TIM1_Pos  (3UL)                     /*!< CLK_EN_TIM1 (Bit 3)                                   */
#define RCC_CLK_GATE_APB_CLK_EN_TIM1_Msk  (0x8UL)                   /*!< CLK_EN_TIM1 (Bitfield-Mask: 0x01)                     */
#define RCC_CLK_GATE_APB_CLK_EN_TIM2_Pos  (2UL)                     /*!< CLK_EN_TIM2 (Bit 2)                                   */
#define RCC_CLK_GATE_APB_CLK_EN_TIM2_Msk  (0x4UL)                   /*!< CLK_EN_TIM2 (Bitfield-Mask: 0x01)                     */
#define RCC_CLK_GATE_APB_CLK_EN_UART0_Pos (1UL)                     /*!< CLK_EN_UART0 (Bit 1)                                  */
#define RCC_CLK_GATE_APB_CLK_EN_UART0_Msk (0x2UL)                   /*!< CLK_EN_UART0 (Bitfield-Mask: 0x01)                    */
/* =====================================================  CLK_GATE_AHB  ====================================================== */
#define RCC_CLK_GATE_AHB_CLK_EN_ESCI_Pos  (2UL)                     /*!< CLK_EN_ESCI (Bit 2)                                   */
#define RCC_CLK_GATE_AHB_CLK_EN_ESCI_Msk  (0x4UL)                   /*!< CLK_EN_ESCI (Bitfield-Mask: 0x01)                     */
#define RCC_CLK_GATE_AHB_CLK_EN_DMA_Pos   (1UL)                     /*!< CLK_EN_DMA (Bit 1)                                    */
#define RCC_CLK_GATE_AHB_CLK_EN_DMA_Msk   (0x2UL)                   /*!< CLK_EN_DMA (Bitfield-Mask: 0x01)                      */
#define RCC_CLK_GATE_AHB_CLK_EN_GPIO_Pos  (0UL)                     /*!< CLK_EN_GPIO (Bit 0)                                   */
#define RCC_CLK_GATE_AHB_CLK_EN_GPIO_Msk  (0x1UL)                   /*!< CLK_EN_GPIO (Bitfield-Mask: 0x01)                     */
/* =================================================  SYSTEM_SOFTWARE_RESET  ================================================= */
#define RCC_SYSTEM_SOFTWARE_RESET_SYS_SW_RST_EN_Pos (24UL)          /*!< SYS_SW_RST_EN (Bit 24)                                */
#define RCC_SYSTEM_SOFTWARE_RESET_SYS_SW_RST_EN_Msk (0xff000000UL)  /*!< SYS_SW_RST_EN (Bitfield-Mask: 0xff)                   */
#define RCC_SYSTEM_SOFTWARE_RESET_SYS_SW_RST_Pos (0UL)              /*!< SYS_SW_RST (Bit 0)                                    */
#define RCC_SYSTEM_SOFTWARE_RESET_SYS_SW_RST_Msk (0x1UL)            /*!< SYS_SW_RST (Bitfield-Mask: 0x01)                      */
/* ==================================================  MODULE_SW_RESET_APB  ================================================== */
#define RCC_MODULE_SW_RESET_APB_SW_RST_DFLASH_Pos (17UL)            /*!< SW_RST_DFLASH (Bit 17)                                */
#define RCC_MODULE_SW_RESET_APB_SW_RST_DFLASH_Msk (0x20000UL)       /*!< SW_RST_DFLASH (Bitfield-Mask: 0x01)                   */
#define RCC_MODULE_SW_RESET_APB_SW_RST_IWDG_Pos (16UL)              /*!< SW_RST_IWDG (Bit 16)                                  */
#define RCC_MODULE_SW_RESET_APB_SW_RST_IWDG_Msk (0x10000UL)         /*!< SW_RST_IWDG (Bitfield-Mask: 0x01)                     */
#define RCC_MODULE_SW_RESET_APB_SW_RST_CAN0_Pos (15UL)              /*!< SW_RST_CAN0 (Bit 15)                                  */
#define RCC_MODULE_SW_RESET_APB_SW_RST_CAN0_Msk (0x8000UL)          /*!< SW_RST_CAN0 (Bitfield-Mask: 0x01)                     */
#define RCC_MODULE_SW_RESET_APB_SW_RST_EDIAG_Pos (13UL)             /*!< SW_RST_EDIAG (Bit 13)                                 */
#define RCC_MODULE_SW_RESET_APB_SW_RST_EDIAG_Msk (0x2000UL)         /*!< SW_RST_EDIAG (Bitfield-Mask: 0x01)                    */
#define RCC_MODULE_SW_RESET_APB_SW_RST_ECAP_Pos (12UL)              /*!< SW_RST_ECAP (Bit 12)                                  */
#define RCC_MODULE_SW_RESET_APB_SW_RST_ECAP_Msk (0x1000UL)          /*!< SW_RST_ECAP (Bitfield-Mask: 0x01)                     */
#define RCC_MODULE_SW_RESET_APB_SW_RST_EPWM_Pos (11UL)              /*!< SW_RST_EPWM (Bit 11)                                  */
#define RCC_MODULE_SW_RESET_APB_SW_RST_EPWM_Msk (0x800UL)           /*!< SW_RST_EPWM (Bitfield-Mask: 0x01)                     */
#define RCC_MODULE_SW_RESET_APB_SW_RST_SPI1_Pos (10UL)              /*!< SW_RST_SPI1 (Bit 10)                                  */
#define RCC_MODULE_SW_RESET_APB_SW_RST_SPI1_Msk (0x400UL)           /*!< SW_RST_SPI1 (Bitfield-Mask: 0x01)                     */
#define RCC_MODULE_SW_RESET_APB_SW_RST_SPI0_Pos (9UL)               /*!< SW_RST_SPI0 (Bit 9)                                   */
#define RCC_MODULE_SW_RESET_APB_SW_RST_SPI0_Msk (0x200UL)           /*!< SW_RST_SPI0 (Bitfield-Mask: 0x01)                     */
#define RCC_MODULE_SW_RESET_APB_SW_RST_ADC1_Pos (8UL)               /*!< SW_RST_ADC1 (Bit 8)                                   */
#define RCC_MODULE_SW_RESET_APB_SW_RST_ADC1_Msk (0x100UL)           /*!< SW_RST_ADC1 (Bitfield-Mask: 0x01)                     */
#define RCC_MODULE_SW_RESET_APB_SW_RST_ADC0_Pos (7UL)               /*!< SW_RST_ADC0 (Bit 7)                                   */
#define RCC_MODULE_SW_RESET_APB_SW_RST_ADC0_Msk (0x80UL)            /*!< SW_RST_ADC0 (Bitfield-Mask: 0x01)                     */
#define RCC_MODULE_SW_RESET_APB_SW_RST_SYSCTRL_Pos (5UL)            /*!< SW_RST_SYSCTRL (Bit 5)                                */
#define RCC_MODULE_SW_RESET_APB_SW_RST_SYSCTRL_Msk (0x20UL)         /*!< SW_RST_SYSCTRL (Bitfield-Mask: 0x01)                  */
#define RCC_MODULE_SW_RESET_APB_SW_RST_TIM0_Pos (4UL)               /*!< SW_RST_TIM0 (Bit 4)                                   */
#define RCC_MODULE_SW_RESET_APB_SW_RST_TIM0_Msk (0x10UL)            /*!< SW_RST_TIM0 (Bitfield-Mask: 0x01)                     */
#define RCC_MODULE_SW_RESET_APB_SW_RST_TIM1_Pos (3UL)               /*!< SW_RST_TIM1 (Bit 3)                                   */
#define RCC_MODULE_SW_RESET_APB_SW_RST_TIM1_Msk (0x8UL)             /*!< SW_RST_TIM1 (Bitfield-Mask: 0x01)                     */
#define RCC_MODULE_SW_RESET_APB_SW_RST_TIM2_Pos (2UL)               /*!< SW_RST_TIM2 (Bit 2)                                   */
#define RCC_MODULE_SW_RESET_APB_SW_RST_TIM2_Msk (0x4UL)             /*!< SW_RST_TIM2 (Bitfield-Mask: 0x01)                     */
#define RCC_MODULE_SW_RESET_APB_SW_RST_UART0_Pos (1UL)              /*!< SW_RST_UART0 (Bit 1)                                  */
#define RCC_MODULE_SW_RESET_APB_SW_RST_UART0_Msk (0x2UL)            /*!< SW_RST_UART0 (Bitfield-Mask: 0x01)                    */
#define RCC_MODULE_SW_RESET_APB_sw_rst_wwdg_Pos (0UL)               /*!< sw_rst_wwdg (Bit 0)                                   */
#define RCC_MODULE_SW_RESET_APB_sw_rst_wwdg_Msk (0x1UL)             /*!< sw_rst_wwdg (Bitfield-Mask: 0x01)                     */
/* ==================================================  MODULE_SW_RESET_AHB  ================================================== */
#define RCC_MODULE_SW_RESET_AHB_SW_RST_ESCI_Pos (2UL)               /*!< SW_RST_ESCI (Bit 2)                                   */
#define RCC_MODULE_SW_RESET_AHB_SW_RST_ESCI_Msk (0x4UL)             /*!< SW_RST_ESCI (Bitfield-Mask: 0x01)                     */
#define RCC_MODULE_SW_RESET_AHB_SW_RST_DMA_Pos (1UL)                /*!< SW_RST_DMA (Bit 1)                                    */
#define RCC_MODULE_SW_RESET_AHB_SW_RST_DMA_Msk (0x2UL)              /*!< SW_RST_DMA (Bitfield-Mask: 0x01)                      */
#define RCC_MODULE_SW_RESET_AHB_SW_RST_GPIO_Pos (0UL)               /*!< SW_RST_GPIO (Bit 0)                                   */
#define RCC_MODULE_SW_RESET_AHB_SW_RST_GPIO_Msk (0x1UL)             /*!< SW_RST_GPIO (Bitfield-Mask: 0x01)                     */
/* =======================================================  PLL_CFG1  ======================================================== */
#define RCC_PLL_CFG1_PLL_REF_DIV_Pos      (30UL)                    /*!< PLL_REF_DIV (Bit 30)                                  */
#define RCC_PLL_CFG1_PLL_REF_DIV_Msk      (0xc0000000UL)            /*!< PLL_REF_DIV (Bitfield-Mask: 0x03)                     */
#define RCC_PLL_CFG1_PLL_LOOPDIV_Pos      (16UL)                    /*!< PLL_LOOPDIV (Bit 16)                                  */
#define RCC_PLL_CFG1_PLL_LOOPDIV_Msk      (0xff0000UL)              /*!< PLL_LOOPDIV (Bitfield-Mask: 0xff)                     */
#define RCC_PLL_CFG1_PLL_PREDIV_Pos       (8UL)                     /*!< PLL_PREDIV (Bit 8)                                    */
#define RCC_PLL_CFG1_PLL_PREDIV_Msk       (0x300UL)                 /*!< PLL_PREDIV (Bitfield-Mask: 0x03)                      */
#define RCC_PLL_CFG1_PLL_POSTDIV_Pos      (4UL)                     /*!< PLL_POSTDIV (Bit 4)                                   */
#define RCC_PLL_CFG1_PLL_POSTDIV_Msk      (0x30UL)                  /*!< PLL_POSTDIV (Bitfield-Mask: 0x03)                     */
#define RCC_PLL_CFG1_PLL_REF_SEL_Pos      (2UL)                     /*!< PLL_REF_SEL (Bit 2)                                   */
#define RCC_PLL_CFG1_PLL_REF_SEL_Msk      (0x4UL)                   /*!< PLL_REF_SEL (Bitfield-Mask: 0x01)                     */
#define RCC_PLL_CFG1_PLL_STABLE_Pos       (1UL)                     /*!< PLL_STABLE (Bit 1)                                    */
#define RCC_PLL_CFG1_PLL_STABLE_Msk       (0x2UL)                   /*!< PLL_STABLE (Bitfield-Mask: 0x01)                      */
#define RCC_PLL_CFG1_PLL_EN_Pos           (0UL)                     /*!< PLL_EN (Bit 0)                                        */
#define RCC_PLL_CFG1_PLL_EN_Msk           (0x1UL)                   /*!< PLL_EN (Bitfield-Mask: 0x01)                          */
/* =======================================================  PLL_CFG2  ======================================================== */
#define RCC_PLL_CFG2_PLL_LDOVREFSEL_Pos   (28UL)                    /*!< PLL_LDOVREFSEL (Bit 28)                               */
#define RCC_PLL_CFG2_PLL_LDOVREFSEL_Msk   (0x70000000UL)            /*!< PLL_LDOVREFSEL (Bitfield-Mask: 0x07)                  */
#define RCC_PLL_CFG2_PLL_CKUSABLE_DIVSEL_Pos (16UL)                 /*!< PLL_CKUSABLE_DIVSEL (Bit 16)                          */
#define RCC_PLL_CFG2_PLL_CKUSABLE_DIVSEL_Msk (0x3ff0000UL)          /*!< PLL_CKUSABLE_DIVSEL (Bitfield-Mask: 0x3ff)            */
#define RCC_PLL_CFG2_PLL_ICP_Pos          (10UL)                    /*!< PLL_ICP (Bit 10)                                      */
#define RCC_PLL_CFG2_PLL_ICP_Msk          (0x3c00UL)                /*!< PLL_ICP (Bitfield-Mask: 0x0f)                         */
#define RCC_PLL_CFG2_PLL_CCOBAND_Pos      (9UL)                     /*!< PLL_CCOBAND (Bit 9)                                   */
#define RCC_PLL_CFG2_PLL_CCOBAND_Msk      (0x200UL)                 /*!< PLL_CCOBAND (Bitfield-Mask: 0x01)                     */
#define RCC_PLL_CFG2_PLL_KVCO_Pos         (8UL)                     /*!< PLL_KVCO (Bit 8)                                      */
#define RCC_PLL_CFG2_PLL_KVCO_Msk         (0x100UL)                 /*!< PLL_KVCO (Bitfield-Mask: 0x01)                        */
#define RCC_PLL_CFG2_PLL_LPF_RSEL_Pos     (1UL)                     /*!< PLL_LPF_RSEL (Bit 1)                                  */
#define RCC_PLL_CFG2_PLL_LPF_RSEL_Msk     (0xeUL)                   /*!< PLL_LPF_RSEL (Bitfield-Mask: 0x07)                    */
#define RCC_PLL_CFG2_PLL_LPF_C_Pos        (0UL)                     /*!< PLL_LPF_C (Bit 0)                                     */
#define RCC_PLL_CFG2_PLL_LPF_C_Msk        (0x1UL)                   /*!< PLL_LPF_C (Bitfield-Mask: 0x01)                       */
/* ========================================================  PLL_DBG  ======================================================== */
#define RCC_PLL_DBG_PLL_DBG_OUT_Pos       (31UL)                    /*!< PLL_DBG_OUT (Bit 31)                                  */
#define RCC_PLL_DBG_PLL_DBG_OUT_Msk       (0x80000000UL)            /*!< PLL_DBG_OUT (Bitfield-Mask: 0x01)                     */
#define RCC_PLL_DBG_PLL_ANA_DBG_Pos       (16UL)                    /*!< PLL_ANA_DBG (Bit 16)                                  */
#define RCC_PLL_DBG_PLL_ANA_DBG_Msk       (0x70000UL)               /*!< PLL_ANA_DBG (Bitfield-Mask: 0x07)                     */
#define RCC_PLL_DBG_PLL_DIG_DBG_Pos       (0UL)                     /*!< PLL_DIG_DBG (Bit 0)                                   */
#define RCC_PLL_DBG_PLL_DIG_DBG_Msk       (0x7UL)                   /*!< PLL_DIG_DBG (Bitfield-Mask: 0x07)                     */
/* ==========================================================  CIR  ========================================================== */
#define RCC_CIR_PLL_STABLT_INT_CLR_Pos    (16UL)                    /*!< PLL_STABLT_INT_CLR (Bit 16)                           */
#define RCC_CIR_PLL_STABLT_INT_CLR_Msk    (0x10000UL)               /*!< PLL_STABLT_INT_CLR (Bitfield-Mask: 0x01)              */
#define RCC_CIR_PLL_STABLT_INT_FLAG_Pos   (8UL)                     /*!< PLL_STABLT_INT_FLAG (Bit 8)                           */
#define RCC_CIR_PLL_STABLT_INT_FLAG_Msk   (0x100UL)                 /*!< PLL_STABLT_INT_FLAG (Bitfield-Mask: 0x01)             */
#define RCC_CIR_PLL_IE_Pos                (0UL)                     /*!< PLL_IE (Bit 0)                                        */
#define RCC_CIR_PLL_IE_Msk                (0x1UL)                   /*!< PLL_IE (Bitfield-Mask: 0x01)                          */
/* =======================================================  EXTAL_CFG  ======================================================= */
#define RCC_EXTAL_CFG_STG_Pos             (16UL)                    /*!< STG (Bit 16)                                          */
#define RCC_EXTAL_CFG_STG_Msk             (0x70000UL)               /*!< STG (Bitfield-Mask: 0x07)                             */
#define RCC_EXTAL_CFG_OUT_EN_Pos          (1UL)                     /*!< OUT_EN (Bit 1)                                        */
#define RCC_EXTAL_CFG_OUT_EN_Msk          (0x2UL)                   /*!< OUT_EN (Bitfield-Mask: 0x01)                          */
#define RCC_EXTAL_CFG_IN_EN_Pos           (0UL)                     /*!< IN_EN (Bit 0)                                         */
#define RCC_EXTAL_CFG_IN_EN_Msk           (0x1UL)                   /*!< IN_EN (Bitfield-Mask: 0x01)                           */
/* ======================================================  RST_REASON  ======================================================= */
#define RCC_RST_REASON_RST_REASON_STATUS_Pos (0UL)                  /*!< RST_REASON_STATUS (Bit 0)                             */
#define RCC_RST_REASON_RST_REASON_STATUS_Msk (0xfUL)                /*!< RST_REASON_STATUS (Bitfield-Mask: 0x0f)               */
/* ======================================================  LDO1P5_CFG  ======================================================= */
#define RCC_LDO1P5_CFG_d2a_ov15_level_Pos (8UL)                     /*!< d2a_ov15_level (Bit 8)                                */
#define RCC_LDO1P5_CFG_d2a_ov15_level_Msk (0x700UL)                 /*!< d2a_ov15_level (Bitfield-Mask: 0x07)                  */
#define RCC_LDO1P5_CFG_d2a_uv15_level_Pos (4UL)                     /*!< d2a_uv15_level (Bit 4)                                */
#define RCC_LDO1P5_CFG_d2a_uv15_level_Msk (0x70UL)                  /*!< d2a_uv15_level (Bitfield-Mask: 0x07)                  */
#define RCC_LDO1P5_CFG_d2a_ov15_en_Pos    (1UL)                     /*!< d2a_ov15_en (Bit 1)                                   */
#define RCC_LDO1P5_CFG_d2a_ov15_en_Msk    (0x2UL)                   /*!< d2a_ov15_en (Bitfield-Mask: 0x01)                     */
#define RCC_LDO1P5_CFG_d2a_uv15_en_Pos    (0UL)                     /*!< d2a_uv15_en (Bit 0)                                   */
#define RCC_LDO1P5_CFG_d2a_uv15_en_Msk    (0x1UL)                   /*!< d2a_uv15_en (Bitfield-Mask: 0x01)                     */
/* ======================================================  LDO5P0_CFG  ======================================================= */
#define RCC_LDO5P0_CFG_d2a_ov50_level_Pos (8UL)                     /*!< d2a_ov50_level (Bit 8)                                */
#define RCC_LDO5P0_CFG_d2a_ov50_level_Msk (0x700UL)                 /*!< d2a_ov50_level (Bitfield-Mask: 0x07)                  */
#define RCC_LDO5P0_CFG_d2a_uv50_level_Pos (4UL)                     /*!< d2a_uv50_level (Bit 4)                                */
#define RCC_LDO5P0_CFG_d2a_uv50_level_Msk (0x70UL)                  /*!< d2a_uv50_level (Bitfield-Mask: 0x07)                  */
#define RCC_LDO5P0_CFG_d2a_en_test_avdd50_div_Pos (2UL)             /*!< d2a_en_test_avdd50_div (Bit 2)                        */
#define RCC_LDO5P0_CFG_d2a_en_test_avdd50_div_Msk (0x4UL)           /*!< d2a_en_test_avdd50_div (Bitfield-Mask: 0x01)          */
#define RCC_LDO5P0_CFG_d2a_ov50_en_Pos    (1UL)                     /*!< d2a_ov50_en (Bit 1)                                   */
#define RCC_LDO5P0_CFG_d2a_ov50_en_Msk    (0x2UL)                   /*!< d2a_ov50_en (Bitfield-Mask: 0x01)                     */
#define RCC_LDO5P0_CFG_d2a_uv50_en_Pos    (0UL)                     /*!< d2a_uv50_en (Bit 0)                                   */
#define RCC_LDO5P0_CFG_d2a_uv50_en_Msk    (0x1UL)                   /*!< d2a_uv50_en (Bitfield-Mask: 0x01)                     */
/* ======================================================  BG_OTP_CFG  ======================================================= */
#define RCC_BG_OTP_CFG_d2a_otp_sel_Pos    (4UL)                     /*!< d2a_otp_sel (Bit 4)                                   */
#define RCC_BG_OTP_CFG_d2a_otp_sel_Msk    (0xf0UL)                  /*!< d2a_otp_sel (Bitfield-Mask: 0x0f)                     */
#define RCC_BG_OTP_CFG_d2a_bg_bf_en_Pos   (1UL)                     /*!< d2a_bg_bf_en (Bit 1)                                  */
#define RCC_BG_OTP_CFG_d2a_bg_bf_en_Msk   (0x2UL)                   /*!< d2a_bg_bf_en (Bitfield-Mask: 0x01)                    */
#define RCC_BG_OTP_CFG_d2a_otp_en_Pos     (0UL)                     /*!< d2a_otp_en (Bit 0)                                    */
#define RCC_BG_OTP_CFG_d2a_otp_en_Msk     (0x1UL)                   /*!< d2a_otp_en (Bitfield-Mask: 0x01)                      */
/* =====================================================  VT_RST_ENABLE  ===================================================== */
#define RCC_VT_RST_ENABLE_IWDG_Pos        (9UL)                     /*!< IWDG (Bit 9)                                          */
#define RCC_VT_RST_ENABLE_IWDG_Msk        (0x200UL)                 /*!< IWDG (Bitfield-Mask: 0x01)                            */
#define RCC_VT_RST_ENABLE_LDO15OC_RST_EN_Pos (8UL)                  /*!< LDO15OC_RST_EN (Bit 8)                                */
#define RCC_VT_RST_ENABLE_LDO15OC_RST_EN_Msk (0x100UL)              /*!< LDO15OC_RST_EN (Bitfield-Mask: 0x01)                  */
#define RCC_VT_RST_ENABLE_BG_OTP_RST_EN_Pos (7UL)                   /*!< BG_OTP_RST_EN (Bit 7)                                 */
#define RCC_VT_RST_ENABLE_BG_OTP_RST_EN_Msk (0x80UL)                /*!< BG_OTP_RST_EN (Bitfield-Mask: 0x01)                   */
#define RCC_VT_RST_ENABLE_UV50_RST_EN_Pos (6UL)                     /*!< UV50_RST_EN (Bit 6)                                   */
#define RCC_VT_RST_ENABLE_UV50_RST_EN_Msk (0x40UL)                  /*!< UV50_RST_EN (Bitfield-Mask: 0x01)                     */
#define RCC_VT_RST_ENABLE_OV50_RST_EN_Pos (5UL)                     /*!< OV50_RST_EN (Bit 5)                                   */
#define RCC_VT_RST_ENABLE_OV50_RST_EN_Msk (0x20UL)                  /*!< OV50_RST_EN (Bitfield-Mask: 0x01)                     */
#define RCC_VT_RST_ENABLE_OTP_RST_EN_Pos  (4UL)                     /*!< OTP_RST_EN (Bit 4)                                    */
#define RCC_VT_RST_ENABLE_OTP_RST_EN_Msk  (0x10UL)                  /*!< OTP_RST_EN (Bitfield-Mask: 0x01)                      */
#define RCC_VT_RST_ENABLE_UV15_RST_EN_Pos (3UL)                     /*!< UV15_RST_EN (Bit 3)                                   */
#define RCC_VT_RST_ENABLE_UV15_RST_EN_Msk (0x8UL)                   /*!< UV15_RST_EN (Bitfield-Mask: 0x01)                     */
#define RCC_VT_RST_ENABLE_OV15_RST_EN_Pos (2UL)                     /*!< OV15_RST_EN (Bit 2)                                   */
#define RCC_VT_RST_ENABLE_OV15_RST_EN_Msk (0x4UL)                   /*!< OV15_RST_EN (Bitfield-Mask: 0x01)                     */
/* ======================================================  INT_STATUS  ======================================================= */
#define RCC_INT_STATUS_LDO15OC_OTP_LV_Pos (8UL)                     /*!< LDO15OC_OTP_LV (Bit 8)                                */
#define RCC_INT_STATUS_LDO15OC_OTP_LV_Msk (0x100UL)                 /*!< LDO15OC_OTP_LV (Bitfield-Mask: 0x01)                  */
#define RCC_INT_STATUS_BG_OTP_LV_Pos      (7UL)                     /*!< BG_OTP_LV (Bit 7)                                     */
#define RCC_INT_STATUS_BG_OTP_LV_Msk      (0x80UL)                  /*!< BG_OTP_LV (Bitfield-Mask: 0x01)                       */
#define RCC_INT_STATUS_UV50_LV_Pos        (6UL)                     /*!< UV50_LV (Bit 6)                                       */
#define RCC_INT_STATUS_UV50_LV_Msk        (0x40UL)                  /*!< UV50_LV (Bitfield-Mask: 0x01)                         */
#define RCC_INT_STATUS_OV50_LV_Pos        (5UL)                     /*!< OV50_LV (Bit 5)                                       */
#define RCC_INT_STATUS_OV50_LV_Msk        (0x20UL)                  /*!< OV50_LV (Bitfield-Mask: 0x01)                         */
#define RCC_INT_STATUS_UV15_LV_Pos        (3UL)                     /*!< UV15_LV (Bit 3)                                       */
#define RCC_INT_STATUS_UV15_LV_Msk        (0x8UL)                   /*!< UV15_LV (Bitfield-Mask: 0x01)                         */
#define RCC_INT_STATUS_OV15_LV_Pos        (2UL)                     /*!< OV15_LV (Bit 2)                                       */
#define RCC_INT_STATUS_OV15_LV_Msk        (0x4UL)                   /*!< OV15_LV (Bitfield-Mask: 0x01)                         */
/* ======================================================  INT_ENABLE  ======================================================= */
#define RCC_INT_ENABLE_LDP15OC_INT_EN_Pos (8UL)                     /*!< LDP15OC_INT_EN (Bit 8)                                */
#define RCC_INT_ENABLE_LDP15OC_INT_EN_Msk (0x100UL)                 /*!< LDP15OC_INT_EN (Bitfield-Mask: 0x01)                  */
#define RCC_INT_ENABLE_BG_OTP_INT_EN_Pos  (7UL)                     /*!< BG_OTP_INT_EN (Bit 7)                                 */
#define RCC_INT_ENABLE_BG_OTP_INT_EN_Msk  (0x80UL)                  /*!< BG_OTP_INT_EN (Bitfield-Mask: 0x01)                   */
#define RCC_INT_ENABLE_UV50_INT_EN_Pos    (6UL)                     /*!< UV50_INT_EN (Bit 6)                                   */
#define RCC_INT_ENABLE_UV50_INT_EN_Msk    (0x40UL)                  /*!< UV50_INT_EN (Bitfield-Mask: 0x01)                     */
#define RCC_INT_ENABLE_OV50_INT_EN_Pos    (5UL)                     /*!< OV50_INT_EN (Bit 5)                                   */
#define RCC_INT_ENABLE_OV50_INT_EN_Msk    (0x20UL)                  /*!< OV50_INT_EN (Bitfield-Mask: 0x01)                     */
#define RCC_INT_ENABLE_UV15_INT_EN_Pos    (3UL)                     /*!< UV15_INT_EN (Bit 3)                                   */
#define RCC_INT_ENABLE_UV15_INT_EN_Msk    (0x8UL)                   /*!< UV15_INT_EN (Bitfield-Mask: 0x01)                     */
#define RCC_INT_ENABLE_OV15_INT_EN_Pos    (2UL)                     /*!< OV15_INT_EN (Bit 2)                                   */
#define RCC_INT_ENABLE_OV15_INT_EN_Msk    (0x4UL)                   /*!< OV15_INT_EN (Bitfield-Mask: 0x01)                     */
/* =======================================================  INT_CLEAR  ======================================================= */
#define RCC_INT_CLEAR_LDO15OC_INT_CLR_Pos (8UL)                     /*!< LDO15OC_INT_CLR (Bit 8)                               */
#define RCC_INT_CLEAR_LDO15OC_INT_CLR_Msk (0x100UL)                 /*!< LDO15OC_INT_CLR (Bitfield-Mask: 0x01)                 */
#define RCC_INT_CLEAR_BG_OTP_INT_CLR_Pos  (7UL)                     /*!< BG_OTP_INT_CLR (Bit 7)                                */
#define RCC_INT_CLEAR_BG_OTP_INT_CLR_Msk  (0x80UL)                  /*!< BG_OTP_INT_CLR (Bitfield-Mask: 0x01)                  */
#define RCC_INT_CLEAR_UV50_INT_CLR_Pos    (6UL)                     /*!< UV50_INT_CLR (Bit 6)                                  */
#define RCC_INT_CLEAR_UV50_INT_CLR_Msk    (0x40UL)                  /*!< UV50_INT_CLR (Bitfield-Mask: 0x01)                    */
#define RCC_INT_CLEAR_OV50_INT_CLR_Pos    (5UL)                     /*!< OV50_INT_CLR (Bit 5)                                  */
#define RCC_INT_CLEAR_OV50_INT_CLR_Msk    (0x20UL)                  /*!< OV50_INT_CLR (Bitfield-Mask: 0x01)                    */
#define RCC_INT_CLEAR_UV15_INT_CLR_Pos    (3UL)                     /*!< UV15_INT_CLR (Bit 3)                                  */
#define RCC_INT_CLEAR_UV15_INT_CLR_Msk    (0x8UL)                   /*!< UV15_INT_CLR (Bitfield-Mask: 0x01)                    */
#define RCC_INT_CLEAR_OV15_INT_CLR_Pos    (2UL)                     /*!< OV15_INT_CLR (Bit 2)                                  */
#define RCC_INT_CLEAR_OV15_INT_CLR_Msk    (0x4UL)                   /*!< OV15_INT_CLR (Bitfield-Mask: 0x01)                    */
/* =======================================================  BIAS_CFG  ======================================================== */
#define RCC_BIAS_CFG_d2a_ibias_en_Pos     (0UL)                     /*!< d2a_ibias_en (Bit 0)                                  */
#define RCC_BIAS_CFG_d2a_ibias_en_Msk     (0x1UL)                   /*!< d2a_ibias_en (Bitfield-Mask: 0x01)                    */
/* ========================================================  SSC_CFG  ======================================================== */
#define RCC_SSC_CFG_ssc_freq_stay_Pos     (16UL)                    /*!< ssc_freq_stay (Bit 16)                                */
#define RCC_SSC_CFG_ssc_freq_stay_Msk     (0x7f0000UL)              /*!< ssc_freq_stay (Bitfield-Mask: 0x7f)                   */
#define RCC_SSC_CFG_ssc_freq_range_Pos    (8UL)                     /*!< ssc_freq_range (Bit 8)                                */
#define RCC_SSC_CFG_ssc_freq_range_Msk    (0xf00UL)                 /*!< ssc_freq_range (Bitfield-Mask: 0x0f)                  */
#define RCC_SSC_CFG_ssc_freq_step_Pos     (4UL)                     /*!< ssc_freq_step (Bit 4)                                 */
#define RCC_SSC_CFG_ssc_freq_step_Msk     (0xf0UL)                  /*!< ssc_freq_step (Bitfield-Mask: 0x0f)                   */
#define RCC_SSC_CFG_ssc_en_Pos            (3UL)                     /*!< ssc_en (Bit 3)                                        */
#define RCC_SSC_CFG_ssc_en_Msk            (0x8UL)                   /*!< ssc_en (Bitfield-Mask: 0x01)                          */
#define RCC_SSC_CFG_ssc_mode_Pos          (0UL)                     /*!< ssc_mode (Bit 0)                                      */
#define RCC_SSC_CFG_ssc_mode_Msk          (0x3UL)                   /*!< ssc_mode (Bitfield-Mask: 0x03)                        */
/* ========================================================  CLK_MUX  ======================================================== */
#define RCC_CLK_MUX_ADC_CLK_SEL_Pos       (21UL)                    /*!< ADC_CLK_SEL (Bit 21)                                  */
#define RCC_CLK_MUX_ADC_CLK_SEL_Msk       (0x200000UL)              /*!< ADC_CLK_SEL (Bitfield-Mask: 0x01)                     */
#define RCC_CLK_MUX_ADC_DIV_UP_Pos        (20UL)                    /*!< ADC_DIV_UP (Bit 20)                                   */
#define RCC_CLK_MUX_ADC_DIV_UP_Msk        (0x100000UL)              /*!< ADC_DIV_UP (Bitfield-Mask: 0x01)                      */
#define RCC_CLK_MUX_ADC_DIV_Pos           (16UL)                    /*!< ADC_DIV (Bit 16)                                      */
#define RCC_CLK_MUX_ADC_DIV_Msk           (0x30000UL)               /*!< ADC_DIV (Bitfield-Mask: 0x03)                         */
#define RCC_CLK_MUX_dbg_clk_sel_Pos       (2UL)                     /*!< dbg_clk_sel (Bit 2)                                   */
#define RCC_CLK_MUX_dbg_clk_sel_Msk       (0xcUL)                   /*!< dbg_clk_sel (Bitfield-Mask: 0x03)                     */
#define RCC_CLK_MUX_lin_baud_clk_sel_Pos  (1UL)                     /*!< lin_baud_clk_sel (Bit 1)                              */
#define RCC_CLK_MUX_lin_baud_clk_sel_Msk  (0x2UL)                   /*!< lin_baud_clk_sel (Bitfield-Mask: 0x01)                */
#define RCC_CLK_MUX_osc_dbg_sel_Pos       (0UL)                     /*!< osc_dbg_sel (Bit 0)                                   */
#define RCC_CLK_MUX_osc_dbg_sel_Msk       (0x1UL)                   /*!< osc_dbg_sel (Bitfield-Mask: 0x01)                     */


/* =========================================================================================================================== */
/* ================                                           eDIAG                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  STS  ========================================================== */
#define eDIAG_STS_BRK_FILED_Pos           (22UL)                    /*!< BRK_FILED (Bit 22)                                    */
#define eDIAG_STS_BRK_FILED_Msk           (0x400000UL)              /*!< BRK_FILED (Bitfield-Mask: 0x01)                       */
#define eDIAG_STS_OTP_FILED_Pos           (21UL)                    /*!< OTP_FILED (Bit 21)                                    */
#define eDIAG_STS_OTP_FILED_Msk           (0x200000UL)              /*!< OTP_FILED (Bitfield-Mask: 0x01)                       */
#define eDIAG_STS_OV50_FILED_Pos          (20UL)                    /*!< OV50_FILED (Bit 20)                                   */
#define eDIAG_STS_OV50_FILED_Msk          (0x100000UL)              /*!< OV50_FILED (Bitfield-Mask: 0x01)                      */
#define eDIAG_STS_UV50_FILED_Pos          (19UL)                    /*!< UV50_FILED (Bit 19)                                   */
#define eDIAG_STS_UV50_FILED_Msk          (0x80000UL)               /*!< UV50_FILED (Bitfield-Mask: 0x01)                      */
#define eDIAG_STS_OV15_FILED_Pos          (18UL)                    /*!< OV15_FILED (Bit 18)                                   */
#define eDIAG_STS_OV15_FILED_Msk          (0x40000UL)               /*!< OV15_FILED (Bitfield-Mask: 0x01)                      */
#define eDIAG_STS_UV15_FILED_Pos          (17UL)                    /*!< UV15_FILED (Bit 17)                                   */
#define eDIAG_STS_UV15_FILED_Msk          (0x20000UL)               /*!< UV15_FILED (Bitfield-Mask: 0x01)                      */
#define eDIAG_STS_LEVEL1_FILED_Pos        (16UL)                    /*!< LEVEL1_FILED (Bit 16)                                 */
#define eDIAG_STS_LEVEL1_FILED_Msk        (0x10000UL)               /*!< LEVEL1_FILED (Bitfield-Mask: 0x01)                    */
#define eDIAG_STS_LEVEL0_FILED_Pos        (15UL)                    /*!< LEVEL0_FILED (Bit 15)                                 */
#define eDIAG_STS_LEVEL0_FILED_Msk        (0x8000UL)                /*!< LEVEL0_FILED (Bitfield-Mask: 0x01)                    */
#define eDIAG_STS_OCD1_POS_FILED_Pos      (14UL)                    /*!< OCD1_POS_FILED (Bit 14)                               */
#define eDIAG_STS_OCD1_POS_FILED_Msk      (0x4000UL)                /*!< OCD1_POS_FILED (Bitfield-Mask: 0x01)                  */
#define eDIAG_STS_OCD1_NEG_FILED_Pos      (13UL)                    /*!< OCD1_NEG_FILED (Bit 13)                               */
#define eDIAG_STS_OCD1_NEG_FILED_Msk      (0x2000UL)                /*!< OCD1_NEG_FILED (Bitfield-Mask: 0x01)                  */
#define eDIAG_STS_OCD0_POS_FILED_Pos      (12UL)                    /*!< OCD0_POS_FILED (Bit 12)                               */
#define eDIAG_STS_OCD0_POS_FILED_Msk      (0x1000UL)                /*!< OCD0_POS_FILED (Bitfield-Mask: 0x01)                  */
#define eDIAG_STS_OCD0_NEG_FILED_Pos      (11UL)                    /*!< OCD0_NEG_FILED (Bit 11)                               */
#define eDIAG_STS_OCD0_NEG_FILED_Msk      (0x800UL)                 /*!< OCD0_NEG_FILED (Bitfield-Mask: 0x01)                  */
#define eDIAG_STS_U_OUT_Pos               (4UL)                     /*!< U_OUT (Bit 4)                                         */
#define eDIAG_STS_U_OUT_Msk               (0x10UL)                  /*!< U_OUT (Bitfield-Mask: 0x01)                           */
#define eDIAG_STS_V_OUT_Pos               (3UL)                     /*!< V_OUT (Bit 3)                                         */
#define eDIAG_STS_V_OUT_Msk               (0x8UL)                   /*!< V_OUT (Bitfield-Mask: 0x01)                           */
#define eDIAG_STS_W_OUT_Pos               (2UL)                     /*!< W_OUT (Bit 2)                                         */
#define eDIAG_STS_W_OUT_Msk               (0x4UL)                   /*!< W_OUT (Bitfield-Mask: 0x01)                           */
#define eDIAG_STS_OUT_VALID_Pos           (1UL)                     /*!< OUT_VALID (Bit 1)                                     */
#define eDIAG_STS_OUT_VALID_Msk           (0x2UL)                   /*!< OUT_VALID (Bitfield-Mask: 0x01)                       */
#define eDIAG_STS_OUT_SYNC_Pos            (0UL)                     /*!< OUT_SYNC (Bit 0)                                      */
#define eDIAG_STS_OUT_SYNC_Msk            (0x1UL)                   /*!< OUT_SYNC (Bitfield-Mask: 0x01)                        */
/* ==========================================================  CR  =========================================================== */
#define eDIAG_CR_SPEED_Pos                (22UL)                    /*!< SPEED (Bit 22)                                        */
#define eDIAG_CR_SPEED_Msk                (0x400000UL)              /*!< SPEED (Bitfield-Mask: 0x01)                           */
#define eDIAG_CR_OFFSET_Pos               (21UL)                    /*!< OFFSET (Bit 21)                                       */
#define eDIAG_CR_OFFSET_Msk               (0x200000UL)              /*!< OFFSET (Bitfield-Mask: 0x01)                          */
#define eDIAG_CR_HYS_Pos                  (19UL)                    /*!< HYS (Bit 19)                                          */
#define eDIAG_CR_HYS_Msk                  (0x180000UL)              /*!< HYS (Bitfield-Mask: 0x03)                             */
#define eDIAG_CR_LPF_Pos                  (16UL)                    /*!< LPF (Bit 16)                                          */
#define eDIAG_CR_LPF_Msk                  (0x70000UL)               /*!< LPF (Bitfield-Mask: 0x07)                             */
#define eDIAG_CR_PGA1_OCD_TH_Pos          (12UL)                    /*!< PGA1_OCD_TH (Bit 12)                                  */
#define eDIAG_CR_PGA1_OCD_TH_Msk          (0x3000UL)                /*!< PGA1_OCD_TH (Bitfield-Mask: 0x03)                     */
#define eDIAG_CR_PGA0_OCD_TH_Pos          (10UL)                    /*!< PGA0_OCD_TH (Bit 10)                                  */
#define eDIAG_CR_PGA0_OCD_TH_Msk          (0xc00UL)                 /*!< PGA0_OCD_TH (Bitfield-Mask: 0x03)                     */
#define eDIAG_CR_PGA1_OCD_EN_Pos          (9UL)                     /*!< PGA1_OCD_EN (Bit 9)                                   */
#define eDIAG_CR_PGA1_OCD_EN_Msk          (0x200UL)                 /*!< PGA1_OCD_EN (Bitfield-Mask: 0x01)                     */
#define eDIAG_CR_PGA0_OCD_EN_Pos          (8UL)                     /*!< PGA0_OCD_EN (Bit 8)                                   */
#define eDIAG_CR_PGA0_OCD_EN_Msk          (0x100UL)                 /*!< PGA0_OCD_EN (Bitfield-Mask: 0x01)                     */
#define eDIAG_CR_OTSEL_Pos                (6UL)                     /*!< OTSEL (Bit 6)                                         */
#define eDIAG_CR_OTSEL_Msk                (0xc0UL)                  /*!< OTSEL (Bitfield-Mask: 0x03)                           */
#define eDIAG_CR_OTEN_Pos                 (5UL)                     /*!< OTEN (Bit 5)                                          */
#define eDIAG_CR_OTEN_Msk                 (0x20UL)                  /*!< OTEN (Bitfield-Mask: 0x01)                            */
#define eDIAG_CR_EDGESEL_Pos              (3UL)                     /*!< EDGESEL (Bit 3)                                       */
#define eDIAG_CR_EDGESEL_Msk              (0x18UL)                  /*!< EDGESEL (Bitfield-Mask: 0x03)                         */
#define eDIAG_CR_OUTSEL_Pos               (2UL)                     /*!< OUTSEL (Bit 2)                                        */
#define eDIAG_CR_OUTSEL_Msk               (0x4UL)                   /*!< OUTSEL (Bitfield-Mask: 0x01)                          */
#define eDIAG_CR_MODE_Pos                 (1UL)                     /*!< MODE (Bit 1)                                          */
#define eDIAG_CR_MODE_Msk                 (0x2UL)                   /*!< MODE (Bitfield-Mask: 0x01)                            */
#define eDIAG_CR_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define eDIAG_CR_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CR1  ========================================================== */
#define eDIAG_CR1_BRKIO_POL_Pos           (22UL)                    /*!< BRKIO_POL (Bit 22)                                    */
#define eDIAG_CR1_BRKIO_POL_Msk           (0x400000UL)              /*!< BRKIO_POL (Bitfield-Mask: 0x01)                       */
#define eDIAG_CR1_LEVEL1_POL_Pos          (21UL)                    /*!< LEVEL1_POL (Bit 21)                                   */
#define eDIAG_CR1_LEVEL1_POL_Msk          (0x200000UL)              /*!< LEVEL1_POL (Bitfield-Mask: 0x01)                      */
#define eDIAG_CR1_LEVEL0_POL_Pos          (20UL)                    /*!< LEVEL0_POL (Bit 20)                                   */
#define eDIAG_CR1_LEVEL0_POL_Msk          (0x100000UL)              /*!< LEVEL0_POL (Bitfield-Mask: 0x01)                      */
#define eDIAG_CR1_BRK_IO_EN_Pos           (12UL)                    /*!< BRK_IO_EN (Bit 12)                                    */
#define eDIAG_CR1_BRK_IO_EN_Msk           (0x1000UL)                /*!< BRK_IO_EN (Bitfield-Mask: 0x01)                       */
#define eDIAG_CR1_ADC_OTP_EN_Pos          (11UL)                    /*!< ADC_OTP_EN (Bit 11)                                   */
#define eDIAG_CR1_ADC_OTP_EN_Msk          (0x800UL)                 /*!< ADC_OTP_EN (Bitfield-Mask: 0x01)                      */
#define eDIAG_CR1_OTP_EN_Pos              (10UL)                    /*!< OTP_EN (Bit 10)                                       */
#define eDIAG_CR1_OTP_EN_Msk              (0x400UL)                 /*!< OTP_EN (Bitfield-Mask: 0x01)                          */
#define eDIAG_CR1_OV50_EN_Pos             (9UL)                     /*!< OV50_EN (Bit 9)                                       */
#define eDIAG_CR1_OV50_EN_Msk             (0x200UL)                 /*!< OV50_EN (Bitfield-Mask: 0x01)                         */
#define eDIAG_CR1_UV50_EN_Pos             (8UL)                     /*!< UV50_EN (Bit 8)                                       */
#define eDIAG_CR1_UV50_EN_Msk             (0x100UL)                 /*!< UV50_EN (Bitfield-Mask: 0x01)                         */
#define eDIAG_CR1_OV15_EN_Pos             (7UL)                     /*!< OV15_EN (Bit 7)                                       */
#define eDIAG_CR1_OV15_EN_Msk             (0x80UL)                  /*!< OV15_EN (Bitfield-Mask: 0x01)                         */
#define eDIAG_CR1_UV15_EN_Pos             (6UL)                     /*!< UV15_EN (Bit 6)                                       */
#define eDIAG_CR1_UV15_EN_Msk             (0x40UL)                  /*!< UV15_EN (Bitfield-Mask: 0x01)                         */
#define eDIAG_CR1_LEVEL1_EN_Pos           (5UL)                     /*!< LEVEL1_EN (Bit 5)                                     */
#define eDIAG_CR1_LEVEL1_EN_Msk           (0x20UL)                  /*!< LEVEL1_EN (Bitfield-Mask: 0x01)                       */
#define eDIAG_CR1_LEVEL0_EN_Pos           (4UL)                     /*!< LEVEL0_EN (Bit 4)                                     */
#define eDIAG_CR1_LEVEL0_EN_Msk           (0x10UL)                  /*!< LEVEL0_EN (Bitfield-Mask: 0x01)                       */
#define eDIAG_CR1_OCD1_POS_EN_Pos         (3UL)                     /*!< OCD1_POS_EN (Bit 3)                                   */
#define eDIAG_CR1_OCD1_POS_EN_Msk         (0x8UL)                   /*!< OCD1_POS_EN (Bitfield-Mask: 0x01)                     */
#define eDIAG_CR1_OCD1_NEG_EN_Pos         (2UL)                     /*!< OCD1_NEG_EN (Bit 2)                                   */
#define eDIAG_CR1_OCD1_NEG_EN_Msk         (0x4UL)                   /*!< OCD1_NEG_EN (Bitfield-Mask: 0x01)                     */
#define eDIAG_CR1_OCD0_POS_EN_Pos         (1UL)                     /*!< OCD0_POS_EN (Bit 1)                                   */
#define eDIAG_CR1_OCD0_POS_EN_Msk         (0x2UL)                   /*!< OCD0_POS_EN (Bitfield-Mask: 0x01)                     */
#define eDIAG_CR1_OCD0_NEG_EN_Pos         (0UL)                     /*!< OCD0_NEG_EN (Bit 0)                                   */
#define eDIAG_CR1_OCD0_NEG_EN_Msk         (0x1UL)                   /*!< OCD0_NEG_EN (Bitfield-Mask: 0x01)                     */
/* ==========================================================  MUX  ========================================================== */
#define eDIAG_MUX_PHSEL_Pos               (0UL)                     /*!< PHSEL (Bit 0)                                         */
#define eDIAG_MUX_PHSEL_Msk               (0x3UL)                   /*!< PHSEL (Bitfield-Mask: 0x03)                           */
/* ==========================================================  IER  ========================================================== */
#define eDIAG_IER_OCD1_POSE_Pos           (6UL)                     /*!< OCD1_POSE (Bit 6)                                     */
#define eDIAG_IER_OCD1_POSE_Msk           (0x40UL)                  /*!< OCD1_POSE (Bitfield-Mask: 0x01)                       */
#define eDIAG_IER_OCD1_NEGE_Pos           (5UL)                     /*!< OCD1_NEGE (Bit 5)                                     */
#define eDIAG_IER_OCD1_NEGE_Msk           (0x20UL)                  /*!< OCD1_NEGE (Bitfield-Mask: 0x01)                       */
#define eDIAG_IER_OCD0_POSE_Pos           (4UL)                     /*!< OCD0_POSE (Bit 4)                                     */
#define eDIAG_IER_OCD0_POSE_Msk           (0x10UL)                  /*!< OCD0_POSE (Bitfield-Mask: 0x01)                       */
#define eDIAG_IER_OCD0_NEGE_Pos           (3UL)                     /*!< OCD0_NEGE (Bit 3)                                     */
#define eDIAG_IER_OCD0_NEGE_Msk           (0x8UL)                   /*!< OCD0_NEGE (Bitfield-Mask: 0x01)                       */
#define eDIAG_IER_LEVE1E_Pos              (2UL)                     /*!< LEVE1E (Bit 2)                                        */
#define eDIAG_IER_LEVE1E_Msk              (0x4UL)                   /*!< LEVE1E (Bitfield-Mask: 0x01)                          */
#define eDIAG_IER_LEVE0E_Pos              (1UL)                     /*!< LEVE0E (Bit 1)                                        */
#define eDIAG_IER_LEVE0E_Msk              (0x2UL)                   /*!< LEVE0E (Bitfield-Mask: 0x01)                          */
#define eDIAG_IER_IE_Pos                  (0UL)                     /*!< IE (Bit 0)                                            */
#define eDIAG_IER_IE_Msk                  (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* ==========================================================  SR  =========================================================== */
#define eDIAG_SR_OCD1_POSF_Pos            (7UL)                     /*!< OCD1_POSF (Bit 7)                                     */
#define eDIAG_SR_OCD1_POSF_Msk            (0x80UL)                  /*!< OCD1_POSF (Bitfield-Mask: 0x01)                       */
#define eDIAG_SR_OCD1_NEGF_Pos            (6UL)                     /*!< OCD1_NEGF (Bit 6)                                     */
#define eDIAG_SR_OCD1_NEGF_Msk            (0x40UL)                  /*!< OCD1_NEGF (Bitfield-Mask: 0x01)                       */
#define eDIAG_SR_OCD0_POSF_Pos            (5UL)                     /*!< OCD0_POSF (Bit 5)                                     */
#define eDIAG_SR_OCD0_POSF_Msk            (0x20UL)                  /*!< OCD0_POSF (Bitfield-Mask: 0x01)                       */
#define eDIAG_SR_OCD0_NEGF_Pos            (4UL)                     /*!< OCD0_NEGF (Bit 4)                                     */
#define eDIAG_SR_OCD0_NEGF_Msk            (0x10UL)                  /*!< OCD0_NEGF (Bitfield-Mask: 0x01)                       */
#define eDIAG_SR_LEVF1F_Pos               (3UL)                     /*!< LEVF1F (Bit 3)                                        */
#define eDIAG_SR_LEVF1F_Msk               (0x8UL)                   /*!< LEVF1F (Bitfield-Mask: 0x01)                          */
#define eDIAG_SR_LEVF0F_Pos               (2UL)                     /*!< LEVF0F (Bit 2)                                        */
#define eDIAG_SR_LEVF0F_Msk               (0x4UL)                   /*!< LEVF0F (Bitfield-Mask: 0x01)                          */
#define eDIAG_SR_NF_Pos                   (1UL)                     /*!< NF (Bit 1)                                            */
#define eDIAG_SR_NF_Msk                   (0x2UL)                   /*!< NF (Bitfield-Mask: 0x01)                              */
#define eDIAG_SR_PF_Pos                   (0UL)                     /*!< PF (Bit 0)                                            */
#define eDIAG_SR_PF_Msk                   (0x1UL)                   /*!< PF (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CLR  ========================================================== */
#define eDIAG_CLR_OCD1_POSCLR_Pos         (7UL)                     /*!< OCD1_POSCLR (Bit 7)                                   */
#define eDIAG_CLR_OCD1_POSCLR_Msk         (0x80UL)                  /*!< OCD1_POSCLR (Bitfield-Mask: 0x01)                     */
#define eDIAG_CLR_OCD1_NEGCLR_Pos         (6UL)                     /*!< OCD1_NEGCLR (Bit 6)                                   */
#define eDIAG_CLR_OCD1_NEGCLR_Msk         (0x40UL)                  /*!< OCD1_NEGCLR (Bitfield-Mask: 0x01)                     */
#define eDIAG_CLR_OCD0_POSCLR_Pos         (5UL)                     /*!< OCD0_POSCLR (Bit 5)                                   */
#define eDIAG_CLR_OCD0_POSCLR_Msk         (0x20UL)                  /*!< OCD0_POSCLR (Bitfield-Mask: 0x01)                     */
#define eDIAG_CLR_OCD0_NEGCLR_Pos         (4UL)                     /*!< OCD0_NEGCLR (Bit 4)                                   */
#define eDIAG_CLR_OCD0_NEGCLR_Msk         (0x10UL)                  /*!< OCD0_NEGCLR (Bitfield-Mask: 0x01)                     */
#define eDIAG_CLR_LEVF1CLR_Pos            (3UL)                     /*!< LEVF1CLR (Bit 3)                                      */
#define eDIAG_CLR_LEVF1CLR_Msk            (0x8UL)                   /*!< LEVF1CLR (Bitfield-Mask: 0x01)                        */
#define eDIAG_CLR_LEVF0CLR_Pos            (2UL)                     /*!< LEVF0CLR (Bit 2)                                      */
#define eDIAG_CLR_LEVF0CLR_Msk            (0x4UL)                   /*!< LEVF0CLR (Bitfield-Mask: 0x01)                        */
#define eDIAG_CLR_NFCLR_Pos               (1UL)                     /*!< NFCLR (Bit 1)                                         */
#define eDIAG_CLR_NFCLR_Msk               (0x2UL)                   /*!< NFCLR (Bitfield-Mask: 0x01)                           */
#define eDIAG_CLR_PFCLR_Pos               (0UL)                     /*!< PFCLR (Bit 0)                                         */
#define eDIAG_CLR_PFCLR_Msk               (0x1UL)                   /*!< PFCLR (Bitfield-Mask: 0x01)                           */
/* =========================================================  FILT  ========================================================== */
#define eDIAG_FILT_FLTTH_Pos              (15UL)                    /*!< FLTTH (Bit 15)                                        */
#define eDIAG_FILT_FLTTH_Msk              (0xf8000UL)               /*!< FLTTH (Bitfield-Mask: 0x1f)                           */
#define eDIAG_FILT_FLTWIN_Pos             (10UL)                    /*!< FLTWIN (Bit 10)                                       */
#define eDIAG_FILT_FLTWIN_Msk             (0x7c00UL)                /*!< FLTWIN (Bitfield-Mask: 0x1f)                          */
#define eDIAG_FILT_FLTDIV_Pos             (0UL)                     /*!< FLTDIV (Bit 0)                                        */
#define eDIAG_FILT_FLTDIV_Msk             (0x3ffUL)                 /*!< FLTDIV (Bitfield-Mask: 0x3ff)                         */
/* =======================================================  FILT_DIA  ======================================================== */
#define eDIAG_FILT_DIA_BRK_FILT_SEL_Pos   (27UL)                    /*!< BRK_FILT_SEL (Bit 27)                                 */
#define eDIAG_FILT_DIA_BRK_FILT_SEL_Msk   (0x38000000UL)            /*!< BRK_FILT_SEL (Bitfield-Mask: 0x07)                    */
#define eDIAG_FILT_DIA_OTP_FILT_SEL_Pos   (24UL)                    /*!< OTP_FILT_SEL (Bit 24)                                 */
#define eDIAG_FILT_DIA_OTP_FILT_SEL_Msk   (0x7000000UL)             /*!< OTP_FILT_SEL (Bitfield-Mask: 0x07)                    */
#define eDIAG_FILT_DIA_OV50_FILT_SEL_Pos  (21UL)                    /*!< OV50_FILT_SEL (Bit 21)                                */
#define eDIAG_FILT_DIA_OV50_FILT_SEL_Msk  (0xe00000UL)              /*!< OV50_FILT_SEL (Bitfield-Mask: 0x07)                   */
#define eDIAG_FILT_DIA_UV50_FILT_SEL_Pos  (18UL)                    /*!< UV50_FILT_SEL (Bit 18)                                */
#define eDIAG_FILT_DIA_UV50_FILT_SEL_Msk  (0x1c0000UL)              /*!< UV50_FILT_SEL (Bitfield-Mask: 0x07)                   */
#define eDIAG_FILT_DIA_OV15_FILT_SEL_Pos  (15UL)                    /*!< OV15_FILT_SEL (Bit 15)                                */
#define eDIAG_FILT_DIA_OV15_FILT_SEL_Msk  (0x38000UL)               /*!< OV15_FILT_SEL (Bitfield-Mask: 0x07)                   */
#define eDIAG_FILT_DIA_UV15_FILT_SEL_Pos  (12UL)                    /*!< UV15_FILT_SEL (Bit 12)                                */
#define eDIAG_FILT_DIA_UV15_FILT_SEL_Msk  (0x7000UL)                /*!< UV15_FILT_SEL (Bitfield-Mask: 0x07)                   */
#define eDIAG_FILT_DIA_LEVEL1_FILT_SEL_Pos (9UL)                    /*!< LEVEL1_FILT_SEL (Bit 9)                               */
#define eDIAG_FILT_DIA_LEVEL1_FILT_SEL_Msk (0xe00UL)                /*!< LEVEL1_FILT_SEL (Bitfield-Mask: 0x07)                 */
#define eDIAG_FILT_DIA_LEVEL0_FILT_SEL_Pos (6UL)                    /*!< LEVEL0_FILT_SEL (Bit 6)                               */
#define eDIAG_FILT_DIA_LEVEL0_FILT_SEL_Msk (0x1c0UL)                /*!< LEVEL0_FILT_SEL (Bitfield-Mask: 0x07)                 */
#define eDIAG_FILT_DIA_OCD_POS_FILT_SEL_Pos (3UL)                   /*!< OCD_POS_FILT_SEL (Bit 3)                              */
#define eDIAG_FILT_DIA_OCD_POS_FILT_SEL_Msk (0x38UL)                /*!< OCD_POS_FILT_SEL (Bitfield-Mask: 0x07)                */
#define eDIAG_FILT_DIA_OCD_NEG_FILT_SEL_Pos (0UL)                   /*!< OCD_NEG_FILT_SEL (Bit 0)                              */
#define eDIAG_FILT_DIA_OCD_NEG_FILT_SEL_Msk (0x7UL)                 /*!< OCD_NEG_FILT_SEL (Bitfield-Mask: 0x07)                */


/* =========================================================================================================================== */
/* ================                                            ADC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR0  ========================================================== */
#define ADC_CR0_PGA_SPD_Pos               (13UL)                    /*!< PGA_SPD (Bit 13)                                      */
#define ADC_CR0_PGA_SPD_Msk               (0x6000UL)                /*!< PGA_SPD (Bitfield-Mask: 0x03)                         */
#define ADC_CR0_TRIG_SEL_Pos              (12UL)                    /*!< TRIG_SEL (Bit 12)                                     */
#define ADC_CR0_TRIG_SEL_Msk              (0x1000UL)                /*!< TRIG_SEL (Bitfield-Mask: 0x01)                        */
#define ADC_CR0_SW_TRIG_Pos               (8UL)                     /*!< SW_TRIG (Bit 8)                                       */
#define ADC_CR0_SW_TRIG_Msk               (0x100UL)                 /*!< SW_TRIG (Bitfield-Mask: 0x01)                         */
#define ADC_CR0_SEQLENGTH_Pos             (4UL)                     /*!< SEQLENGTH (Bit 4)                                     */
#define ADC_CR0_SEQLENGTH_Msk             (0x70UL)                  /*!< SEQLENGTH (Bitfield-Mask: 0x07)                       */
#define ADC_CR0_PGAEN_Pos                 (3UL)                     /*!< PGAEN (Bit 3)                                         */
#define ADC_CR0_PGAEN_Msk                 (0x8UL)                   /*!< PGAEN (Bitfield-Mask: 0x01)                           */
#define ADC_CR0_CONT_Pos                  (2UL)                     /*!< CONT (Bit 2)                                          */
#define ADC_CR0_CONT_Msk                  (0x4UL)                   /*!< CONT (Bitfield-Mask: 0x01)                            */
#define ADC_CR0_DMAEN_Pos                 (1UL)                     /*!< DMAEN (Bit 1)                                         */
#define ADC_CR0_DMAEN_Msk                 (0x2UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
#define ADC_CR0_ADEN_Pos                  (0UL)                     /*!< ADEN (Bit 0)                                          */
#define ADC_CR0_ADEN_Msk                  (0x1UL)                   /*!< ADEN (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CR1  ========================================================== */
#define ADC_CR1_TACTIVE_Pos               (8UL)                     /*!< TACTIVE (Bit 8)                                       */
#define ADC_CR1_TACTIVE_Msk               (0xfff00UL)               /*!< TACTIVE (Bitfield-Mask: 0xfff)                        */
/* ==========================================================  OTP  ========================================================== */
#define ADC_OTP_TEMPMAX_Pos               (16UL)                    /*!< TEMPMAX (Bit 16)                                      */
#define ADC_OTP_TEMPMAX_Msk               (0x1fff0000UL)            /*!< TEMPMAX (Bitfield-Mask: 0x1fff)                       */
#define ADC_OTP_OTPEN_Pos                 (0UL)                     /*!< OTPEN (Bit 0)                                         */
#define ADC_OTP_OTPEN_Msk                 (0x1UL)                   /*!< OTPEN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  SR  =========================================================== */
#define ADC_SR_EOT_Pos                    (4UL)                     /*!< EOT (Bit 4)                                           */
#define ADC_SR_EOT_Msk                    (0x10UL)                  /*!< EOT (Bitfield-Mask: 0x01)                             */
#define ADC_SR_ADCRDY_Pos                 (3UL)                     /*!< ADCRDY (Bit 3)                                        */
#define ADC_SR_ADCRDY_Msk                 (0x8UL)                   /*!< ADCRDY (Bitfield-Mask: 0x01)                          */
#define ADC_SR_OTP_Pos                    (2UL)                     /*!< OTP (Bit 2)                                           */
#define ADC_SR_OTP_Msk                    (0x4UL)                   /*!< OTP (Bitfield-Mask: 0x01)                             */
#define ADC_SR_TRIGERR_Pos                (1UL)                     /*!< TRIGERR (Bit 1)                                       */
#define ADC_SR_TRIGERR_Msk                (0x2UL)                   /*!< TRIGERR (Bitfield-Mask: 0x01)                         */
#define ADC_SR_EOC_Pos                    (0UL)                     /*!< EOC (Bit 0)                                           */
#define ADC_SR_EOC_Msk                    (0x1UL)                   /*!< EOC (Bitfield-Mask: 0x01)                             */
/* ==========================================================  IER  ========================================================== */
#define ADC_IER_OTPIE_Pos                 (2UL)                     /*!< OTPIE (Bit 2)                                         */
#define ADC_IER_OTPIE_Msk                 (0x4UL)                   /*!< OTPIE (Bitfield-Mask: 0x01)                           */
#define ADC_IER_TRIGERRIE_Pos             (1UL)                     /*!< TRIGERRIE (Bit 1)                                     */
#define ADC_IER_TRIGERRIE_Msk             (0x2UL)                   /*!< TRIGERRIE (Bitfield-Mask: 0x01)                       */
#define ADC_IER_EOCIE_Pos                 (0UL)                     /*!< EOCIE (Bit 0)                                         */
#define ADC_IER_EOCIE_Msk                 (0x1UL)                   /*!< EOCIE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  CIR  ========================================================== */
#define ADC_CIR_EOTCLR_Pos                (4UL)                     /*!< EOTCLR (Bit 4)                                        */
#define ADC_CIR_EOTCLR_Msk                (0x10UL)                  /*!< EOTCLR (Bitfield-Mask: 0x01)                          */
#define ADC_CIR_OTPCLR_Pos                (2UL)                     /*!< OTPCLR (Bit 2)                                        */
#define ADC_CIR_OTPCLR_Msk                (0x4UL)                   /*!< OTPCLR (Bitfield-Mask: 0x01)                          */
#define ADC_CIR_TRIGERRCLR_Pos            (1UL)                     /*!< TRIGERRCLR (Bit 1)                                    */
#define ADC_CIR_TRIGERRCLR_Msk            (0x2UL)                   /*!< TRIGERRCLR (Bitfield-Mask: 0x01)                      */
#define ADC_CIR_EOCCLR_Pos                (0UL)                     /*!< EOCCLR (Bit 0)                                        */
#define ADC_CIR_EOCCLR_Msk                (0x1UL)                   /*!< EOCCLR (Bitfield-Mask: 0x01)                          */
/* =========================================================  CHCFG  ========================================================= */
#define ADC_CHCFG_TSAMP_Pos               (22UL)                    /*!< TSAMP (Bit 22)                                        */
#define ADC_CHCFG_TSAMP_Msk               (0xffc00000UL)            /*!< TSAMP (Bitfield-Mask: 0x3ff)                          */
#define ADC_CHCFG_TRIGDELAY_Pos           (12UL)                    /*!< TRIGDELAY (Bit 12)                                    */
#define ADC_CHCFG_TRIGDELAY_Msk           (0x3ff000UL)              /*!< TRIGDELAY (Bitfield-Mask: 0x3ff)                      */
#define ADC_CHCFG_PGASEL_Pos              (10UL)                    /*!< PGASEL (Bit 10)                                       */
#define ADC_CHCFG_PGASEL_Msk              (0xc00UL)                 /*!< PGASEL (Bitfield-Mask: 0x03)                          */
#define ADC_CHCFG_PGAGAIN_Pos             (7UL)                     /*!< PGAGAIN (Bit 7)                                       */
#define ADC_CHCFG_PGAGAIN_Msk             (0x380UL)                 /*!< PGAGAIN (Bitfield-Mask: 0x07)                         */
#define ADC_CHCFG_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_CHCFG_CHSEL_Msk               (0x1fUL)                  /*!< CHSEL (Bitfield-Mask: 0x1f)                           */
/* =========================================================  DATA  ========================================================== */
#define ADC_DATA_DISP_CHSEL_Pos           (16UL)                    /*!< DISP_CHSEL (Bit 16)                                   */
#define ADC_DATA_DISP_CHSEL_Msk           (0x1f0000UL)              /*!< DISP_CHSEL (Bitfield-Mask: 0x1f)                      */
#define ADC_DATA_ADC_DATA_Pos             (0UL)                     /*!< ADC_DATA (Bit 0)                                      */
#define ADC_DATA_ADC_DATA_Msk             (0x1fffUL)                /*!< ADC_DATA (Bitfield-Mask: 0x1fff)                      */
/* =========================================================  TDATA  ========================================================= */
#define ADC_TDATA_DISP_CHSEL_Pos          (16UL)                    /*!< DISP_CHSEL (Bit 16)                                   */
#define ADC_TDATA_DISP_CHSEL_Msk          (0x1f0000UL)              /*!< DISP_CHSEL (Bitfield-Mask: 0x1f)                      */
#define ADC_TDATA_ADC_DATA_Pos            (0UL)                     /*!< ADC_DATA (Bit 0)                                      */
#define ADC_TDATA_ADC_DATA_Msk            (0x1fffUL)                /*!< ADC_DATA (Bitfield-Mask: 0x1fff)                      */
/* =========================================================  TEST  ========================================================== */
#define ADC_TEST_DIG_PGA_DEBUG_OUT_Pos    (31UL)                    /*!< DIG_PGA_DEBUG_OUT (Bit 31)                            */
#define ADC_TEST_DIG_PGA_DEBUG_OUT_Msk    (0x80000000UL)            /*!< DIG_PGA_DEBUG_OUT (Bitfield-Mask: 0x01)               */
#define ADC_TEST_DIG_PGA_DEBUG_IN_Pos     (28UL)                    /*!< DIG_PGA_DEBUG_IN (Bit 28)                             */
#define ADC_TEST_DIG_PGA_DEBUG_IN_Msk     (0x70000000UL)            /*!< DIG_PGA_DEBUG_IN (Bitfield-Mask: 0x07)                */
#define ADC_TEST_ANA_PGA_DEBUG_IN_Pos     (24UL)                    /*!< ANA_PGA_DEBUG_IN (Bit 24)                             */
#define ADC_TEST_ANA_PGA_DEBUG_IN_Msk     (0x7000000UL)             /*!< ANA_PGA_DEBUG_IN (Bitfield-Mask: 0x07)                */
#define ADC_TEST_DEBUG_DATA_Pos           (21UL)                    /*!< DEBUG_DATA (Bit 21)                                   */
#define ADC_TEST_DEBUG_DATA_Msk           (0x200000UL)              /*!< DEBUG_DATA (Bitfield-Mask: 0x01)                      */
#define ADC_TEST_DIG_ADC_DEBUG_OUT_Pos    (19UL)                    /*!< DIG_ADC_DEBUG_OUT (Bit 19)                            */
#define ADC_TEST_DIG_ADC_DEBUG_OUT_Msk    (0x80000UL)               /*!< DIG_ADC_DEBUG_OUT (Bitfield-Mask: 0x01)               */
#define ADC_TEST_DIG_ADC_DEBUG_IN_Pos     (16UL)                    /*!< DIG_ADC_DEBUG_IN (Bit 16)                             */
#define ADC_TEST_DIG_ADC_DEBUG_IN_Msk     (0x70000UL)               /*!< DIG_ADC_DEBUG_IN (Bitfield-Mask: 0x07)                */
#define ADC_TEST_ANA_ADC_DEBUG_IN_Pos     (12UL)                    /*!< ANA_ADC_DEBUG_IN (Bit 12)                             */
#define ADC_TEST_ANA_ADC_DEBUG_IN_Msk     (0x7000UL)                /*!< ANA_ADC_DEBUG_IN (Bitfield-Mask: 0x07)                */
#define ADC_TEST_CNT_VALID_Pos            (8UL)                     /*!< CNT_VALID (Bit 8)                                     */
#define ADC_TEST_CNT_VALID_Msk            (0x100UL)                 /*!< CNT_VALID (Bitfield-Mask: 0x01)                       */
#define ADC_TEST_SEQ_CTRL_FSM_Pos         (4UL)                     /*!< SEQ_CTRL_FSM (Bit 4)                                  */
#define ADC_TEST_SEQ_CTRL_FSM_Msk         (0x70UL)                  /*!< SEQ_CTRL_FSM (Bitfield-Mask: 0x07)                    */
#define ADC_TEST_ANA_CTRL_FSM_Pos         (0UL)                     /*!< ANA_CTRL_FSM (Bit 0)                                  */
#define ADC_TEST_ANA_CTRL_FSM_Msk         (0x7UL)                   /*!< ANA_CTRL_FSM (Bitfield-Mask: 0x07)                    */

/** @} */ /* End of group PosMask_peripherals */


/* =========================================================================================================================== */
/* ================                           Enumerated Values Peripheral Section                            ================ */
/* =========================================================================================================================== */


/** @addtogroup EnumValue_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                           FMC0                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
/* =============================================  FMC0 CR PRESCALER_CFG [0..2]  ============================================== */
typedef enum {                                  /*!< FMC0_CR_PRESCALER_CFG                                                     */
  Prescaler_Level0                     = 0,     /*!< Level0 : if system clock frequncy is less than 4 MHz                      */
  Prescaler_Level1                     = 1,     /*!< Level1 : if system clock frequncy is less than 8 MHz but greater
                                                                    than 4 MHz                                                 */
  Prescaler_Level2                     = 2,     /*!< Level2 : if system clock frequncy is less than 16 MHz but greater
                                                     than 8 MHz                                                                */
  Prescaler_Level3                     = 3,     /*!< Level3 : if system clock frequncy is less than 32 MHz but greater
                                                     than 16 MHz                                                               */
} Prescaler_Enum;

/* ==========================================================  SR0  ========================================================== */
/* ================================================  FMC0 SR0 ECC_ERR [4..5]  ================================================ */
typedef enum {                                  /*!< FMC0_SR0_ECC_ERR                                                          */
  ECC_ErrType_NoErr                    = 0,     /*!< NoErr : No Error                                                          */
  ECC_ErrType_SingleErr                = 1,     /*!< SingleErr : A 1-bit ECC error occurred                                    */
  ECC_ErrType_MultiBitErr              = 2,     /*!< MultiBitErr : More than 1-bit ECC error occurred                          */
} ECC_ErrType_Enum;

/* ==========================================================  SR1  ========================================================== */
/* ==========================================================  CMD  ========================================================== */
/* ==================================================  FMC0 CMD CMD [0..2]  ================================================== */
typedef enum {                                  /*!< FMC0_CMD_CMD                                                              */
  RJ_FlashCMD_Read                     = 1,     /*!< Read : Read                                                               */
  RJ_FlashCMD_Program                  = 2,     /*!< Program : Program                                                         */
  RJ_FlashCMD_EraseSector              = 3,     /*!< EraseSector : Erase Sector                                                */
  RJ_FlashCMD_EraseChip                = 4,     /*!< EraseChip : Erase Chip                                                    */
} RJ_FlashCMD_Enum;

/* ========================================================  CMD_EXE  ======================================================== */
/* =========================================================  BYTES  ========================================================= */
/* =========================================================  ADDR  ========================================================== */
/* =========================================================  DATA0  ========================================================= */
/* =========================================================  DATA1  ========================================================= */
/* =========================================================  DATA2  ========================================================= */
/* =========================================================  INIT  ========================================================== */
/* ==========================================================  IER  ========================================================== */
/* ==========================================================  CLR  ========================================================== */
/* ========================================================  PARAM0  ========================================================= */
/* ========================================================  PARAM1  ========================================================= */
/* =========================================================  TRIM0  ========================================================= */
/* =========================================================  TRIM1  ========================================================= */
/* =========================================================  TRIM2  ========================================================= */
/* =========================================================  FTST  ========================================================== */
/* =======================================================  TRIM_KEY  ======================================================== */
/* =======================================================  PARAM_KEY  ======================================================= */
/* ========================================================  ECC_INL  ======================================================== */
/* ========================================================  ECC_INM  ======================================================== */
/* ========================================================  ECC_INH  ======================================================== */


/* =========================================================================================================================== */
/* ================                                           GPIOA                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  MODER  ========================================================= */
/* ================================================  GPIOA MODER MODE [0..1]  ================================================ */
typedef enum {                                  /*!< GPIOA_MODER_MODE                                                          */
  GPIO_Mode_INPUT                      = 0,     /*!< INPUT : Input mode                                                        */
  GPIO_Mode_OUTPUT                     = 1,     /*!< OUTPUT : Output mode                                                      */
  GPIO_Mode_ALTENATE                   = 2,     /*!< ALTENATE : Altenate mode                                                  */
  GPIO_Mode_ANALOG                     = 3,     /*!< ANALOG : Analog mode                                                      */
} GPIO_Mode_Enum;

/* ========================================================  OTYPER  ========================================================= */
/* ================================================  GPIOA OTYPER OT [0..0]  ================================================= */
typedef enum {                                  /*!< GPIOA_OTYPER_OT                                                           */
  GPIO_OutputType_PP                   = 0,     /*!< PP : push pull output type                                                */
  GPIO_OutputType_OD                   = 1,     /*!< OD : Open drain output type                                               */
} GPIO_OutputType_Enum;

/* ==========================================================  STR  ========================================================== */
/* =================================================  GPIOA STR STR [0..0]  ================================================== */
typedef enum {                                  /*!< GPIOA_STR_STR                                                             */
  GPIO_Strength_OHM67                  = 0,     /*!< OHM67 : OHM67                                                             */
  GPIO_Strength_OHM57                  = 1,     /*!< OHM57 : OHM57                                                             */
} GPIO_Strength_Enum;

/* =========================================================  SLEWR  ========================================================= */
/* ================================================  GPIOA SLEWR RATE [0..0]  ================================================ */
typedef enum {                                  /*!< GPIOA_SLEWR_RATE                                                          */
  GPIO_SlewRate_NS4                    = 0,     /*!< NS4 : NS4                                                                 */
  GPIO_SlewRate_NS5                    = 1,     /*!< NS5 : NS5                                                                 */
} GPIO_SlewRate_Enum;

/* =========================================================  PUPDR  ========================================================= */
/* ================================================  GPIOA PUPDR PUPD [0..1]  ================================================ */
typedef enum {                                  /*!< GPIOA_PUPDR_PUPD                                                          */
  GPIO_PullMode_NONE                   = 0,     /*!< NONE : None pull                                                          */
  GPIO_PullMode_Up                     = 1,     /*!< Up : Pull up                                                              */
  GPIO_PullMode_DO                     = 2,     /*!< DO : Pull down                                                            */
} GPIO_PullMode_Enum;

/* ==========================================================  IDR  ========================================================== */
/* ==========================================================  ODR  ========================================================== */
/* =========================================================  AFLR  ========================================================== */
/* =========================================================  AFHR  ========================================================== */
/* ========================================================  EDGIER  ========================================================= */
/* ===============================================  GPIOA EDGIER EDGIE [0..1]  =============================================== */
typedef enum {                                  /*!< GPIOA_EDGIER_EDGIE                                                        */
  GPIO_EdegIntMode_None                = 0,     /*!< None : None                                                               */
  GPIO_EdegIntMode_OnRiseEdge          = 1,     /*!< OnRiseEdge : Enable edge interrupt on rise edge only.                     */
  GPIO_EdegIntMode_OnFallEdge          = 2,     /*!< OnFallEdge : Enable edge interrupt on fall edge only.                     */
  GPIO_EdegIntMode_OnBothEdge          = 3,     /*!< OnBothEdge : Enable edge interrupt on both rise and fall edge
                                                     only.                                                                     */
} GPIO_EdegIntMode_Enum;

/* ========================================================  EDGISR  ========================================================= */
/* ==============================================  GPIOA EDGISR EDGISR [0..1]  =============================================== */
typedef enum {                                  /*!< GPIOA_EDGISR_EDGISR                                                       */
  GPIO_EdegIntStatus_None              = 0,     /*!< None : No edge interrupt flag                                             */
  GPIO_EdegIntStatus_RiseEdge          = 1,     /*!< RiseEdge : Rise edge interrupt flag                                       */
  GPIO_EdegIntStatus_FallEdge          = 2,     /*!< FallEdge : Fall edge interrupt flag                                       */
  GPIO_EdegIntStatus_BothEdge          = 3,     /*!< BothEdge : Rise and fall edge interrupt flag                              */
} GPIO_EdegIntStatus_Enum;

/* ========================================================  EDGICLR  ======================================================== */
/* =============================================  GPIOA EDGICLR EDGICLR [0..1]  ============================================== */
typedef enum {                                  /*!< GPIOA_EDGICLR_EDGICLR                                                     */
  GPIO_EdgeIntClear_None               = 0,     /*!< None : None                                                               */
  GPIO_EdgeIntClear_RiseEdge           = 1,     /*!< RiseEdge : Clear rise edge interrupt status                               */
  GPIO_EdgeIntClear_FallEdge           = 2,     /*!< FallEdge : Clear fall edge interrupt status                               */
  GPIO_EdgeIntClear_BothEdge           = 3,     /*!< BothEdge : Clear rise/fall edge interrupt status                          */
} GPIO_EdgeIntClear_Enum;

/* ========================================================  LEVIER  ========================================================= */
/* ===============================================  GPIOA LEVIER LEVIE [0..1]  =============================================== */
typedef enum {                                  /*!< GPIOA_LEVIER_LEVIE                                                        */
  GPIO_LevelIntMode_Disable            = 0,     /*!< Disable : Level interrupt disable                                         */
  GPIO_LevelIntMode_HighLevel          = 1,     /*!< HighLevel : High level interrupt enable                                   */
  GPIO_LevelIntMode_LowLevel           = 2,     /*!< LowLevel : Low level interrupt enable                                     */
  GPIO_LevelIntMode_Reserve            = 3,     /*!< Reserve : Reserve                                                         */
} GPIO_LevelIntMode_Enum;

/* ========================================================  LEVISR  ========================================================= */
/* ==============================================  GPIOA LEVISR LEVISR [0..1]  =============================================== */
typedef enum {                                  /*!< GPIOA_LEVISR_LEVISR                                                       */
  GPIO_LevelIntStatus_None             = 0,     /*!< None : None                                                               */
  GPIO_LevelIntStatus_HighLevel        = 1,     /*!< HighLevel : High level interrupt status                                   */
  GPIO_LevelIntStatus_LowLevel         = 2,     /*!< LowLevel : Low level interrupt status                                     */
  GPIO_LevelIntStatus_Reserve          = 3,     /*!< Reserve : Reserve                                                         */
} GPIO_LevelIntStatus_Enum;

/* ========================================================  LEVICLR  ======================================================== */
/* =============================================  GPIOA LEVICLR LEVICLR [0..1]  ============================================== */
typedef enum {                                  /*!< GPIOA_LEVICLR_LEVICLR                                                     */
  GPIO_LevelIntClear_None              = 0,     /*!< None : None                                                               */
  GPIO_LevelIntClear_HighLevel         = 1,     /*!< HighLevel : High level interrupt status clear                             */
  GPIO_LevelIntClear_LowLevel          = 2,     /*!< LowLevel : Low level interrupt status clear                               */
  GPIO_LevelIntClear_Reserve           = 3,     /*!< Reserve : Reserve                                                         */
} GPIO_LevelIntClear_Enum;



/* =========================================================================================================================== */
/* ================                                           SPI0                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  CTRLR0  ========================================================= */
/* ==============================================  SPI0 CTRLR0 DFS_32 [16..20]  ============================================== */
typedef enum {                                  /*!< SPI0_CTRLR0_DFS_32                                                        */
  SPI_DataFrameSize_04_BITS            = 3,     /*!< 04_BITS : 4-bit serial data transfer                                      */
  SPI_DataFrameSize_05_BITS            = 4,     /*!< 05_BITS : 5-bit serial data transfer                                      */
  SPI_DataFrameSize_06_BITS            = 5,     /*!< 06_BITS : 6-bit serial data transfer                                      */
  SPI_DataFrameSize_07_BITS            = 6,     /*!< 07_BITS : 7-bit serial data transfer                                      */
  SPI_DataFrameSize_08_BITS            = 7,     /*!< 08_BITS : 8-bit serial data transfer                                      */
  SPI_DataFrameSize_09_BITS            = 8,     /*!< 09_BITS : 9-bit serial data transfer                                      */
  SPI_DataFrameSize_10_BITS            = 9,     /*!< 10_BITS : 10-bit serial data transfer                                     */
  SPI_DataFrameSize_11_BITS            = 10,    /*!< 11_BITS : 11-bit serial data transfer                                     */
  SPI_DataFrameSize_12_BITS            = 11,    /*!< 12_BITS : 12-bit serial data transfer                                     */
  SPI_DataFrameSize_13_BITS            = 12,    /*!< 13_BITS : 13-bit serial data transfer                                     */
  SPI_DataFrameSize_14_BITS            = 13,    /*!< 14_BITS : 14-bit serial data transfer                                     */
  SPI_DataFrameSize_15_BITS            = 14,    /*!< 15_BITS : 15-bit serial data transfer                                     */
  SPI_DataFrameSize_16_BITS            = 15,    /*!< 16_BITS : 16-bit serial data transfer                                     */
  SPI_DataFrameSize_17_BITS            = 16,    /*!< 17_BITS : 17-bit serial data transfer                                     */
  SPI_DataFrameSize_18_BITS            = 17,    /*!< 18_BITS : 18-bit serial data transfer                                     */
  SPI_DataFrameSize_19_BITS            = 18,    /*!< 19_BITS : 19-bit serial data transfer                                     */
  SPI_DataFrameSize_20_BITS            = 19,    /*!< 20_BITS : 20-bit serial data transfer                                     */
  SPI_DataFrameSize_21_BITS            = 20,    /*!< 21_BITS : 21-bit serial data transfer                                     */
  SPI_DataFrameSize_22_BITS            = 21,    /*!< 22_BITS : 22-bit serial data transfer                                     */
  SPI_DataFrameSize_23_BITS            = 22,    /*!< 23_BITS : 23-bit serial data transfer                                     */
  SPI_DataFrameSize_24_BITS            = 23,    /*!< 24_BITS : 24-bit serial data transfer                                     */
  SPI_DataFrameSize_25_BITS            = 24,    /*!< 25_BITS : 25-bit serial data transfer                                     */
  SPI_DataFrameSize_26_BITS            = 25,    /*!< 26_BITS : 26-bit serial data transfer                                     */
  SPI_DataFrameSize_27_BITS            = 26,    /*!< 27_BITS : 27-bit serial data transfer                                     */
  SPI_DataFrameSize_28_BITS            = 27,    /*!< 28_BITS : 28-bit serial data transfer                                     */
  SPI_DataFrameSize_29_BITS            = 28,    /*!< 29_BITS : 29-bit serial data transfer                                     */
  SPI_DataFrameSize_30_BITS            = 29,    /*!< 30_BITS : 30-bit serial data transfer                                     */
  SPI_DataFrameSize_31_BITS            = 30,    /*!< 31_BITS : 31-bit serial data transfer                                     */
  SPI_DataFrameSize_32_BITS            = 31,    /*!< 32_BITS : 32-bit serial data transfer                                     */
} SPI_DataFrameSize_Enum;

/* ===============================================  SPI0 CTRLR0 CFS [12..15]  ================================================ */
typedef enum {                                  /*!< SPI0_CTRLR0_CFS                                                           */
  SPI_ControlFrameSize_01_BIT          = 0,     /*!< 01_BIT : 1-bit Control Word                                               */
  SPI_ControlFrameSize_02_BIT          = 1,     /*!< 02_BIT : 2-bit Control Word                                               */
  SPI_ControlFrameSize_03_BIT          = 2,     /*!< 03_BIT : 3-bit Control Word                                               */
  SPI_ControlFrameSize_04_BIT          = 3,     /*!< 04_BIT : 4-bit Control Word                                               */
  SPI_ControlFrameSize_05_BIT          = 4,     /*!< 05_BIT : 5-bit Control Word                                               */
  SPI_ControlFrameSize_06_BIT          = 5,     /*!< 06_BIT : 6-bit Control Word                                               */
  SPI_ControlFrameSize_07_BIT          = 6,     /*!< 07_BIT : 7-bit Control Word                                               */
  SPI_ControlFrameSize_08_BIT          = 7,     /*!< 08_BIT : 8-bit Control Word                                               */
  SPI_ControlFrameSize_09_BIT          = 8,     /*!< 09_BIT : 9-bit Control Word                                               */
  SPI_ControlFrameSize_10_BIT          = 9,     /*!< 10_BIT : 10-bit Control Word                                              */
  SPI_ControlFrameSize_11_BIT          = 10,    /*!< 11_BIT : 11-bit Control Word                                              */
  SPI_ControlFrameSize_12_BIT          = 11,    /*!< 12_BIT : 12-bit Control Word                                              */
  SPI_ControlFrameSize_13_BIT          = 12,    /*!< 13_BIT : 13-bit Control Word                                              */
  SPI_ControlFrameSize_14_BIT          = 13,    /*!< 14_BIT : 14-bit Control Word                                              */
  SPI_ControlFrameSize_15_BIT          = 14,    /*!< 15_BIT : 15-bit Control Word                                              */
  SPI_ControlFrameSize_16_BIT          = 15,    /*!< 16_BIT : 16-bit Control Word                                              */
} SPI_ControlFrameSize_Enum;

/* ================================================  SPI0 CTRLR0 TMOD [8..9]  ================================================ */
typedef enum {                                  /*!< SPI0_CTRLR0_TMOD                                                          */
  SPI_TransferMode_TX_AND_RX           = 0,     /*!< TX_AND_RX : Transmit and receive                                          */
  SPI_TransferMode_TX_ONLY             = 1,     /*!< TX_ONLY : Transmit only mode or Write                                     */
  SPI_TransferMode_RX_ONLY             = 2,     /*!< RX_ONLY : Receive only mode or Read                                       */
  SPI_TransferMode_EEPROM_READ         = 3,     /*!< EEPROM_READ : EEPROM Read mode                                            */
} SPI_TransferMode_Enum;

/* ===============================================  SPI0 CTRLR0 SCPOL [7..7]  ================================================ */
typedef enum {                                  /*!< SPI0_CTRLR0_SCPOL                                                         */
  SPI_CPOL_Low                         = 0,     /*!< Low : Inactive state of serial clock is low                               */
  SPI_CPOL_High                        = 1,     /*!< High : Inactive state of serial clock is high                             */
} SPI_CPOL_Enum;

/* ================================================  SPI0 CTRLR0 SCPH [6..6]  ================================================ */
typedef enum {                                  /*!< SPI0_CTRLR0_SCPH                                                          */
  SPI_CPHA_1Edge                       = 0,     /*!< 1Edge : Data are captured on the first edge of theserial clock            */
  SPI_CPHA_2Edge                       = 1,     /*!< 2Edge : Data are captured on the second edge of theserial clock           */
} SPI_CPHA_Enum;

/* ================================================  SPI0 CTRLR0 FRF [4..5]  ================================================= */
typedef enum {                                  /*!< SPI0_CTRLR0_FRF                                                           */
  SPI_FrameFormat_MOTOROLA_SPI         = 0,     /*!< MOTOROLA_SPI : Motorolla SPI Frame Format                                 */
  SPI_FrameFormat_TEXAS_SSP            = 1,     /*!< TEXAS_SSP : Texas Instruments SSP Frame Format                            */
  SPI_FrameFormat_NS_MICROWIRE         = 2,     /*!< NS_MICROWIRE : National Microwire Frame Format                            */
} SPI_FrameFormat_Enum;

/* ========================================================  CTRLR1  ========================================================= */
/* ========================================================  SSIENR  ========================================================= */
/* =========================================================  MWCR  ========================================================== */
/* ==========================================================  SER  ========================================================== */
/* =========================================================  BAUDR  ========================================================= */
/* ========================================================  TXFTLR  ========================================================= */
/* ========================================================  RXFTLR  ========================================================= */
/* =========================================================  TXFLR  ========================================================= */
/* =========================================================  RXFLR  ========================================================= */
/* ==========================================================  SR  =========================================================== */
/* ==========================================================  IMR  ========================================================== */
/* ==========================================================  ISR  ========================================================== */
/* =========================================================  RISR  ========================================================== */
/* ========================================================  TXOICR  ========================================================= */
/* ========================================================  RXOICR  ========================================================= */
/* ========================================================  RXUICR  ========================================================= */
/* ========================================================  MSTICR  ========================================================= */
/* ==========================================================  ICR  ========================================================== */
/* =========================================================  DMACR  ========================================================= */
/* ========================================================  DMATDLR  ======================================================== */
/* ========================================================  DMARDLR  ======================================================== */
/* ==========================================================  IDR  ========================================================== */
/* ====================================================  SSI_VERSION_ID  ===================================================== */
/* ==========================================================  DR  =========================================================== */
/* =====================================================  RX_SAMPLE_DLY  ===================================================== */
/* ====================================================  TXD_DRIVE_EDGE  ===================================================== */


/* =========================================================================================================================== */
/* ================                                           ePWM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
/* ==============================================  ePWM CR1 CMP5TRGCF [20..21]  ============================================== */
typedef enum {                                  /*!< ePWM_CR1_CMP5TRGCF                                                        */
  ePWM_CR1_CMP5TRGCF_DOWN              = 1,     /*!< DOWN : Trig is generated when counting down                               */
  ePWM_CR1_CMP5TRGCF_UP                = 2,     /*!< UP : Trig is generated when counting up                                   */
} ePWM_CR1_CMP5TRGCF_Enum;

/* ==============================================  ePWM CR1 CMP4TRGCF [18..19]  ============================================== */
typedef enum {                                  /*!< ePWM_CR1_CMP4TRGCF                                                        */
  ePWM_CR1_CMP4TRGCF_DOWN              = 1,     /*!< DOWN : Trig is generated when counting down                               */
  ePWM_CR1_CMP4TRGCF_UP                = 2,     /*!< UP : Trig is generated when counting up                                   */
} ePWM_CR1_CMP4TRGCF_Enum;

/* ==============================================  ePWM CR1 CMP3TRGCF [16..17]  ============================================== */
typedef enum {                                  /*!< ePWM_CR1_CMP3TRGCF                                                        */
  ePWM_CR1_CMP3TRGCF_DOWN              = 1,     /*!< DOWN : Trig is generated when counting down                               */
  ePWM_CR1_CMP3TRGCF_UP                = 2,     /*!< UP : Trig is generated when counting up                                   */
} ePWM_CR1_CMP3TRGCF_Enum;

/* ==============================================  ePWM CR1 CMP2TRGCF [14..15]  ============================================== */
typedef enum {                                  /*!< ePWM_CR1_CMP2TRGCF                                                        */
  ePWM_CR1_CMP2TRGCF_DOWN              = 1,     /*!< DOWN : Trig is generated when counting down                               */
  ePWM_CR1_CMP2TRGCF_UP                = 2,     /*!< UP : Trig is generated when counting up                                   */
} ePWM_CR1_CMP2TRGCF_Enum;

/* ==============================================  ePWM CR1 CMP1TRGCF [12..13]  ============================================== */
typedef enum {                                  /*!< ePWM_CR1_CMP1TRGCF                                                        */
  ePWM_CR1_CMP1TRGCF_DOWN              = 1,     /*!< DOWN : Trig is generated when counting down                               */
  ePWM_CR1_CMP1TRGCF_UP                = 2,     /*!< UP : Trig is generated when counting up                                   */
} ePWM_CR1_CMP1TRGCF_Enum;

/* ==============================================  ePWM CR1 CMP0TRGCF [10..11]  ============================================== */
typedef enum {                                  /*!< ePWM_CR1_CMP0TRGCF                                                        */
  ePWM_CR1_CMP0TRGCF_DOWN              = 1,     /*!< DOWN : Trig is generated when counting down                               */
  ePWM_CR1_CMP0TRGCF_UP                = 2,     /*!< UP : Trig is generated when counting up                                   */
} ePWM_CR1_CMP0TRGCF_Enum;

/* ==========================================================  CR2  ========================================================== */
/* =========================================================  SMCR  ========================================================== */
/* =========================================================  DIER  ========================================================== */
/* ==========================================================  SR  =========================================================== */
/* ==========================================================  EGR  ========================================================== */
/* =========================================================  CCMR1  ========================================================= */
/* =========================================================  CCMR2  ========================================================= */
/* =========================================================  CCER  ========================================================== */
/* ==========================================================  CNT  ========================================================== */
/* ==========================================================  PSC  ========================================================== */
/* ==========================================================  ARR  ========================================================== */
/* =========================================================  CCR1  ========================================================== */
/* =========================================================  CCR2  ========================================================== */
/* =========================================================  CCR3  ========================================================== */
/* =========================================================  CCR4  ========================================================== */
/* ==========================================================  DCR  ========================================================== */
/* =========================================================  DMAR  ========================================================== */
/* ==========================================================  RCR  ========================================================== */
/* =========================================================  BDTR  ========================================================== */
/* =========================================================  CMP01  ========================================================= */
/* =========================================================  CMP23  ========================================================= */
/* =========================================================  CMP45  ========================================================= */


/* =========================================================================================================================== */
/* ================                                          SYSCFG                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  CHIPID  ========================================================= */
/* ==========================================================  RDP  ========================================================== */
/* ========================================================  RAM0IER  ======================================================== */
/* ========================================================  RAM0ISR  ======================================================== */
/* =======================================================  RAM0ICLR  ======================================================== */
/* =======================================================  RAM0SYND  ======================================================== */
/* =======================================================  RAM0INJL  ======================================================== */
/* =======================================================  RAM0INJH  ======================================================== */
/* ========================================================  RAM1IER  ======================================================== */
/* ========================================================  RAM1ISR  ======================================================== */
/* =======================================================  RAM1ICLR  ======================================================== */
/* =======================================================  RAM1SYND  ======================================================== */
/* =======================================================  RAM1INJL  ======================================================== */
/* =======================================================  RAM1INJH  ======================================================== */
/* ========================================================  ADC0TRG  ======================================================== */
/* ========================================================  ADC1TRG  ======================================================== */
/* ========================================================  TIM0TRG  ======================================================== */
/* ========================================================  TIM1TRG  ======================================================== */
/* ========================================================  TIM2TRG  ======================================================== */
/* =========================================================  TRGO0  ========================================================= */
/* =========================================================  TRGO1  ========================================================= */
/* =========================================================  DBGEN  ========================================================= */
/* ========================================================  DBGLOCK  ======================================================== */
/* ========================================================  DBGMODE  ======================================================== */
/* =========================================================  DFTEN  ========================================================= */
/* ========================================================  DFTLOCK  ======================================================== */
/* ========================================================  DFTMODE  ======================================================== */
/* ========================================================  OSCHENR  ======================================================== */
/* ======================================================  OSCHENLOCKR  ====================================================== */
/* ========================================================  REMAPR  ========================================================= */


/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  ISR  ========================================================== */
/* =========================================================  IFCR  ========================================================== */
/* =========================================================  CCR1  ========================================================== */
/* ========================================================  CNDTR1  ========================================================= */
/* =========================================================  CPAR1  ========================================================= */
/* =========================================================  CMAR1  ========================================================= */
/* =========================================================  CCR2  ========================================================== */
/* ========================================================  CNDTR2  ========================================================= */
/* =========================================================  CPAR2  ========================================================= */
/* =========================================================  CMAR2  ========================================================= */
/* =========================================================  CCR3  ========================================================== */
/* ========================================================  CNDTR3  ========================================================= */
/* =========================================================  CPAR3  ========================================================= */
/* =========================================================  CMAR3  ========================================================= */
/* =========================================================  CCR4  ========================================================== */
/* ========================================================  CNDTR4  ========================================================= */
/* =========================================================  CPAR4  ========================================================= */
/* =========================================================  CMAR4  ========================================================= */
/* =========================================================  CCR5  ========================================================== */
/* ========================================================  CNDTR5  ========================================================= */
/* =========================================================  CPAR5  ========================================================= */
/* =========================================================  CMAR5  ========================================================= */
/* =========================================================  CCR6  ========================================================== */
/* ========================================================  CNDTR6  ========================================================= */
/* =========================================================  CPAR6  ========================================================= */
/* =========================================================  CMAR6  ========================================================= */
/* =========================================================  CCR7  ========================================================== */
/* ========================================================  CNDTR7  ========================================================= */
/* =========================================================  CPAR7  ========================================================= */
/* =========================================================  CMAR7  ========================================================= */


/* =========================================================================================================================== */
/* ================                                           eCAP                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
/* ==========================================================  CR2  ========================================================== */
/* =========================================================  SMCR  ========================================================== */
/* =========================================================  DIER  ========================================================== */
/* ==========================================================  SR  =========================================================== */
/* ==========================================================  EGR  ========================================================== */
/* =========================================================  CCMR1  ========================================================= */
/* =========================================================  CCMR2  ========================================================= */
/* =========================================================  CCER  ========================================================== */
/* ==========================================================  CNT  ========================================================== */
/* ==========================================================  PSC  ========================================================== */
/* ==========================================================  ARR  ========================================================== */
/* =========================================================  CCR1  ========================================================== */
/* =========================================================  CCR2  ========================================================== */
/* =========================================================  CCR3  ========================================================== */
/* =========================================================  CCR4  ========================================================== */


/* =========================================================================================================================== */
/* ================                                           TIM0                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
/* ==========================================================  CNT  ========================================================== */
/* ==========================================================  IER  ========================================================== */
/* ==========================================================  SR  =========================================================== */
/* ==========================================================  CLR  ========================================================== */
/* ==========================================================  PRD  ========================================================== */


/* =========================================================================================================================== */
/* ================                                           WWDG                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
/* ==========================================================  CFR  ========================================================== */
/* =================================================  WWDG CFR WDGTB [7..8]  ================================================= */
typedef enum {                                  /*!< WWDG_CFR_WDGTB                                                            */
  WWDG_CFR_WDGTB_Div1                  = 0,     /*!< Div1 : Div1                                                               */
  WWDG_CFR_WDGTB_Div2                  = 1,     /*!< Div2 : Div2                                                               */
  WWDG_CFR_WDGTB_Div4                  = 2,     /*!< Div4 : Div4                                                               */
  WWDG_CFR_WDGTB_Div8                  = 3,     /*!< Div8 : Div8                                                               */
} WWDG_CFR_WDGTB_Enum;

/* ==========================================================  SR  =========================================================== */


/* =========================================================================================================================== */
/* ================                                           IWDG                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  KR  =========================================================== */
/* ==========================================================  PR  =========================================================== */
/* ==========================================================  RLR  ========================================================== */
/* ==========================================================  SR  =========================================================== */


/* =========================================================================================================================== */
/* ================                                            LIN                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  LINCR1  ========================================================= */
/* ===============================================  LIN LINCR1 NLSE [16..16]  ================================================ */
typedef enum {                                  /*!< LIN_LINCR1_NLSE                                                           */
  LIN_LINCR1_NLSE_DIS                  = 0,     /*!< DIS : LINSR.LINS shows the current LIN state and does not capture
                                                     the LIN state on bit error.                                               */
  LIN_LINCR1_NLSE_EN                   = 1,     /*!< EN : LINSR.LINS is captured when a bit error flag occurs.                 */
} LIN_LINCR1_NLSE_Enum;

/* ================================================  LIN LINCR1 CCD [15..15]  ================================================ */
typedef enum {                                  /*!< LIN_LINCR1_CCD                                                            */
  LIN_LINCR1_CCD_DIS                   = 0,     /*!< DIS : Checksum calculation is done by hardware. The LINCFR register
                                                     is read-only.                                                             */
  LIN_LINCR1_CCD_EN                    = 1,     /*!< EN : Checksum calculation is disabled. The LINCFR register is
                                                     read/write. If the checksum field is enabled (CFD = 0),
                                                     LINCFR can be programmed to send a software-calculated
                                                     checksum/CRC.                                                             */
} LIN_LINCR1_CCD_Enum;

/* ================================================  LIN LINCR1 CFD [14..14]  ================================================ */
typedef enum {                                  /*!< LIN_LINCR1_CFD                                                            */
  LIN_LINCR1_CFD_DIS                   = 0,     /*!< DIS : Checksum field is sent after the required number of data
                                                     bytes are sent.                                                           */
  LIN_LINCR1_CFD_EN                    = 1,     /*!< EN : No checksum field is sent in the frame.                              */
} LIN_LINCR1_CFD_Enum;

/* ===============================================  LIN LINCR1 LASE [13..13]  ================================================ */
typedef enum {                                  /*!< LIN_LINCR1_LASE                                                           */
  LIN_LINCR1_LASE_DIS                  = 0,     /*!< DIS : Disable autosynchronization.                                        */
  LIN_LINCR1_LASE_EN                   = 1,     /*!< EN : Enable autosynchronization.                                          */
} LIN_LINCR1_LASE_Enum;

/* ==============================================  LIN LINCR1 AUTOWU [12..12]  =============================================== */
typedef enum {                                  /*!< LIN_LINCR1_AUTOWU                                                         */
  LIN_LINCR1_AUTOWU_DIS                = 0,     /*!< DIS : The SLEEP bit is cleared by software only.                          */
  LIN_LINCR1_AUTOWU_EN                 = 1,     /*!< EN : The SLEEP bit is cleared by hardware whenever the LINSR.WUF
                                                     bit is set.                                                               */
} LIN_LINCR1_AUTOWU_Enum;

/* ================================================  LIN LINCR1 MBL [8..11]  ================================================= */
typedef enum {                                  /*!< LIN_LINCR1_MBL                                                            */
  LIN_LINCR1_MBL_B10                   = 0,     /*!< B10 : 10-bit break length                                                 */
  LIN_LINCR1_MBL_B11                   = 1,     /*!< B11 : 11-bit break length                                                 */
  LIN_LINCR1_MBL_B12                   = 2,     /*!< B12 : 12-bit break length                                                 */
  LIN_LINCR1_MBL_B13                   = 3,     /*!< B13 : 13-bit break length                                                 */
  LIN_LINCR1_MBL_B14                   = 4,     /*!< B14 : 14-bit break length                                                 */
  LIN_LINCR1_MBL_B15                   = 5,     /*!< B15 : 15-bit break length                                                 */
  LIN_LINCR1_MBL_B16                   = 6,     /*!< B16 : 16-bit break length                                                 */
  LIN_LINCR1_MBL_B17                   = 7,     /*!< B17 : 17-bit break length                                                 */
  LIN_LINCR1_MBL_B18                   = 8,     /*!< B18 : 18-bit break length                                                 */
  LIN_LINCR1_MBL_B19                   = 9,     /*!< B19 : 19-bit break length                                                 */
  LIN_LINCR1_MBL_B20                   = 10,    /*!< B20 : 20-bit break length                                                 */
  LIN_LINCR1_MBL_B21                   = 11,    /*!< B21 : 21-bit break length                                                 */
  LIN_LINCR1_MBL_B22                   = 12,    /*!< B22 : 22-bit break length                                                 */
  LIN_LINCR1_MBL_B23                   = 13,    /*!< B23 : 23-bit break length                                                 */
  LIN_LINCR1_MBL_B36                   = 14,    /*!< B36 : 36-bit break length                                                 */
  LIN_LINCR1_MBL_B50                   = 15,    /*!< B50 : 50-bit break length                                                 */
} LIN_LINCR1_MBL_Enum;

/* =================================================  LIN LINCR1 BF [7..7]  ================================================== */
typedef enum {                                  /*!< LIN_LINCR1_BF                                                             */
  LIN_LINCR1_BF_DIS                    = 0,     /*!< DIS : Receiver ignores incoming frame if ID does not match any
                                                     ID filter or if no ID filters are active.                                 */
  LIN_LINCR1_BF_EN                     = 1,     /*!< EN : If no ID filters are active, receiver responds to incoming
                                                     frames. If ID filters are active, receiver responds if
                                                     frame is received but does not match any filter.                          */
} LIN_LINCR1_BF_Enum;

/* ================================================  LIN LINCR1 LBKM [5..5]  ================================================= */
typedef enum {                                  /*!< LIN_LINCR1_LBKM                                                           */
  LIN_LINCR1_LBKM_DIS                  = 0,     /*!< DIS : Disable Loop Back mode.                                             */
  LIN_LINCR1_LBKM_EN                   = 1,     /*!< EN : Enable Loop Back mode.                                               */
} LIN_LINCR1_LBKM_Enum;

/* =================================================  LIN LINCR1 MME [4..4]  ================================================= */
typedef enum {                                  /*!< LIN_LINCR1_MME                                                            */
  LIN_LINCR1_MME_SLAVE                 = 0,     /*!< SLAVE : Slave mode.                                                       */
  LIN_LINCR1_MME_MASTER                = 1,     /*!< MASTER : Master mode.                                                     */
} LIN_LINCR1_MME_Enum;

/* ================================================  LIN LINCR1 SSBL [3..3]  ================================================= */
typedef enum {                                  /*!< LIN_LINCR1_SSBL                                                           */
  LIN_LINCR1_SSBL_B11                  = 0,     /*!< B11 : 11-bit break length.                                                */
  LIN_LINCR1_SSBL_B10                  = 1,     /*!< B10 : 10-bit break length.                                                */
} LIN_LINCR1_SSBL_Enum;

/* ================================================  LIN LINCR1 RBLM [2..2]  ================================================= */
typedef enum {                                  /*!< LIN_LINCR1_RBLM                                                           */
  LIN_LINCR1_RBLM_DIS                  = 0,     /*!< DIS : Receiver is buffer is not locked. The next incoming message
                                                     overwrites the previous one.                                              */
  LIN_LINCR1_RBLM_EN                   = 1,     /*!< EN : Receiver buffer is locked against overrun. Once the buffer
                                                     is full, the next incoming message is discarded if the
                                                     buffer is not released by software clearing the LINSR.RMB
                                                     bit.                                                                      */
} LIN_LINCR1_RBLM_Enum;

/* ========================================================  LINIER  ========================================================= */
/* ===============================================  LIN LINIER SZIE [15..15]  ================================================ */
typedef enum {                                  /*!< LIN_LINIER_SZIE                                                           */
  LIN_LINIER_SZIE_DIS                  = 0,     /*!< DIS : Interrupt disabled.                                                 */
  LIN_LINIER_SZIE_EN                   = 1,     /*!< EN : Interrupt enabled. An interrupt is generated when the Stuck
                                                     at Zero Flag (SZF) is set in LINESR or UARTSR.                            */
} LIN_LINIER_SZIE_Enum;

/* ===============================================  LIN LINIER OCIE [14..14]  ================================================ */
typedef enum {                                  /*!< LIN_LINIER_OCIE                                                           */
  LIN_LINIER_OCIE_DIS                  = 0,     /*!< DIS : Interrupt disabled.                                                 */
  LIN_LINIER_OCIE_EN                   = 1,     /*!< EN : Interrupt enabled. An interrupt is generated when the Output
                                                     Compare Flag (OCF) is set in LINESR or UARTSR.                            */
} LIN_LINIER_OCIE_Enum;

/* ===============================================  LIN LINIER BEIE [13..13]  ================================================ */
typedef enum {                                  /*!< LIN_LINIER_BEIE                                                           */
  LIN_LINIER_BEIE_DIS                  = 0,     /*!< DIS : Interrupt disabled.                                                 */
  LIN_LINIER_BEIE_EN                   = 1,     /*!< EN : Interrupt enabled. An interrupt is generated when the Bit
                                                     Error Flag (BEF) is set in LINESR.                                        */
} LIN_LINIER_BEIE_Enum;

/* ===============================================  LIN LINIER CEIE [12..12]  ================================================ */
typedef enum {                                  /*!< LIN_LINIER_CEIE                                                           */
  LIN_LINIER_CEIE_DIS                  = 0,     /*!< DIS : Interrupt disabled.                                                 */
  LIN_LINIER_CEIE_EN                   = 1,     /*!< EN : Interrupt enabled. An interrupt is generated when the Checksum
                                                     Error Flag (CEF) is set in LINESR.                                        */
} LIN_LINIER_CEIE_Enum;

/* ===============================================  LIN LINIER HEIE [11..11]  ================================================ */
typedef enum {                                  /*!< LIN_LINIER_HEIE                                                           */
  LIN_LINIER_HEIE_DIS                  = 0,     /*!< DIS : Interrupt disabled.                                                 */
  LIN_LINIER_HEIE_EN                   = 1,     /*!< EN : Interrupt enabled. An interrupt is generated when the any
                                                     of the following flags are set in LINESR: SFEF, SDEF, IDPEF.              */
} LIN_LINIER_HEIE_Enum;

/* ================================================  LIN LINIER FEIE [8..8]  ================================================= */
typedef enum {                                  /*!< LIN_LINIER_FEIE                                                           */
  LIN_LINIER_FEIE_DIS                  = 0,     /*!< DIS : Interrupt disabled.                                                 */
  LIN_LINIER_FEIE_EN                   = 1,     /*!< EN : Interrupt enabled. An interrupt is generated when the Frame
                                                     Error Flag (FEF) is set in LINESR or UARTSR.                              */
} LIN_LINIER_FEIE_Enum;

/* ================================================  LIN LINIER BOIE [7..7]  ================================================= */
typedef enum {                                  /*!< LIN_LINIER_BOIE                                                           */
  LIN_LINIER_BOIE_DIS                  = 0,     /*!< DIS : Interrupt disabled.                                                 */
  LIN_LINIER_BOIE_EN                   = 1,     /*!< EN : Interrupt enabled. An interrupt is generated when the Buffer
                                                     Overrun Flag (BOF) is set in LINESR or UARTSR.                            */
} LIN_LINIER_BOIE_Enum;

/* ================================================  LIN LINIER LSIE [6..6]  ================================================= */
typedef enum {                                  /*!< LIN_LINIER_LSIE                                                           */
  LIN_LINIER_LSIE_DIS                  = 0,     /*!< DIS : Interrupt disabled.                                                 */
  LIN_LINIER_LSIE_EN                   = 1,     /*!< EN : Interrupt enabled. An interrupt generated on entering the
                                                     following states: Sync Del, Sync Field, Identifier Field,
                                                     Checksum.                                                                 */
} LIN_LINIER_LSIE_Enum;

/* ================================================  LIN LINIER WUIE [5..5]  ================================================= */
typedef enum {                                  /*!< LIN_LINIER_WUIE                                                           */
  LIN_LINIER_WUIE_DIS                  = 0,     /*!< DIS : Interrupt disabled.                                                 */
  LIN_LINIER_WUIE_EN                   = 1,     /*!< EN : Interrupt enabled. An interrupt generated when the Wakeup
                                                     Flag (WUF) is set in LINESR or UARTSR.                                    */
} LIN_LINIER_WUIE_Enum;

/* ================================================  LIN LINIER TOIE [3..3]  ================================================= */
typedef enum {                                  /*!< LIN_LINIER_TOIE                                                           */
  LIN_LINIER_TOIE_DIS                  = 0,     /*!< DIS : Interrupt disabled.                                                 */
  LIN_LINIER_TOIE_EN                   = 1,     /*!< EN : Interrupt enabled. An interrupt generated when the LINFlexD
                                                     is in UART mode and the Timeout bit (TO) is set in UARTSR.                */
} LIN_LINIER_TOIE_Enum;

/* ================================================  LIN LINIER DRIE [2..2]  ================================================= */
typedef enum {                                  /*!< LIN_LINIER_DRIE                                                           */
  LIN_LINIER_DRIE_DIS                  = 0,     /*!< DIS : Interrupt disabled.                                                 */
  LIN_LINIER_DRIE_EN                   = 1,     /*!< EN : Interrupt enabled. An interrupt generated when the Data
                                                     Received Flag (DRF) is set in LINESR or UARTSR.                           */
} LIN_LINIER_DRIE_Enum;

/* ================================================  LIN LINIER DTIE [1..1]  ================================================= */
typedef enum {                                  /*!< LIN_LINIER_DTIE                                                           */
  LIN_LINIER_DTIE_DIS                  = 0,     /*!< DIS : Interrupt disabled.                                                 */
  LIN_LINIER_DTIE_EN                   = 1,     /*!< EN : Interrupt enabled. An interrupt generated when the Data
                                                     Transmitted Flag (DTF) is set in LINESR or UARTSR.                        */
} LIN_LINIER_DTIE_Enum;

/* ================================================  LIN LINIER HRIE [0..0]  ================================================= */
typedef enum {                                  /*!< LIN_LINIER_HRIE                                                           */
  LIN_LINIER_HRIE_DIS                  = 0,     /*!< DIS : Interrupt disabled.                                                 */
  LIN_LINIER_HRIE_EN                   = 1,     /*!< EN : Interrupt enabled. An interrupt is generated Header Received
                                                     Flag (HRF) is set in LINSR.                                               */
} LIN_LINIER_HRIE_Enum;

/* =========================================================  LINSR  ========================================================= */
/* ================================================  LIN LINSR RDC [16..18]  ================================================= */
typedef enum {                                  /*!< LIN_LINSR_RDC                                                             */
  LIN_LINSR_RDC_B1                     = 0,     /*!< B1 : 1 byte                                                               */
  LIN_LINSR_RDC_B2                     = 1,     /*!< B2 : 2 bytes                                                              */
  LIN_LINSR_RDC_B3                     = 2,     /*!< B3 : 3 bytes                                                              */
  LIN_LINSR_RDC_B4                     = 3,     /*!< B4 : 4 bytes                                                              */
  LIN_LINSR_RDC_B5                     = 4,     /*!< B5 : 5 bytes                                                              */
  LIN_LINSR_RDC_B6                     = 5,     /*!< B6 : 6 bytes                                                              */
  LIN_LINSR_RDC_B7                     = 6,     /*!< B7 : 7 bytes                                                              */
  LIN_LINSR_RDC_B8                     = 7,     /*!< B8 : 8 bytes                                                              */
} LIN_LINSR_RDC_Enum;

/* =================================================  LIN LINSR RMB [9..9]  ================================================== */
typedef enum {                                  /*!< LIN_LINSR_RMB                                                             */
  LIN_LINSR_RMB_FREE                   = 0,     /*!< FREE : Buffer is free.                                                    */
  LIN_LINSR_RMB_READY                  = 1,     /*!< READY : Buffer data is ready to be read by software. RMB should
                                                     be cleared by software after reading the data received
                                                     in the buffer.                                                            */
} LIN_LINSR_RMB_Enum;

/* ================================================  LIN LINSR RXBUSY [7..7]  ================================================ */
typedef enum {                                  /*!< LIN_LINSR_RXBUSY                                                          */
  LIN_LINSR_RXBUSY_IDLE                = 0,     /*!< IDLE : Receiver is idle.                                                  */
  LIN_LINSR_RXBUSY_BUSY                = 1,     /*!< BUSY : Reception is ongoing.                                              */
} LIN_LINSR_RXBUSY_Enum;

/* ========================================================  LINESR  ========================================================= */
/* ========================================================  UARTCR  ========================================================= */
/* ================================================  LIN UARTCR MIS [31..31]  ================================================ */
typedef enum {                                  /*!< LIN_UARTCR_MIS                                                            */
  LIN_UARTCR_MIS_DIS                   = 0,     /*!< DIS : UARTCTO monitors the number of bits to be received.                 */
  LIN_UARTCR_MIS_EN                    = 1,     /*!< EN : UARTCTO monitors the idle state of the reception line.               */
} LIN_UARTCR_MIS_Enum;

/* ===============================================  LIN UARTCR ROSE [23..23]  ================================================ */
typedef enum {                                  /*!< LIN_UARTCR_ROSE                                                           */
  LIN_UARTCR_ROSE_DIS                  = 0,     /*!< DIS : Each bit is oversampled sixteen times.                              */
  LIN_UARTCR_ROSE_EN                   = 1,     /*!< EN : OSR bits determine the oversampling rate.                            */
} LIN_UARTCR_ROSE_Enum;

/* ================================================  LIN UARTCR DTU [19..19]  ================================================ */
typedef enum {                                  /*!< LIN_UARTCR_DTU                                                            */
  LIN_UARTCR_DTU_EN                    = 0,     /*!< EN : Timeout must be handled by software.                                 */
  LIN_UARTCR_DTU_DIS                   = 1,     /*!< DIS : Timeout in UART mode is disabled after the configured
                                                     number of data frames are received.                                       */
} LIN_UARTCR_DTU_Enum;

/* ===============================================  LIN UARTCR SBUR [17..18]  ================================================ */
typedef enum {                                  /*!< LIN_UARTCR_SBUR                                                           */
  LIN_UARTCR_SBUR_SP1                  = 0,     /*!< SP1 : 1 stop bit                                                          */
  LIN_UARTCR_SBUR_SP2                  = 1,     /*!< SP2 : 2 stop bits                                                         */
  LIN_UARTCR_SBUR_SP3                  = 2,     /*!< SP3 : 3 stop bits                                                         */
} LIN_UARTCR_SBUR_Enum;

/* ================================================  LIN UARTCR WLS [16..16]  ================================================ */
typedef enum {                                  /*!< LIN_UARTCR_WLS                                                            */
  LIN_UARTCR_WLS_DIS                   = 0,     /*!< DIS : Disable 12-bit + parity bit in reception.                           */
  LIN_UARTCR_WLS_EN                    = 1,     /*!< EN : Enable 12-bit + parity bit in reception (UART mode).                 */
} LIN_UARTCR_WLS_Enum;

/* ================================================  LIN UARTCR RFBM [9..9]  ================================================= */
typedef enum {                                  /*!< LIN_UARTCR_RFBM                                                           */
  LIN_UARTCR_RFBM_DIS                  = 0,     /*!< DIS : Rx buffer mode enabled.                                             */
  LIN_UARTCR_RFBM_EN                   = 1,     /*!< EN : Rx FIFO mode enabled.                                                */
} LIN_UARTCR_RFBM_Enum;

/* ================================================  LIN UARTCR TFBM [8..8]  ================================================= */
typedef enum {                                  /*!< LIN_UARTCR_TFBM                                                           */
  LIN_UARTCR_TFBM_MODE_BUF             = 0,     /*!< MODE_BUF : Tx buffer mode enabled.                                        */
  LIN_UARTCR_TFBM_MODE_FIFO            = 1,     /*!< MODE_FIFO : Tx FIFO mode enabled.                                         */
} LIN_UARTCR_TFBM_Enum;

/* ================================================  LIN UARTCR RXEN [5..5]  ================================================= */
typedef enum {                                  /*!< LIN_UARTCR_RXEN                                                           */
  LIN_UARTCR_RXEN_DIS                  = 0,     /*!< DIS : Receiver disabled.                                                  */
  LIN_UARTCR_RXEN_EN                   = 1,     /*!< EN : Receiver enabled.                                                    */
} LIN_UARTCR_RXEN_Enum;

/* ================================================  LIN UARTCR TXEN [4..4]  ================================================= */
typedef enum {                                  /*!< LIN_UARTCR_TXEN                                                           */
  LIN_UARTCR_TXEN_DIS                  = 0,     /*!< DIS : Transmitter disabled.                                               */
  LIN_UARTCR_TXEN_EN                   = 1,     /*!< EN : Transmitter enabled.                                                 */
} LIN_UARTCR_TXEN_Enum;

/* =================================================  LIN UARTCR PCE [2..2]  ================================================= */
typedef enum {                                  /*!< LIN_UARTCR_PCE                                                            */
  LIN_UARTCR_PCE_DIS                   = 0,     /*!< DIS : Parity transmit/check disabled.                                     */
  LIN_UARTCR_PCE_EN                    = 1,     /*!< EN : Parity transmit/check enabled.                                       */
} LIN_UARTCR_PCE_Enum;

/* ================================================  LIN UARTCR UART [0..0]  ================================================= */
typedef enum {                                  /*!< LIN_UARTCR_UART                                                           */
  LIN_UARTCR_UART_MODE_LIN             = 0,     /*!< MODE_LIN : LIN mode                                                       */
  LIN_UARTCR_UART_MODE_UART            = 1,     /*!< MODE_UART : UART mode                                                     */
} LIN_UARTCR_UART_Enum;

/* ========================================================  UARTSR  ========================================================= */
/* ================================================  LIN UARTSR OCF [14..14]  ================================================ */
typedef enum {                                  /*!< LIN_UARTSR_OCF                                                            */
  LIN_UARTSR_OCF_INACTIVE              = 0,     /*!< INACTIVE : No output compare event occurred.                              */
  LIN_UARTSR_OCF_ACTIVE                = 1,     /*!< ACTIVE : The content of the timeout counter matched the content
                                                     of LINOCR.                                                                */
} LIN_UARTSR_OCF_Enum;

/* ================================================  LIN UARTSR PE [10..13]  ================================================= */
typedef enum {                                  /*!< LIN_UARTSR_PE                                                             */
  LIN_UARTSR_PE_INACTIVE               = 0,     /*!< INACTIVE : No parity error detected.                                      */
  LIN_UARTSR_PE_ACTIVE                 = 1,     /*!< ACTIVE : Parity error detected.                                           */
} LIN_UARTSR_PE_Enum;

/* =================================================  LIN UARTSR RMB [9..9]  ================================================= */
typedef enum {                                  /*!< LIN_UARTSR_RMB                                                            */
  LIN_UARTSR_RMB_FREE                  = 0,     /*!< FREE : Buffer is free.                                                    */
  LIN_UARTSR_RMB_RDY                   = 1,     /*!< RDY : Buffer data is ready to be read by software.                        */
} LIN_UARTSR_RMB_Enum;

/* ========================================================  LINTCSR  ======================================================== */
/* ===============================================  LIN LINTCSR MODE [10..10]  =============================================== */
typedef enum {                                  /*!< LIN_LINTCSR_MODE                                                          */
  LIN_LINTCSR_MODE_MODE_LIN            = 0,     /*!< MODE_LIN : LIN mode                                                       */
  LIN_LINTCSR_MODE_MODE_OC             = 1,     /*!< MODE_OC : Output compare mode                                             */
} LIN_LINTCSR_MODE_Enum;

/* ================================================  LIN LINTCSR IOT [9..9]  ================================================= */
typedef enum {                                  /*!< LIN_LINTCSR_IOT                                                           */
  LIN_LINTCSR_IOT_DIS                  = 0,     /*!< DIS : LIN state machine does not reset to Idle on timeout.                */
  LIN_LINTCSR_IOT_EN                   = 1,     /*!< EN : LIN state machine resets to Idle on timeout event.                   */
} LIN_LINTCSR_IOT_Enum;

/* ================================================  LIN LINTCSR TOCE [8..8]  ================================================ */
typedef enum {                                  /*!< LIN_LINTCSR_TOCE                                                          */
  LIN_LINTCSR_TOCE_DIS                 = 0,     /*!< DIS : Timeout counter disabled. UARTSR.OCF flag is not set on
                                                     an output compare event.                                                  */
  LIN_LINTCSR_TOCE_EN                  = 1,     /*!< EN : Timeout counter enabled. UARTSR.OCF is set if an output
                                                     compare event occurs.                                                     */
} LIN_LINTCSR_TOCE_Enum;

/* ========================================================  LINOCR  ========================================================= */
/* ========================================================  LINTOCR  ======================================================== */
/* ========================================================  LINFBRR  ======================================================== */
/* ================================================  LIN LINFBRR FBR [0..3]  ================================================= */
typedef enum {                                  /*!< LIN_LINFBRR_FBR                                                           */
  LIN_LINFBRR_FBR_DIV0_16              = 0,     /*!< DIV0_16 : Fraction(LDIV) = 0                                              */
  LIN_LINFBRR_FBR_DIV1_16              = 1,     /*!< DIV1_16 : Fraction(LDIV) = 1/16                                           */
  LIN_LINFBRR_FBR_DIV2_16              = 2,     /*!< DIV2_16 : Fraction(LDIV) = 2/16                                           */
  LIN_LINFBRR_FBR_DIV3_16              = 3,     /*!< DIV3_16 : Fraction(LDIV) = 3/16                                           */
  LIN_LINFBRR_FBR_DIV4_16              = 4,     /*!< DIV4_16 : Fraction(LDIV) = 4/16                                           */
  LIN_LINFBRR_FBR_DIV5_16              = 5,     /*!< DIV5_16 : Fraction(LDIV) = 5/16                                           */
  LIN_LINFBRR_FBR_DIV6_16              = 6,     /*!< DIV6_16 : Fraction(LDIV) = 6/16                                           */
  LIN_LINFBRR_FBR_DIV7_16              = 7,     /*!< DIV7_16 : Fraction(LDIV) = 7/16                                           */
  LIN_LINFBRR_FBR_DIV8_16              = 8,     /*!< DIV8_16 : Fraction(LDIV) = 8/16                                           */
  LIN_LINFBRR_FBR_DIV9_16              = 9,     /*!< DIV9_16 : Fraction(LDIV) = 9/16                                           */
  LIN_LINFBRR_FBR_DIV10_16             = 10,    /*!< DIV10_16 : Fraction(LDIV) = 10/16                                         */
  LIN_LINFBRR_FBR_DIV11_16             = 11,    /*!< DIV11_16 : Fraction(LDIV) = 11/16                                         */
  LIN_LINFBRR_FBR_DIV12_16             = 12,    /*!< DIV12_16 : Fraction(LDIV) = 12/16                                         */
  LIN_LINFBRR_FBR_DIV13_16             = 13,    /*!< DIV13_16 : Fraction(LDIV) = 13/16                                         */
  LIN_LINFBRR_FBR_DIV14_16             = 14,    /*!< DIV14_16 : Fraction(LDIV) = 14/16                                         */
  LIN_LINFBRR_FBR_DIV15_16             = 15,    /*!< DIV15_16 : Fraction(LDIV) = 15/16                                         */
} LIN_LINFBRR_FBR_Enum;

/* ========================================================  LINIBRR  ======================================================== */
/* ========================================================  LINCFR  ========================================================= */
/* ========================================================  LINCR2  ========================================================= */
/* ===============================================  LIN LINCR2 TBDE [15..15]  ================================================ */
typedef enum {                                  /*!< LIN_LINCR2_TBDE                                                           */
  LIN_LINCR2_TBDE_DIS                  = 0,     /*!< DIS : Delimiter length in break field is 1 bit.                           */
  LIN_LINCR2_TBDE_EN                   = 1,     /*!< EN : Delimiter length in break field is 2 bits.                           */
} LIN_LINCR2_TBDE_Enum;

/* ===============================================  LIN LINCR2 IOBE [14..14]  ================================================ */
typedef enum {                                  /*!< LIN_LINCR2_IOBE                                                           */
  LIN_LINCR2_IOBE_DIS                  = 0,     /*!< DIS : Bit error does not reset LIN state machine.                         */
  LIN_LINCR2_IOBE_EN                   = 1,     /*!< EN : Bit error resets LIN state machine.                                  */
} LIN_LINCR2_IOBE_Enum;

/* ===============================================  LIN LINCR2 IOPE [13..13]  ================================================ */
typedef enum {                                  /*!< LIN_LINCR2_IOPE                                                           */
  LIN_LINCR2_IOPE_DIS                  = 0,     /*!< DIS : Parity error does not reset LIN state machine.                      */
  LIN_LINCR2_IOPE_EN                   = 1,     /*!< EN : Parity error resets LIN state machine.                               */
} LIN_LINCR2_IOPE_Enum;

/* =========================================================  BIDR  ========================================================== */
/* ================================================  LIN BIDR CCS_A [16..16]  ================================================ */
typedef enum {                                  /*!< LIN_BIDR_CCS_A                                                            */
  LIN_BIDR_CCS_A_DISABLE               = 0,     /*!< DISABLE : RX checksum calculated when header is received.                 */
  LIN_BIDR_CCS_A_ENABLE                = 1,     /*!< ENABLE : RX checksum calculated at stop time.                             */
} LIN_BIDR_CCS_A_Enum;

/* ==================================================  LIN BIDR DIR [9..9]  ================================================== */
typedef enum {                                  /*!< LIN_BIDR_DIR                                                              */
  LIN_BIDR_DIR_RECV                    = 0,     /*!< RECV : LINFlexD receives the data and copies it to the DATA
                                                     registers.                                                                */
  LIN_BIDR_DIR_TRANS                   = 1,     /*!< TRANS : LINFlexD transmits the data from the DATA registers.              */
} LIN_BIDR_DIR_Enum;

/* ==================================================  LIN BIDR CCS [8..8]  ================================================== */
typedef enum {                                  /*!< LIN_BIDR_CCS                                                              */
  LIN_BIDR_CCS_ENHANCE                 = 0,     /*!< ENHANCE : Enhanced checksum covering identifier and data fields.
                                                     This is compatible with LIN specification rev. 2.0 and
                                                     higher.                                                                   */
  LIN_BIDR_CCS_CLASSIC                 = 1,     /*!< CLASSIC : Classic checksum covering data field only. This is
                                                     compatible with LIN specification rev. 1.3 and lower.                     */
} LIN_BIDR_CCS_Enum;

/* =========================================================  BDRL  ========================================================== */
/* =========================================================  BDRM  ========================================================== */
/* =========================================================  IFER  ========================================================== */
/* =========================================================  IFMI  ========================================================== */
/* =========================================================  IFMR  ========================================================== */
/* =========================================================  IFCR  ========================================================== */
/* ==================================================  LIN IFCR DIR [9..9]  ================================================== */
typedef enum {                                  /*!< LIN_IFCR_DIR                                                              */
  LIN_IFCR_DIR_RECV                    = 0,     /*!< RECV : LINFlexD receives the data and copy it to the DATA registers.      */
  LIN_IFCR_DIR_TRANS                   = 1,     /*!< TRANS : LINFlexD transmits the data from the DATA register.               */
} LIN_IFCR_DIR_Enum;

/* ==================================================  LIN IFCR CCS [8..8]  ================================================== */
typedef enum {                                  /*!< LIN_IFCR_CCS                                                              */
  LIN_IFCR_CCS_ENHANCE                 = 0,     /*!< ENHANCE : Enhanced checksum covering identifier and data fields.
                                                     This is compatible with LIN specification rev. 2.0 and
                                                     higher.                                                                   */
  LIN_IFCR_CCS_CLASSIC                 = 1,     /*!< CLASSIC : Classic checksum covering data field only. This is
                                                     compatible with LIN specification rev. 1.3 and lower.                     */
} LIN_IFCR_CCS_Enum;

/* ==========================================================  GCR  ========================================================== */
/* =================================================  LIN GCR TDFBM [5..5]  ================================================== */
typedef enum {                                  /*!< LIN_GCR_TDFBM                                                             */
  LIN_GCR_TDFBM_LSB                    = 0,     /*!< LSB : The first bit of transmitted data is the least significant
                                                     bit of the buffer data register (DATA0[0], DATA1[0], DATA2[0],
                                                     DATA3[0], DATA4[0], DATA5[0], DATA6[0], DATA7[0]).                        */
  LIN_GCR_TDFBM_MSB                    = 1,     /*!< MSB : The first bit of transmitted data is the most significant
                                                     bit of the buffer data register (DATA0[7], DATA1[7], DATA2[7],
                                                     DATA3[7], DATA4[7], DATA5[7], DATA6[7], DATA7[7]).                        */
} LIN_GCR_TDFBM_Enum;

/* =================================================  LIN GCR RDFBM [4..4]  ================================================== */
typedef enum {                                  /*!< LIN_GCR_RDFBM                                                             */
  LIN_GCR_RDFBM_LSB                    = 0,     /*!< LSB : The first bit of received data is mapped to least significant
                                                     bit of the buffer data register (DATA0[0], DATA1[0], DATA2[0],
                                                     DATA3[0], DATA4[0], DATA5[0], DATA6[0], DATA7[0]).                        */
  LIN_GCR_RDFBM_MSB                    = 1,     /*!< MSB : The first bit of received data is mapped to the most significant
                                                     bit of the buffer data register (DATA0[7], DATA1[7], DATA2[7],
                                                     DATA3[7], DATA4[7], DATA5[7], DATA6[7], DATA7[7]).                        */
} LIN_GCR_RDFBM_Enum;

/* =================================================  LIN GCR TDLIS [3..3]  ================================================== */
typedef enum {                                  /*!< LIN_GCR_TDLIS                                                             */
  LIN_GCR_TDLIS_NO_INV                 = 0,     /*!< NO_INV : Transmitted data is not inverted.                                */
  LIN_GCR_TDLIS_INV                    = 1,     /*!< INV : Transmitted data is inverted.                                       */
} LIN_GCR_TDLIS_Enum;

/* =================================================  LIN GCR RDLIS [2..2]  ================================================== */
typedef enum {                                  /*!< LIN_GCR_RDLIS                                                             */
  LIN_GCR_RDLIS_NO_INV                 = 0,     /*!< NO_INV : Received data is not inverted.                                   */
  LIN_GCR_RDLIS_INV                    = 1,     /*!< INV : Received data is inverted.                                          */
} LIN_GCR_RDLIS_Enum;

/* ==================================================  LIN GCR STOP [1..1]  ================================================== */
typedef enum {                                  /*!< LIN_GCR_STOP                                                              */
  LIN_GCR_STOP_SP1                     = 0,     /*!< SP1 : One stop bit.                                                       */
  LIN_GCR_STOP_SP2                     = 1,     /*!< SP2 : Two stop bits.                                                      */
} LIN_GCR_STOP_Enum;

/* ========================================================  UARTPTO  ======================================================== */
/* ========================================================  UARTCTO  ======================================================== */
/* =======================================================  LINOUTPHY  ======================================================= */
/* ===============================================  LIN LINOUTPHY TXEN [0..0]  =============================================== */
typedef enum {                                  /*!< LIN_LINOUTPHY_TXEN                                                        */
  LIN_LINOUTPHY_TXEN_DIS               = 0,     /*!< DIS : TX disable.                                                         */
  LIN_LINOUTPHY_TXEN_EN                = 1,     /*!< EN : TX enable.                                                           */
} LIN_LINOUTPHY_TXEN_Enum;

/* ===============================================  LIN LINOUTPHY RXEN [1..1]  =============================================== */
typedef enum {                                  /*!< LIN_LINOUTPHY_RXEN                                                        */
  LIN_LINOUTPHY_RXEN_DIS               = 0,     /*!< DIS : RX disable.                                                         */
  LIN_LINOUTPHY_RXEN_EN                = 1,     /*!< EN : RX enable.                                                           */
} LIN_LINOUTPHY_RXEN_Enum;

/* =============================================  LIN LINOUTPHY TXPU_1K [2..2]  ============================================== */
typedef enum {                                  /*!< LIN_LINOUTPHY_TXPU_1K                                                     */
  LIN_LINOUTPHY_TXPU_1K_DIS            = 0,     /*!< DIS : TX PULL up disable.                                                 */
  LIN_LINOUTPHY_TXPU_1K_EN             = 1,     /*!< EN : TX PULL up enable.                                                   */
} LIN_LINOUTPHY_TXPU_1K_Enum;

/* =============================================  LIN LINOUTPHY TXPU_30K [3..3]  ============================================= */
typedef enum {                                  /*!< LIN_LINOUTPHY_TXPU_30K                                                    */
  LIN_LINOUTPHY_TXPU_30K_DIS           = 0,     /*!< DIS : TX PULL up disable.                                                 */
  LIN_LINOUTPHY_TXPU_30K_EN            = 1,     /*!< EN : TX PULL up enable.                                                   */
} LIN_LINOUTPHY_TXPU_30K_Enum;

/* ==========================================  LIN LINOUTPHY SLOPE_ENHANCE [4..4]  =========================================== */
typedef enum {                                  /*!< LIN_LINOUTPHY_SLOPE_ENHANCE                                               */
  LIN_LINOUTPHY_SLOPE_ENHANCE_OFF      = 0,     /*!< OFF : slope enhance disable.                                              */
  LIN_LINOUTPHY_SLOPE_ENHANCE_ON       = 1,     /*!< ON : slope enhance enable.                                                */
} LIN_LINOUTPHY_SLOPE_ENHANCE_Enum;

/* =======================================================  LININPHY  ======================================================== */
/* ===============================================  LIN LININPHY TXEN [0..0]  ================================================ */
typedef enum {                                  /*!< LIN_LININPHY_TXEN                                                         */
  LIN_LININPHY_TXEN_DIS                = 0,     /*!< DIS : TX disable.                                                         */
  LIN_LININPHY_TXEN_EN                 = 1,     /*!< EN : TX enable.                                                           */
} LIN_LININPHY_TXEN_Enum;

/* ===============================================  LIN LININPHY RXEN [1..1]  ================================================ */
typedef enum {                                  /*!< LIN_LININPHY_RXEN                                                         */
  LIN_LININPHY_RXEN_DIS                = 0,     /*!< DIS : RX disable.                                                         */
  LIN_LININPHY_RXEN_EN                 = 1,     /*!< EN : RX enable.                                                           */
} LIN_LININPHY_RXEN_Enum;

/* ===============================================  LIN LININPHY TXPU [2..2]  ================================================ */
typedef enum {                                  /*!< LIN_LININPHY_TXPU                                                         */
  LIN_LININPHY_TXPU_DIS                = 0,     /*!< DIS : TX PULL up disable.                                                 */
  LIN_LININPHY_TXPU_EN                 = 1,     /*!< EN : TX PULL up enable.                                                   */
} LIN_LININPHY_TXPU_Enum;

/* ===========================================  LIN LININPHY SLOPE_ENHANCE [3..3]  =========================================== */
typedef enum {                                  /*!< LIN_LININPHY_SLOPE_ENHANCE                                                */
  LIN_LININPHY_SLOPE_ENHANCE_OFF       = 0,     /*!< OFF : slope enhance disable.                                              */
  LIN_LININPHY_SLOPE_ENHANCE_ON        = 1,     /*!< ON : slope enhance enable.                                                */
} LIN_LININPHY_SLOPE_ENHANCE_Enum;

/* =======================================================  LINSWITCH  ======================================================= */
/* ======================================================  LINTESTMODE  ====================================================== */
/* =========================================  LIN LINTESTMODE switch_dbg_en [0..0]  ========================================== */
typedef enum {                                  /*!< LIN_LINTESTMODE_switch_dbg_en                                             */
  LIN_LINTESTMODE_switch_dbg_en_DISABLE = 0,    /*!< DISABLE : debug disable.                                                  */
  LIN_LINTESTMODE_switch_dbg_en_ENABLE = 1,     /*!< ENABLE : debug enable.                                                    */
} LIN_LINTESTMODE_switch_dbg_en_Enum;

/* =========================================  LIN LINTESTMODE switch_dbg_sel [1..2]  ========================================= */
typedef enum {                                  /*!< LIN_LINTESTMODE_switch_dbg_sel                                            */
  LIN_LINTESTMODE_switch_dbg_sel_LINC2PAD = 0,  /*!< LINC2PAD : lin controller is selected to be debug by pad.                 */
  LIN_LINTESTMODE_switch_dbg_sel_LINSPHY2PAD = 1,/*!< LINSPHY2PAD : lin slave phy is selected to be debug by pad.              */
  LIN_LINTESTMODE_switch_dbg_sel_LINMPHY2PAD = 2,/*!< LINMPHY2PAD : lin master phy is selected to be debug by pad.             */
} LIN_LINTESTMODE_switch_dbg_sel_Enum;

/* =======================================  LIN LINTESTMODE switch_linc_slave [3..3]  ======================================== */
typedef enum {                                  /*!< LIN_LINTESTMODE_switch_linc_slave                                         */
  LIN_LINTESTMODE_switch_linc_slave_LINSPHY = 0,/*!< LINSPHY : lin controler connected with lins phy.                          */
  LIN_LINTESTMODE_switch_linc_slave_LINMPHY = 1,/*!< LINMPHY : lin controler connected with linm phy.                          */
} LIN_LINTESTMODE_switch_linc_slave_Enum;

/* =======================================  LIN LINTESTMODE switch_monitor_en [4..4]  ======================================== */
typedef enum {                                  /*!< LIN_LINTESTMODE_switch_monitor_en                                         */
  LIN_LINTESTMODE_switch_monitor_en_DISABLE = 0,/*!< DISABLE : monitor disable.                                                */
  LIN_LINTESTMODE_switch_monitor_en_ENABLE = 1, /*!< ENABLE : monitor enable.                                                  */
} LIN_LINTESTMODE_switch_monitor_en_Enum;

/* =======================================================  LINPHYCFG  ======================================================= */
/* =======================================================  LINPHYIE  ======================================================== */
/* =======================================================  LINPHYSR  ======================================================== */
/* =======================================================  LINPHYCLR  ======================================================= */
/* =====================================================  LINPHYMTOCNT  ====================================================== */
/* =====================================================  LINPHYSTOCNT  ====================================================== */


/* =========================================================================================================================== */
/* ================                                            CAN                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CREL  ========================================================== */
/* =========================================================  ENDN  ========================================================== */
/* =========================================================  DBTP  ========================================================== */
/* =========================================================  TEST  ========================================================== */
/* ==========================================================  RWD  ========================================================== */
/* =========================================================  CCCR  ========================================================== */
/* =========================================================  NBTP  ========================================================== */
/* =========================================================  TSCC  ========================================================== */
/* =========================================================  TSCV  ========================================================== */
/* =========================================================  TOCC  ========================================================== */
/* =========================================================  TOCV  ========================================================== */
/* ==========================================================  ECR  ========================================================== */
/* ==========================================================  PSR  ========================================================== */
/* =========================================================  TDCR  ========================================================== */
/* ==========================================================  IR  =========================================================== */
/* ==========================================================  IE  =========================================================== */
/* ==========================================================  ILS  ========================================================== */
/* ==========================================================  ILE  ========================================================== */
/* ==========================================================  GFC  ========================================================== */
/* =========================================================  SIDFC  ========================================================= */
/* =========================================================  XIDFC  ========================================================= */
/* =========================================================  XIDAM  ========================================================= */
/* =========================================================  HPMS  ========================================================== */
/* =========================================================  NDAT1  ========================================================= */
/* =========================================================  NDAT2  ========================================================= */
/* =========================================================  RXF0C  ========================================================= */
/* =========================================================  RXF0S  ========================================================= */
/* =========================================================  RXF0A  ========================================================= */
/* =========================================================  RXBC  ========================================================== */
/* =========================================================  RXF1C  ========================================================= */
/* =========================================================  RXF1S  ========================================================= */
/* =========================================================  RXF1A  ========================================================= */
/* =========================================================  RXESC  ========================================================= */
/* =========================================================  TXBC  ========================================================== */
/* =========================================================  TXFQS  ========================================================= */
/* =========================================================  TXESC  ========================================================= */
/* =========================================================  TXBRP  ========================================================= */
/* =========================================================  TXBAR  ========================================================= */
/* =========================================================  TXBCR  ========================================================= */
/* =========================================================  TXBTO  ========================================================= */
/* =========================================================  TXBCF  ========================================================= */
/* ========================================================  TXBTIE  ========================================================= */
/* ========================================================  TXBCIE  ========================================================= */
/* =========================================================  TXEFC  ========================================================= */
/* =========================================================  TXEFS  ========================================================= */
/* =========================================================  TXEFA  ========================================================= */


/* =========================================================================================================================== */
/* ================                                            RCC                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  CLK_DIV  ======================================================== */
/* ==============================================  RCC CLK_DIV PCLK_DIV [8..9]  ============================================== */
typedef enum {                                  /*!< RCC_CLK_DIV_PCLK_DIV                                                      */
  PCLKDIV_NOTDIV                       = 0,     /*!< NOTDIV : NOTDIV                                                           */
  PCLKDIV_DIV2                         = 1,     /*!< DIV2 : DIV2                                                               */
  PCLKDIV_DIV3                         = 2,     /*!< DIV3 : DIV3                                                               */
  PCLKDIV_DIV4                         = 3,     /*!< DIV4 : DIV4                                                               */
} PCLKDIV_Enum;

/* ===============================================  RCC CLK_DIV CLKSEL [5..6]  =============================================== */
typedef enum {                                  /*!< RCC_CLK_DIV_CLKSEL                                                        */
  CLKSEL_HalfSafeOSC                   = 0,     /*!< HalfSafeOSC : HalfSafeOSC                                                 */
  CLKSEL_SafeOSC                       = 1,     /*!< SafeOSC : SafeOSC                                                         */
  CLKSEL_ROSC48                        = 2,     /*!< ROSC48 : ROSC48                                                           */
  CLKSEL_PLL                           = 3,     /*!< PLL : PLL                                                                 */
} CLKSEL_Enum;

/* ===========================================  RCC CLK_DIV CLK_DIV_FACTOR [0..3]  =========================================== */
typedef enum {                                  /*!< RCC_CLK_DIV_CLK_DIV_FACTOR                                                */
  CLKDIV_DIV2                          = 1,     /*!< DIV2 : Clock frequency dived by 2                                         */
  CLKDIV_DIV4                          = 2,     /*!< DIV4 : Clock frequency dived by 4                                         */
  CLKDIV_DIV6                          = 3,     /*!< DIV6 : Clock frequency dived by 6                                         */
  CLKDIV_DIV8                          = 4,     /*!< DIV8 : Clock frequency dived by 8                                         */
  CLKDIV_DIV10                         = 5,     /*!< DIV10 : Clock frequency dived by 10                                       */
  CLKDIV_DIV12                         = 6,     /*!< DIV12 : Clock frequency dived by 12                                       */
  CLKDIV_DIV14                         = 7,     /*!< DIV14 : Clock frequency dived by 14                                       */
  CLKDIV_DIV16                         = 8,     /*!< DIV16 : Clock frequency dived by 16                                       */
  CLKDIV_DIV18                         = 9,     /*!< DIV18 : Clock frequency dived by 18                                       */
  CLKDIV_DIV20                         = 10,    /*!< DIV20 : Clock frequency dived by 20                                       */
  CLKDIV_DIV22                         = 11,    /*!< DIV22 : Clock frequency dived by 22                                       */
  CLKDIV_DIV24                         = 12,    /*!< DIV24 : Clock frequency dived by 24                                       */
  CLKDIV_DIV26                         = 13,    /*!< DIV26 : Clock frequency dived by 26                                       */
  CLKDIV_DIV28                         = 14,    /*!< DIV28 : Clock frequency dived by 28                                       */
  CLKDIV_DIV30                         = 15,    /*!< DIV30 : Clock frequency dived by 30                                       */
} CLKDIV_Enum;

/* =====================================================  CLK_GATE_APB  ====================================================== */
/* =====================================================  CLK_GATE_AHB  ====================================================== */
/* =================================================  SYSTEM_SOFTWARE_RESET  ================================================= */
/* ==================================================  MODULE_SW_RESET_APB  ================================================== */
/* ==================================================  MODULE_SW_RESET_AHB  ================================================== */
/* =======================================================  PLL_CFG1  ======================================================== */
/* ===========================================  RCC PLL_CFG1 PLL_REF_DIV [30..31]  =========================================== */
typedef enum {                                  /*!< RCC_PLL_CFG1_PLL_REF_DIV                                                  */
  PLL_REF48M_DIV_DIV2                  = 0,     /*!< DIV2 : ROSC48MHz / 2 as PLL reference clock                               */
  PLL_REF48M_DIV_DIV4                  = 1,     /*!< DIV4 : ROSC48MHz / 4 as PLL reference clock                               */
  PLL_REF48M_DIV_DIV8                  = 2,     /*!< DIV8 : ROSC48MHz / 8 as PLL reference clock                               */
  PLL_REF48M_DIV_DIV16                 = 3,     /*!< DIV16 : ROSC48MHz / 16 as PLL reference clock                             */
} PLL_REF48M_DIV_Enum;

/* ============================================  RCC PLL_CFG1 PLL_PREDIV [8..9]  ============================================= */
typedef enum {                                  /*!< RCC_PLL_CFG1_PLL_PREDIV                                                   */
  PLL_PREDIV_DIV1                      = 0,     /*!< DIV1 : Fpfd=F_input/1                                                     */
  PLL_PREDIV_DIV2                      = 1,     /*!< DIV2 : Fpfd=F_input/2                                                     */
  PLL_PREDIV_DIV4                      = 2,     /*!< DIV4 : Fpfd=F_input/4                                                     */
  PLL_PREDIV_DIV8                      = 3,     /*!< DIV8 : Fpfd=F_input/8                                                     */
} PLL_PREDIV_Enum;

/* ============================================  RCC PLL_CFG1 PLL_POSTDIV [4..5]  ============================================ */
typedef enum {                                  /*!< RCC_PLL_CFG1_PLL_POSTDIV                                                  */
  RCC_PLL_CFG1_PLL_POSTDIV_DIV1        = 0,     /*!< DIV1 : F_out=Fvco/1                                                       */
  RCC_PLL_CFG1_PLL_POSTDIV_DIV2        = 1,     /*!< DIV2 : F_out=Fvco/2                                                       */
  RCC_PLL_CFG1_PLL_POSTDIV_DIV4        = 2,     /*!< DIV4 : F_out=Fvco/4                                                       */
  RCC_PLL_CFG1_PLL_POSTDIV_DIV8        = 3,     /*!< DIV8 : F_out=Fvco/8                                                       */
} RCC_PLL_CFG1_PLL_POSTDIV_Enum;

/* =======================================================  PLL_CFG2  ======================================================== */
/* =========================================  RCC PLL_CFG2 PLL_LDOVREFSEL [28..30]  ========================================== */
typedef enum {                                  /*!< RCC_PLL_CFG2_PLL_LDOVREFSEL                                               */
  PLL_LDOVREF_Vref2p60                 = 0,     /*!< Vref2p60 : 2.60V                                                          */
  PLL_LDOVREF_Vref2p65                 = 1,     /*!< Vref2p65 : 2.65V                                                          */
  PLL_LDOVREF_Vref2p70                 = 2,     /*!< Vref2p70 : 2.70V                                                          */
  PLL_LDOVREF_Vref2p75                 = 3,     /*!< Vref2p75 : 2.75V                                                          */
  PLL_LDOVREF_Vref2p80                 = 4,     /*!< Vref2p80 : 2.80V                                                          */
  PLL_LDOVREF_Vref2p85                 = 5,     /*!< Vref2p85 : 2.85V                                                          */
  PLL_LDOVREF_Vref2p90                 = 6,     /*!< Vref2p90 : 2.90V                                                          */
  PLL_LDOVREF_Vref2p95                 = 7,     /*!< Vref2p95 : 2.95V                                                          */
} PLL_LDOVREF_Enum;

/* =============================================  RCC PLL_CFG2 PLL_ICP [10..13]  ============================================= */
typedef enum {                                  /*!< RCC_PLL_CFG2_PLL_ICP                                                      */
  PLL_ICP_ICP1p5625                    = 0,     /*!< ICP1p5625 : 1.5625 uA                                                     */
  PLL_ICP_ICP4p6875                    = 1,     /*!< ICP4p6875 : 4.6875uA                                                      */
  PLL_ICP_ICP7p8125                    = 2,     /*!< ICP7p8125 : 7.8125uA                                                      */
  PLL_ICP_ICP10p9375                   = 3,     /*!< ICP10p9375 : 10.9375uA                                                    */
  PLL_ICP_ICP14p0625                   = 4,     /*!< ICP14p0625 : 14.0625uA                                                    */
  PLL_ICP_ICP17p1875                   = 5,     /*!< ICP17p1875 : 17.1875uA                                                    */
  PLL_ICP_ICP20p3125                   = 6,     /*!< ICP20p3125 : 20.3125A                                                     */
  PLL_ICP_ICP23p4375                   = 7,     /*!< ICP23p4375 : 23.4375uA                                                    */
  PLL_ICP_ICP3p125                     = 8,     /*!< ICP3p125 : 3.125uA                                                        */
  PLL_ICP_ICP9p375                     = 9,     /*!< ICP9p375 : 9.375uA                                                        */
  PLL_ICP_ICP15p625                    = 10,    /*!< ICP15p625 : 15.625uA                                                      */
  PLL_ICP_ICP21p875                    = 11,    /*!< ICP21p875 : 21.875uA                                                      */
  PLL_ICP_ICP28p125                    = 12,    /*!< ICP28p125 : 28.125uA                                                      */
  PLL_ICP_ICP34p375                    = 13,    /*!< ICP34p375 : 34.375uA                                                      */
  PLL_ICP_ICP40p625                    = 14,    /*!< ICP40p625 : 40.625uA                                                      */
  PLL_ICP_ICP46p875                    = 15,    /*!< ICP46p875 : 46.875uA                                                      */
} PLL_ICP_Enum;

/* ============================================  RCC PLL_CFG2 PLL_CCOBAND [9..9]  ============================================ */
typedef enum {                                  /*!< RCC_PLL_CFG2_PLL_CCOBAND                                                  */
  PLL_CCOBAND_Band400M                 = 0,     /*!< Band400M : 400MHz band                                                    */
  PLL_CCOBAND_Band700M                 = 1,     /*!< Band700M : 700MHz- band                                                   */
} PLL_CCOBAND_Enum;

/* =============================================  RCC PLL_CFG2 PLL_KVCO [8..8]  ============================================== */
typedef enum {                                  /*!< RCC_PLL_CFG2_PLL_KVCO                                                     */
  PLL_KVCO_KVCO300M                    = 0,     /*!< KVCO300M : 300MHz/V                                                       */
  PLL_KVCO_KVCO400M                    = 1,     /*!< KVCO400M : 400MHz/V                                                       */
} PLL_KVCO_Enum;

/* ===========================================  RCC PLL_CFG2 PLL_LPF_RSEL [1..3]  ============================================ */
typedef enum {                                  /*!< RCC_PLL_CFG2_PLL_LPF_RSEL                                                 */
  PLL_LPFR_LPFR5K                      = 0,     /*!< LPFR5K : 5K                                                               */
  PLL_LPFR_LPFR8K                      = 1,     /*!< LPFR8K : 8K                                                               */
  PLL_LPFR_LPFR13K                     = 2,     /*!< LPFR13K : 13K                                                             */
  PLL_LPFR_LPFR18K                     = 3,     /*!< LPFR18K : 18K                                                             */
  PLL_LPFR_LPFR23K                     = 4,     /*!< LPFR23K : 23K                                                             */
  PLL_LPFR_LPFR31p4K                   = 5,     /*!< LPFR31p4K : 31.4K                                                         */
  PLL_LPFR_LPFR41p4K                   = 6,     /*!< LPFR41p4K : 41.4K                                                         */
  PLL_LPFR_LPFR51p4K                   = 7,     /*!< LPFR51p4K : 51.4K                                                         */
} PLL_LPFR_Enum;

/* =============================================  RCC PLL_CFG2 PLL_LPF_C [0..0]  ============================================= */
typedef enum {                                  /*!< RCC_PLL_CFG2_PLL_LPF_C                                                    */
  RCC_PLL_CFG2_PLL_LPF_C_LPFC1p2PF     = 0,     /*!< LPFC1p2PF : 1.2pF                                                         */
  RCC_PLL_CFG2_PLL_LPF_C_LPFC2p3PF     = 1,     /*!< LPFC2p3PF : 2.3pF                                                         */
} RCC_PLL_CFG2_PLL_LPF_C_Enum;

/* ========================================================  PLL_DBG  ======================================================== */
/* ==========================================================  CIR  ========================================================== */
/* =======================================================  EXTAL_CFG  ======================================================= */
/* ======================================================  RST_REASON  ======================================================= */
/* ========================================  RCC RST_REASON RST_REASON_STATUS [0..3]  ======================================== */
typedef enum {                                  /*!< RCC_RST_REASON_RST_REASON_STATUS                                          */
  RST_REASON_POR                       = 1,     /*!< POR : power on reset                                                      */
  RST_REASON_WWDG                      = 2,     /*!< WWDG : watch dog reset                                                    */
  RST_REASON_SYSSOFT                   = 3,     /*!< SYSSOFT : system software reset                                           */
  RST_REASON_CORE                      = 4,     /*!< CORE : core reset                                                         */
  RST_REASON_OTPADC                    = 7,     /*!< OTPADC : over temperature reset by ADC                                    */
  RST_REASON_V50OV                     = 8,     /*!< V50OV : ldo50 over voltage reset                                          */
  RST_REASON_V50UV                     = 9,     /*!< V50UV : ldo50 under voltage reset                                         */
  RST_REASON_V15OV                     = 10,    /*!< V15OV : ldo15 over voltage reset                                          */
  RST_REASON_V15UV                     = 11,    /*!< V15UV : ldo15 under voltage reset                                         */
  RST_REASON_OPTBG                     = 12,    /*!< OPTBG : over temperature reset by BG                                      */
  RST_REASON_IWDG                      = 13,    /*!< IWDG : iwdg                                                               */
} RST_REASON_Enum;

/* ======================================================  LDO1P5_CFG  ======================================================= */
/* ======================================================  LDO5P0_CFG  ======================================================= */
/* ======================================================  BG_OTP_CFG  ======================================================= */
/* =====================================================  VT_RST_ENABLE  ===================================================== */
/* ======================================================  INT_STATUS  ======================================================= */
/* ======================================================  INT_ENABLE  ======================================================= */
/* =======================================================  INT_CLEAR  ======================================================= */
/* =======================================================  BIAS_CFG  ======================================================== */
/* ========================================================  SSC_CFG  ======================================================== */
/* ========================================================  CLK_MUX  ======================================================== */
/* =============================================  RCC CLK_MUX ADC_DIV [16..17]  ============================================== */
typedef enum {                                  /*!< RCC_CLK_MUX_ADC_DIV                                                       */
  ADCCLK_DIV_NOTDIV                    = 0,     /*!< NOTDIV : NOTDIV                                                           */
  ADCCLK_DIV_DIV2                      = 1,     /*!< DIV2 : DIV2                                                               */
  ADCCLK_DIV_DIV3                      = 2,     /*!< DIV3 : DIV3                                                               */
  ADCCLK_DIV_DIV4                      = 3,     /*!< DIV4 : DIV4                                                               */
} ADCCLK_DIV_Enum;



/* =========================================================================================================================== */
/* ================                                           eDIAG                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  STS  ========================================================== */
/* ==========================================================  CR  =========================================================== */
/* ==========================================================  CR1  ========================================================== */
/* ==========================================================  MUX  ========================================================== */
/* ==========================================================  IER  ========================================================== */
/* ==========================================================  SR  =========================================================== */
/* ==========================================================  CLR  ========================================================== */
/* =========================================================  FILT  ========================================================== */
/* =======================================================  FILT_DIA  ======================================================== */


/* =========================================================================================================================== */
/* ================                                           ADC0                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR0  ========================================================== */
/* ==========================================================  CR1  ========================================================== */
/* ==========================================================  OTP  ========================================================== */
/* ==========================================================  SR  =========================================================== */
/* ==========================================================  IER  ========================================================== */
/* ==========================================================  CIR  ========================================================== */
/* =========================================================  CHCFG  ========================================================= */
/* =========================================================  DATA  ========================================================== */
/* =========================================================  TDATA  ========================================================= */
/* =========================================================  TEST  ========================================================== */

/** @} */ /* End of group EnumValue_peripherals */


#ifdef __cplusplus
}
#endif

#endif /* R2401_H */


/** @} */ /* End of group R2401 */

/** @} */ /* End of group  */
